2017 Devices for Integrated Circuit (DevIC), 23-24 March, 2017, Kalyani, India 326

Low-Noise CMOS Differential-amplifier design

using Automated-design methodology
Chabungbam Lison Singh, Ashim Jyoti Gogoi, Chabungbam Anandini, K. L. Baishnab
Dept. of Electronics and Communication Engineering,
NIT Silchar, 788010-India
[email protected], [email protected]

Abstract— The increasing complexity of Integrated Circuits procedure which considered the circuit performance
(ICs) and requirement of accurate design, made the automated specifications as objective function subject to a set of
design technique a necessity. The design of analog circuit constraints. This method is highly reliable and accurate in
involves satisfying different sets of constraints along with designing analog circuit. Examples: - ASTRX/OBLX [6],
determination of optimal design parameters value that result in DELIGHT.SPICE [7], etc.
optimized performance of the circuit. Presence of noise in a
P. R. A. Vural [8] introduces the application of Swarm
circuit affect its performance, hence proper analysis become a
Intelligence in optimal sizing of CMOS analog circuits. B. P.
necessity in realization a high performance circuit (low-noise De [9] presents an ALCPSO-based design methodology for
circuit). This paper presents a new automated design optimal designing of n-channel input folded-cascode Op-amp
methodology of designing a low-noise Differential-amplifier and complementary metal oxide semiconductor two-stage
with current mirror load, with both MOS transistor length and comparator with P-type metal oxide semiconductor. O. Jack
width optimization, considering various performance [10] performs the analysis of thermal and flicker noises of
specifications as constraints. Nature-inspired heuristic BSIM3 transistor model using ⁄ analysis methodology.
optimization algorithm has an ability to give acceptable From, the available literature we can conclude that design of
approximate solution within a reasonable time. Here, Human- CMOS circuit with thermal noise minimization is lacking in
Behavior Based Particle Swarm Optimization (HPSO) the literature.
algorithm is used as an intended candidate to determine
Presence of noise in a circuit limits its ability to process
optimal design parameters value to realize a low-noise minimum level of signal leading in deterioration of
amplifier with minimum total circuit area. The MATLAB and performance of the circuit. Hence, realization of high
CADENCE tool is linked to verify the purposed automated performance circuit requires proper analysis of noise and
design methodology using UMC 0.18 μm parameters derivation of methodology to minimize noise in the circuit. Not
technology. Further, the performance of the purposed much literature is available in the field of automated design
automated design methodology is compared with previous methodology incorporating noise as design specification. In
design methodology to check its efficiency in terms of speed, this paper, noise is incorporated as performance parameters in
time and robustness. addition to other circuit performance parameters, which gives
the advantages of considering both length and width of MOS
Keywords—HPSO; Differential amplifier; Thermal noise; transistor as design variables. The presented methodology not
Cadence; HPSO only optimized the noise and total circuit area but also give an
in-sight into the trade-off between the noise and other circuit
I. INTRODUCTION
specifications. The paper is organized as follows: Section 2
Particle Swarm Optimization (PSO) [1,2] is an describes the formulation of design problem for the circuit
optimization algorithm that involves a population of particles using proposed design methodology. Section 3 shows the
and converges to the optimal solution through local interaction determination of global optimal solutions and validation
of particles with each other and global interaction of process. Finally, section 4 gives the conclusion of the paper.
environment with the particles. PSO is very popular and is
II. HPSO-BASED DESIGN PROCEDURE
very suitable to perform optimization problem in complex
science and engineering field due to ease of implementation A. HPSO Algorithm
and has highest number of publication [3]. The automated In 2014 H. Liu introduced variants of PSO, known as
design methodologies are of two types: (i) Knowledge-based HPSO. HPSO eliminates the condition of easy trapping of the
and (ii) Optimization-based method. The knowledge-based particles in the local optima solutions due to decreasing
design involves the expertness of designer to synthesis a diversity in the population in the original PSO. To maintain
design rule. The knowledge-based design is tedious job, take diversity in the population, a parameter known as global worst
long time and limited to few topologies. Examples include:- particle is introduced in the velocity update equation, which
IDAC [4], OASYS [5], etc. The optimization-based design, on helps in maintaining balance between the exploration and
the other hand involves deriving an automated design

978-1-5090-4724-6/17/$31.00 ©2017

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 2017 Devices for Integrated Circuit (DevIC), 23-24 March, 2017, Kalyani, India 327

exploitation search ability. Further, the two acceleration remaining performance specifications. Using the optimal
coefficients are removed from the velocity update equation length of MOS transistor, optimal aspect ratio of MOS
thereby bringing down the complexity of the algorithm. The transistor is determined that satisfies all the remaining
detail description of the HPSO algorithm is given in [11].
constraints.
B. Formulation of Design Problem TABLE I Components information for HPSO-based design procedure
Design of analog circuit involves selection of optimal Components Value
transistor dimension that results in optimized performance of Supply voltage (V): VDD, VSS 1.8, -1.8
desired or required circuit performance specifications. Sizing Fabrication technology dependent (V) 0.42, -0.42
technique, a part of analog circuit design, is a constructive : VTN, VPN
mapping process that maps the circuit performance Fabrication technology dependent 355, 75
(µA/V2): KN, KP
specifications (objectives or constraints) into the circuit design
Temperature 300o K
parameters. In other words, design parameters value is used to
evaluate performance of such circuit specifications [12]. Thus TABLE II Constraints for the HPSO-based design procedure
to get the optimized performance of a circuit, the design Design constraints [8] Ranges
parameters are determined under different conditions of , k=1-6 100 3
constraint and multi-objectives. In this paper, we design a low- 3.5
Lk, k=1-6 (μm
noise CMOS differential-amplifier with current-mirror load,
SR (V/µs) 10
shown in figure 1, via optimizing several required CL (pF) 4
performance specifications with the main objective of AV (dB) 40
minimizing circuit area and thermal noise using HPSO. ICMR (V) 1.8 1.5

For designing low-noise differential amplifier with current

mirror load, the following circuit performance parameters
considered are constraints [13,14]: Thermal noise, Slew rate,
Frequency response, Lower and Upper Input Common-Mode
Ratio (ICMR), Small-signal voltage gain. While dimension of
MOS transistor, load capacitance are considered as design
parameters.
1. Thermal noise of a differential-amplifier [13]

2 2
V = 8kT 

1
+
2K3' W ID3 
L3 ( ) (1)

n,in
3  2K' W I
 1 L1 D1 ( )
' W
2K1
L 1
ID1 

( )
2. Slew Rate (SR), determination of [14]
I
SR = D 5 (2)
CL

Fig. 1 Differential-amplifier with current mirror load 3. Frequency response (f-3dB), determination of
[14]
The HPSO-based design procedure starts with two type of 1
f − 3 dB = (3)
information: 1st information defines the components such as R out C L
technology, power supply and temperature, as shown in table
I. 2nd information defines the optimal range for each design 4. Upper ICMR (VIC(max), determine [14]
specifications and design parameters as shown in table II. We
V IC (m ax) = V DD − V SG 3 + VTN 1 (4)
construct a particle vector structure for the circuit [8] and the
2ID5
particle vector structure is divided into two parts: 1st particle
vector structure is constructed to determine optimal length of
(W L ) 3
=
K (V SG 3 + V T P )
'
P
(5)

MOS transistor that results in minimization of thermal noise.

And, the 2nd particle vector structure is constructed for the 5. Lower ICMR, determine [14]

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 2017 Devices for Integrated Circuit (DevIC), 23-24 March, 2017, Kalyani, India 328

VIC (min) = VSS + VDS 5 (sat) + VGS 1 (6) noise, after 25 iterations taking a minimum time of 0.221 sec,
as shown in figure 3. The optimal value of the MOS transistor
2ID5
(W L ) =
K N' V DS
5
2
5 (sat)
(7) length and the thermal noise obtained by the HPSO algorithm
are given in tables III and IV.
A Cost Function for the circuit is defined that the proposed
design methodology must satisfy. In other word, CF is main
objective for the selected or constructed circuit that is to be
satisfied, which is defined as thermal noise and total circuit
area minimization, i.e.
C F1 = m in(V n2, in ) (8)
T
C F 2 = m in (  W k × L k ) , T = 6 (9 )
k =1

Targeted CFs are ≤ 50 ⁄√ 10 and

≤ 300 .
Considering the equation (1) describing the thermal noise
of differential amplifier, MOS transistors M1 and M 3 length
are considered as design variables. The initial population
matrix for the HPSO-based design procedure is taken as 10 ×
2 , where row, 10 represents the number of particles
(solutions) in the swarm and column, 2 represents the
dimensions (design variables) of particle vector. The
corresponding particle vector structure for satisfying the
constraints of thermal noise is expressed as
X diff − amp , noise = [ L1 , L2 ] (10)
Where, L1 and L3 are the length of the MOS transistors M1 and
M3 , respectively.
Similarly, considering eqns. (2-8), width of all MOS
transistors are considered as design variables, i.e. W1 -W6. The
initial population matrix is taken as 10 × 6, where rows, 10
represents the number of particles in the swarm and column, 6
represents the dimension (design specifications) of particle
vector. The corresponding particle vector structure is Fig. 2 Flow-chart of a HPSO-based design procedure
expressed as

Xdiff −amp,per_specf = [SR,CL ,f−3dB ,VIC (min), Av ,VIC (max)] (11)

Where, SR is the slew rate, CL is the load capacitance, f-3dB is
the cut-off frequency, VIC(min) is the lower ICMR, Av is the
voltage gain, VIC(max) is the upper ICMR.
The system architecture of a HPSO-based design
procedure for designing a Low- noise Differential amplifier is
shown in figure 2.
III. OPTIMIZATION AND CADENCE RESULTS

A. Optimization using HPSO

Considering eqns. (1), thermal noise optimization is
performed by the HPSO-based design procedure to obtain the
optimal length of MOS transistors that result in minimization
of thermal noise in the circuit. An optimal ranges for length is
taken as ≤ 3.5 µm [8] and value for rest of the parameters are
taken as = 1.38 × 10 ⁄ , = 355 ⁄ , =
75 ⁄ [12] and each width is assumed between 1-30 µm. Fig. 3 Thermal noise optimization using HPSO
The HPSO optimization algorithm is run for 50 iterations and
it able to converge to the optimal solution, minimized thermal

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 2017 Devices for Integrated Circuit (DevIC), 23-24 March, 2017, Kalyani, India 329

Now, rests of the performance specifications are optimized TABLE IV Comparison of design specifications for different algorithm-based
design procedures
through HPSO-based design procedure to obtain value of
width of MOS transistors using optimal length of MOS Design Specifications IPSO [8 ] HPSO
transistors with main aim of minimizing total area of the criteria
circuit. And we select the length of MOS transistor M5 and M6 SR (V/µs) 10 22.4 11.9
as 1.4 µm [8] and ran the HPSO optimization algorithm for 50 CL (pF) 4 5 4.4
iterations to minimize the total circuit while satisfying all the AV (dB) 42 41.93
40
constraints. It can be seen that HPSO algorithm is able to
100 100 149.18
converge to the optimal solution after 20 iterations, figure 4,
VIC(max) ≤ 1.8 1.4 1.15
taking a minimum time of 0.211 sec. The efficiency of the
(V)
HPSO-based design procedure in obtaining global optimal
VIC(min) (V) 1.5 -0.8 -0.33
solutions with respect to IPSO-based design procedure is
⁄ ≤ 50 at 10 - 21.03
given in tables III and table IV, respectively. ,
MHz
Total area ≤300 296 94.19
(µm2)

Fig. 4 MOS Transistor Area optimization using HPSO

B. Cadence Simulation
To validate the purpose design procedure, the differential
amplifier with current mirror load is redesigned in the Fig. 5 Noise analysis plot of a Differential-amplifier with current mirror load
CADENCE simulation tools with UMC 0.18 µm parameters (cadence simulation).
technology using the optimal design parameters value. Figure
5 shows the shows the noise analysis plot of the differential- IV. CONCLUSION
amplifier obtained through CADENCE simulation and it can This paper presents a new HPSO-based design
be seen that minimization of thermal noise occurs at higher methodology for designing Differential amplifier with current
frequencies [13]. Hence, the HPSO-based design procedure is mirror load. The presented design methodology was able to
able to obtain the optimal value of design parameters that obtain much better optimal solutions, in terms of design
result in satisfaction of both constraints and objective variables and satisfying set of constraints taking a minimum
functions of the Differential-amplifier. time of 0.432 second, thereby proving its better efficiency
with respect another well-known IPSO-based design method.
TABLE III Comparison of design parameters for different algorithm-based In addition to minimization of noise in the circuit, the total
design procedures
circuit area was also minimized much lower as compared to
Design criteria IPSO [8] HPSO
other automated design method. Finally, we simulate the
W1,W2 (µm) 29.4 7.40
noise analysis in the CADENCE with the optimal design
W3,W4 (µm) 11.3 6.11 variable values to validate our presented automated design
W5,W6 (µm) 2.8 2.8 procedure. For future work, our presented design
L1,L2 (µm) 3.5 3.056 methodology can be used to derive multi-objective
L3,L4 (µm) 3.5 3.3654 optimization problems in higher-order amplifier.

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 2017 Devices for Integrated Circuit (DevIC), 23-24 March, 2017, Kalyani, India 330

Acknowledgment [7] W. Nye, D. C. Riley, A. Sangiovanni-Vincentelli, L. A. Tits, “

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