Electronic Instrumentation & Measurements

High-Speed Digital I/O and Logic Analyzer

-- NI 655x series

Chia-Ling Wei（魏嘉玲）, Professor

Department of Electrical Engineering,
National Cheng Kung University, Tainan, Taiwan
Outline

 Fundamentals of Digital I/O and Logic Analyzers

1.1 Voltage Levels
1.1.1 Single-ended Digital I/O Voltage Levels
1.1.2 Differential Digital I/O Voltage Levels
1.2 Logic Level Families
1.2.1 Single-Ended Logic Families
1.2.2 Differential Logic Families
1.3 Clocked Digital Generation, Acquisition, and Compare States
1.3.1 Choosing the Proper Digital Drive Type
1.3.2 Digital Drive States (0, 1, and Z)
1.3.3 Digital Compare States (L, H, and X)

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Outline
1.4 Digital Termination
1.4.1 Transmission Lines
1.4.2 Characteristic Impedance
1.4.3 Signal Reflections
1.4.4 Types of Termination
 Common Terminology for Digital I/O
2.1 Eye Diagram Analysis
2.1.1 Jitter
2.1.2 Hold and Setup Time
2.1.3 Drift
2.1.4 Eye Diagram
2.1.5 Example of Digital Signals Timing Analysis
2.2 Double Data Rate

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Outline

 Logic Analyzer Application – NI 655x Series

3.1 Logic Analyzer

3.2 Features of NI655x

3.3 Advanced Acquisition Timing Options

3.4 Diverse Acquisition Triggering Choices

3.5 Powerful Visualization Programming Features

3.6 Extensive Expansion and Integration Capabilities

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 Fundamentals of
Digital I/O and Logic Analyzers

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1.1 Voltage Levels

 Voltage levels for a digital IO device are what defines how a device
determines a valid logic state (logic high level or logic low level).

 Voltage levels are defined differently depending on whether you

are discussing a single-ended or differential device.

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1.1.1 Single-ended Digital I/O Voltage Levels

 Voltage levels are usually specified in terms of the voltage placed

 on the output terminal when driving a high level signal or when driving a low
level signal
 on the input terminal for the signal to be recognized as a high or low level signal.
 In general, the single-ended voltage levels are defined as follows:
 Generation Voltage High Level (VOH) - the voltage produced at the channel
electronics when the Pattern Generation Engine generates a binary one. When
configured for open collector generation, Generation Voltage High Level is
equivalent to setting the data channel to a high-impedance state.
 Generation Voltage Low Level (VOL) — the voltage produced at the channel
electronics when the Pattern Generation Engine generates a binary zero.
 Acquisition Voltage High Level (VIH) —the voltage level at or above which the
Pattern Acquisition Engine senses a binary one.
 Acquisition Voltage Low Level (VIL) - the voltage level at or below which the
Pattern Acquisition Engine senses a binary zero.

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Voltage level Compatibility

 When connecting a digital module to a device under test (DUT), you

must ensure that the interface voltage levels are compatible.

Fig. 1-1 Explanation of Single-ended Digital Voltage Levels

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Voltage level Compatibility

 Configure the digital device such that the following conditions are
met:
· Generation Voltage High Level ≥ DUT VIH
· Generation Voltage Low Level ≤ DUT VIL
· Acquisition Voltage High Level ≤ DUT VOH
· Acquisition Voltage Low Level ≥ DUT VOL
· Acquisition Voltage High Level > Acquisition Voltage Low Level

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Noise Immunity Margin (NIM)

 The extra margin between the voltage level being driven by the
source and the voltage level required at the destination is known as
the noise immunity margin (NIM).

 The NIM indicates the amount of noise tolerable on the connecting

cable with a data bit being received in correctly.

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1.1.2 Differential Digital I/O Voltage Levels

 Differential signals are transmitted in parity: two conductors,

referenced to each other, are used to transmit data.

 For the differential digital signal to be interpreted as a binary 0, the

signal must be less than its complementary signal by more than a
particular value, VTH.

Fig. 1-2

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 Differential Digital I/O Voltage Levels
 In general, the differential voltage levels are defined as follows:
 Differential Output Voltage (VOD)—the difference in voltage between the
positive and complementary conductors of a differential transmission.

 Offset Voltage (VOS)—the common mode of the differential signal.

 Threshold Voltage (VTH)—the differential voltage threshold at which the

receiver registers a valid logic state.

 Input Voltage Range (VRANGE)—the absolute voltage, referenced to common,

allowed by the receiver.

Fig. 1-2

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Advantage of Differential Voltage Transmission

 Higher noise immunity

 Immune to the noise coupling to both terminals

 Allow much smaller signal swings, which let you transmit data
 much farther

 much faster, and

 at a fraction of the power

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1.2 Logic Level Families

 Logic families are groups of logic circuits with standardized voltage

levels that constitute a voltage high or low level.

 All circuits within a logic family are compatible with other circuits
within that family, since they share the same characteristics.

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1.2.1 Single-Ended Logic Families

Table 1-1 Common Single-ended Logic Families

Logic Family Voltage Range

CMOS 0 – 5V

TTL 0 – 5V

LVTTL 0 – 3.3V

LVCMOS 0 – 3.3V

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1.2.2 Differential Logic Families:
Low-Voltage Differential Signaling (LVDS)
 Low-Voltage Differential Signaling (LVDS)
Low-voltage differential signaling (LVDS) is a low-noise, low-power, low-
amplitude differential method for high-speed digital data transfer.

Fig. 1-3 Diagram of the typical LVDS circuit

 A voltage of approximately 350 mV (3.5 mA x 100 Ω) is established.

 The polarity of differential voltage depends on the direction of the current.
 The receiver recognizes a positive differential voltage signal as a logic high
level (1) and a negative differential voltage as a logic low level (0).

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1.2.2 Differential Logic Families:
Low-Voltage Positive Emitter-Coupled Logic (LVPECL)

 LVPECL circuits are a type of ECL circuit that require a pair of

signal lines for each channel.

 The differential transmission scheme is less susceptible to common-

mode noise than single-ended transmission methods. LVPECL
circuits are designed for use with VCC = 3 V or 3.3 V.

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Emitter-Coupled Logic
 Emitter-Coupled Logic is based on
the use of a multi-input differential
amplifier to amplify and combine the
digital signals, and emitter followers
to adjust the dc voltage levels.
 As a result, none of the transistors in
the gate ever enter saturation, nor do
they ever get turned completely off.
The transistors remain entirely within
their active operating regions at all
times.
 As a result, the transistors do not
have a charge storage time to contend
with, and can change states much
more rapidly. Thus, the main Fig. 1-4
advantage of this type of logic gate is
extremely high speed.
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1.3 Clocked Digital States

 Choosing the Proper Digital Drive Type

 Digital Drive States (0, 1, and Z)

 Digital Compare States (L, H, and X)

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1.3.1 Choosing the Proper Digital Drive Type

 Single-ended high-speed digital waveform generator/analyzers

support two drive types
 active drive: a channel generates the voltage High Level for logic 1, and
the voltage Low Level for logic 0

 open collector: a channel goes to the high-impedance state for logic 1,

and external pull-up resistors are typically used to force a voltage for
the logic high state. Vdd

output pin

Fig. 1-5 Open collector configuration

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1.3.2 Digital Drive States (0, 1, and Z)
 Other than 1 and 0, another logic state is ‘Z’ also referred to as “tri-state”

 the state where the driver is not driving any value at all

 the potential of the wire is floating at an unknown voltage level

 used to test digital lines that can be driven by multiple transmitters

 E.g. CPU-memory data bus, open-collector configuration

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Initial and Idle States
 The Initial state configures the state of the data generation channels
after a session has been configured but before the device starts
generating the waveform.
 useful while the device is waiting for a Start trigger

 The Idle state configures the state of the data generation channels
after the waveform generation has begun and the generation has
paused or stopped.
 The Initial state and Idle state are per channel selectable from
 1— Drive the channel to a high level.
 0— Drive the channel to a low level.
 X— Hold last value/Leave the channel at its current state.
 Z— Put the channel in a high-impedance state.

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Per Cycle Tristate

 Some digital waveform generator/analyzers allow you to select

between driving a 0 or a 1 during every active period of the sample
clock.

 To enable this functionality, you create waveforms composed of 0, 1,

and Z values.

Fig. 1-6 Example of a Digital Waveform Composed of 0, 1, and Z Values

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Per Cycle Tristate

 Per cycle tristate is useful for communicating or testing bidirectional

digital channels
 E.q. communicating with a memory device may require the generator to
drive address and data channels during a write, but tristate the data
channels during a read

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1.3.3 Digital Compare States (L, H, and X)

 Three common states while acquiring

 L: the devices is expecting a Logic Low

 H: the devices is expecting a Logic High

 X: mean different things depending on whether the device is generating

or acquiring data

 in acquisition mode“don’t care”

 in generation mode  “whatever logical value you were previously

transmitting – keep transmitting it.”

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Digital Drive States v.s Digital Compare States

Table 1-2 Common Digital Drive and Compare States

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1.4 Digital Termination

 In high-speed digital systems, simple passive circuit elements like

wires, cables, and chip PCB interconnections can significantly affect
signal quality

 High-speed digital edges contain frequency components that are

several times the effective toggle rate of that signal

 Proper termination is needed to maximize signal quality and

minimize the effects of signal reflections

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Example

 The signals in the following figures show identical digital

waveforms generated by an digital device, with or without proper
termination.

Fig. 1-7(a) Properly Terminated Digital Channel (b) Improperly Terminated Digital Channel

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Improper Termination

 Improper termination may produce

 Signals that exceed specified high-level and low-level thresholds (overshoot and
undershoot)

 Signals that have false edges (ringing)

 Signals that have reduced operating margins (degraded eye diagram caused by
inter-symbol interference)

 Potential physical damage or overheating of driver/receiver components in

extreme cases

 Consider the following key areas when designing your test system:
 ZS—The impedance at the source of the transmission line

 Z0—The characteristic AC impedance of the transmission line

 Zt—The impedance at the destination of the transmission line

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1.4.1 Transmission Lines

 In high-speed application, the small geometries of typical wire

dimensions become a significant portion of the signal wavelengths,
and the small stray inductance and capacitance become electrically
significant impedances

 If the physical length of a wire or electrical interconnect is greater

than 1/6 of the electrical length of a signal propagating on that wire,
the system must be analyzed as a transmission line.

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Electrical length

 Electrical length (l) is defined as the distance that a signal can travel
in an electrical medium during the time that it takes for one rise or
fall time, whichever is longer

l(m) = Velocity(m/ns) • trise , or

l(m) = trise(ns)/tpd(ns/m)

where trise is the rise/fall time of the digital edge, and tpd is the
propagation delay of the edge in the transmission line.

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Single-ended Transmission Line
 A voltage source (Vs) generates a digital edge with an impedance of
Zs looking "into" the transmission line. The transmission line itself
has some low characteristic AC impedance (Z0) to ground, typically
50 Ω for most test systems. The end of the transmission line is most
commonly terminated through an impedance (Zt) to ground at the
destination.

Fig. 1-8 Diagram of a Basic Single-ended Transmission Line

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1.4.2 Characteristic Impedance

 The physical properties of the transmission line materials determine

this characteristic impedance, Z0
 E.g., the dielectric of the insulators and the cross sectional geometry of a
cable determine the capacitance

 The characteristic impedance is a function of both this inductance

and capacitance.

 It is critical that the characteristic impedance is matched to the

source impedance
 If not matched, the signal at the load is greatly distorted in both time
and amplitude

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1.4.3 Signal Reflections

 If a mismatch between Z0 and the termination (Zt) exists, portions of

the wave are reflected

 If a mismatch exists between the transmission line characteristic

impedance (Z0) and Zs, then portions of the reflected wave are
re-reflected

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Reflection Coefficient

 Reflection caused by an impedance mismatch at the end of a

transmission line is quantified by the reflection coefficient, Γ

Γ = Vr/Vi = (Zt - Z0)/(Zt + Z0)

where Vr is the reflected voltage, Vi is the incident voltage, Zt is the

terminating impedance, and Z0 is the characteristic impedance of
the transmission line

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1.4.4 Types of Termination

 There are several forms of line termination, including parallel,

series, and differential.

 Practically, termination at only one end of the transmission line is

often adequate and is more commonly used.

Fig. 1-8
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1.4.4 Types of Termination

 Parallel termination

 Differential termination

 Series termination

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Parallel termination

 Parallel termination matches the characteristic impedance of the

medium at the end of the line (Zt = Z0).

Fig. 7-9

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Differential Termination

 Differential termination is a variation of parallel termination used

for differential transmission lines. Many electrical standards, such as
emitter-coupled logic (ECL) and LVDS, require that traces are
routed differentially. As such, parallel termination is used between
the two modes of the differential trace.

RD=100Ω

Fig. 7-10
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Series Termination

 Series termination places series impedance equal to the

characteristic impedance at the source of the transmission line (Zs =
Z0). This termination prevents the source from re-reflecting any
reflections from an unterminated transmission line. It also prevents
reflections from the transmission line to the source at the entry.

Zs=Zo

Fig. 7-11
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 Common Terminology for
Digital I/O and Logic Analyzers

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2.1 Eye Diagram Analysis

 Digital transmitters drive new data samples on each “assertion” edge of the
clock also called active clock edge. For some devices, the assertion edge is
the rising edge; for others it is the falling edge

 In fact, the data is transmitted after a small delay from the assertion edge of
the clock; this delay is called the clock-to-out time or tCO

 Receivers sample data on each active clock edge. However, the signals are
distorted at transmission. Hence, the received clock/data edges are usually
skewed and jittered.

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2.1 Eye Diagram Analysis

 Therefore, data patterns are difficult to study in the time domain

 Every data set is different
 Finding isolated pulses is a pain

 In 1962, John Mayo at Bell Laboratories found a better way

 Scope traces are launched using the transmit clock as an external trigger
 The resulting oscillogram overlays every data-pattern-dependent variation of the
filtered NRZ spectrum
 For obvious reasons, these are called “eye diagrams”…

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2.1.1 Jitter

 Jitter is the deviation from ideal timing of an event, and is typically

measured from the zero-crossing of a reference signal.

 Jitter typically comes from cross-talk, simultaneous switching

outputs, and other regularly occurring interference signals.

 Since jitter varies over time, measurements and quantification of

jitter can range from a visual estimate on a scope of the range of
jitter in seconds, to a statistical-based measurement such as one
based on the standard deviation over time.

Fig. 2-2 Example of Jitter

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2.1.2 Hold and Setup Time

 Setup time (tSU) is the amount of time that the data signals must be
stable before the assertion edge of the receiver’s clock

 Hold time (tH) is the amount of time that the data signals must be
stable after the assertion edge of the receiver’s clock

 The set-up time and the hold time serve to require a stable window
around the assertion edge of the receiver’s clock for the receiver to
reliably sample the data

Fig. 2-1 Set time and hold time

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2.1.3 Drift

 Clock drift occurs when the transmitter’s clock period is slightly

different from that of the receiver.

 After many clock cycles, the difference between the two periods
becomes noticeable and may cause loss of synchronization and
other errors.

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2.1.4 Eye Diagram

 An eye diagram is constructed by looking at the outputs of a digital

transmitter over three time periods.

 An eye diagram, shown in Fig. 2-3, is constructed by overlaying all

of the possible combinations of 0’s and 1’s (0 1 1 in pink, 1 1 0 in
yellow, 0 0 1 in blue, 1 0 0 in green ) on single plot.

Fig. 2-3

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Timing Error Analysis by Use of Eye Diagram

 The Eye Diagram is a timing analysis tool providing the user with a
good visual of timing and level errors, e.g., maximum Jitter and
voltage level errors

Fig. 2-4 Jitter and Voltage Noise View from an Eye Diagram

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Eye Width

 Eye width is the width of the white space of the final eye diagram

 If an eye diagram is composed of enough samples (millions and

millions of three time period transitions), the eye width is a good
measure of the amount of time, in any given time period, that the
data lines are stable. This can give a good idea of how much setup
time and hold-time is allowable.

Fig. 2-5

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Eye Height

 Eye height is the height of the white space of the final eye diagram

 If an eye diagram is composed of enough samples, the eye height

can tell where the receiver’s VIH and VIL need to be to sample the
data correctly.

 For the better quality of the digital signal transmission, the eye
width and eye height should be as large as possible

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2.1.5 Example of Digital Signals Timing Analysis

 A real eye diagram, shown in Fig. 2-6 on next page, is an intensity

plot of the overlaid transitions sampled by high-speed digitizer,
such as the NI 5124 200 MS/s digitizer. The color of the plot is a
measure of the percentage of overlaid transitions for any given pixel.

 The assertion edges of the receiver’s clock, shown in Fig. 2-6 on the
next page, is the vertical, solid, lines

 The receiver’s VIH and VIL shown in Fig. 2-6 are represented by the
horizontal dashed lines

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2.1.5 Example of Digital Signals Timing Analysis

Fig. 2-6

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2.1.5 Example of Digital Signals Timing Analysis

1. Point where the overlaid data transitions cross the VIH of the
receiver. This is the earliest time that the clock could occur to
guarantee reliable data sampling. If the clock were any earlier, the
data lines could still be changing during the required set-up time
period. In this system the VIH voltage level is the limiting level.
2. This intersection marks the valid point for the clock assertion time +
the clock hold time.
3. Receiver’s setup time
4. Receiver’s hold time
5. Low percentage of the overlaid transitions
6. Very high percentage of the transitions

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2.2 Double Data Rate
 Data is usually latched on either the rising or falling edges of the
sample clock, called Single Data Rate (SDR).

 Double Data Rate (DDR) means to latch data on both the rising and
falling edges of the sample clock
 Increase the rate of data being sent into and out of digital devices

 Effectively double the data transfer rate without increasing the clock
speed

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 Logic Analyzer Example
-- NI 655x

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3.1 Logic Analyzer

 When performing a digital waveform acquisition, it is frequently a

requirement to acquire data from multiple channels. In many
situations, the signals of interest are a bus of data or control lines.

 A logic analyzer is a tool that allows numerous digital waveforms to

be acquired simultaneously. The acquisition can be clocked
internally, or the System Under Test (SUT) can provide the sample
clock. A logic analyzer also supports multiple triggering schemes to
determine when data is acquired.

 Let’s use the NI 655x as a example to introduce the usage and

features of a logic analyzer

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3.2 Features of NI655x

 20 data channels that can be used for simultaneous digital waveform

acquisitions.
 Each of these channels has a deep on board memory used to store data
during acquisitions.
 Three memory sizes are available with the NI 655x to suit a wide range of
applications: 1 Mbit per channel, 8 Mbits per channel, or 16 Mbits per
channel
 NI 655x is flexible on
 Memory Sizes
 Voltage Levels: adjustable in 10 mV
increments from -2 V to +5.5 V
 Input Impedances: a programmable input
impedance of 50  or 10 k.

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3.3 Advanced Acquisition Timing Options

 Digital waveform acquisitions are controlled by two clocks: the

sample clock and the reference clock

 Sample clock rates

 NI 6552: up to 100 MHz

 NI 6551: up to 50 MHz

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Sample Clock
 The sample clock is the primary timebase for a digital waveform
acquisition
 control when samples are acquired

 capable of initiating the acquisition of one sample per channel for every
period of the sample clock

 capable of acquiring data at different positions relative to the pulses of

the sample clock, including rising edge data, falling edge data, and
delayed data

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Delayed Data

 Delayed data is acquired at a specified time after the rising edge of

the sample clock.
 The delay can vary between 0 and 100% of the clock period with a
resolution of 0.4% of the clock period.

Fig. 3-1: Available Data Positions

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Generation of Sample Clock
 The sample clock can be programmed to come from either the on
board clock source or an external clock source
 on board clock source is a high-precision 200 MHz Voltage Controlled
Crystal Oscillator (VCXO) clock source

 the sample clock can be generated from dividing the on board clock
source by any integer from 2 to 4,194,304 for the NI 6552, and from
4 to 4,194,304 for the NI 6551

 An external clock frequency can be provided as the sample clock rate

through an SMB jack connector on the NI 655x front panel or the PXI
backplane

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Reference Clock
 To guarantee a high level of precision, the on board clock source can use a
phase locked loop (PLL) circuit to lock the internal timebase of the NI 655x
to a known reference frequency, which is called the reference clock.

 The most common source is the 10 MHz reference clock available from
the PXI backplane.

 A reference clock for the PLL can also be provided through an SMB jack
connector on the NI 655x front panel.
Sample clock
fin
Phase- Voltage- f
Reference Charge Loop Vc o
Frequency
Detector
Pump Filter
Controlled
Oscillator
1/N
clock

PLL On board
clock source
1/N

Fig. 3-2

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Clock Export

 It is often necessary to export either the sample or reference clock to

the System Under Test (SUT).
 The NI 655x has the capability to export its sample clock to the DDC
connector or an SMB jack connector on the NI 655x front panel.

 If a reference clock for the PLL has been configured, it can also be
exported to an SMB jack connector on the NI 655x front panel.

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3.4 Diverse Acquisition Triggering Choices

 The NI 655x supports numerous trigger types.

 edge triggers: a signal from low to high or high to low

 pattern match trigger: configures the NI 655x to monitor the input

channels for a specific pattern (i.e. '10100111'). When this pattern is
detected on the input channels, the trigger asserts.

 A pattern match trigger can also be configured to trigger the NI

655x when the pattern is not matched.

 level triggers: a trigger can be configured for a signal transition below

the defined low level or above the defined high level.

 software trigger: generated internally by a programmatic call in

software.

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The Actions a Trigger Can Initiate

 The NI 655x also supports various actions that a trigger can initiate
 A reference trigger establishes the reference point that separates
pretrigger and posttrigger samples.

 acquire a certain number of samples of digital data before

(pretrigger) and after (posttrigger) a trigger.

 A start trigger simply starts the process of sampling and storing data.

 A pause trigger is to pause the sampling during an active acquisition

 The supported types for a reference trigger and a start trigger are
edge, pattern match, and software.

 The supported types for a pause trigger are level and pattern match.

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3.5 Powerful Visualization Programming Features

 The NI 655x can be programmed in LabVIEW 7 Express (or later),

LabWindows/CVI 6.0 (or later), or C/C++.

 The Digital Waveform Graph, included in LabVIEW, is a powerful user

interface object that allows digital data to be displayed in a very informative
and logical manner.

Fig. 3-3 LabVIEW Digital Waveform Graph

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Digital Waveform Graph
 Multiple channels can also be grouped together and displayed as
buses.
 The format of the bus plots can be hexadecimal, decimal, octal, or binary.

Fig. 3-4 Digital Waveform Graph displaying two buses of hexadecimal digital data

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Digital Table
 LabVIEW also provides the Digital Table. This user interface object
allows digital data to be displayed as text.
 The format of the text can be hexadecimal, decimal, octal, or binary.

Fig. 3-5 LabVIEW Digital Table with Binary Data

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3.6 Extensive Expansion and Integration Capabilities

 Some applications require more than the 20 digital waveform

acquisition channels provided by a single NI 655x.
 the integrated timing and triggering capabilities of the PXI form factor
makes it simple to synchronize multiple NI 655x devices in a system

 PXI chassis are available with 4, 8, or 18 slots.

 Synchronization of these modules is needed. For additional information

concerning the synchronization capabilities of the NI 655x, please refer
to the NI Digital Waveform Generator/Analyzer Help.

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Digital Waveform Generation

 Besides performing digital waveform acquisitions, the NI 655x is

also capable of generating digital waveforms.

 In fact the NI 655x can acquire and generate simultaneously.

 During the process of debugging and validating a digital system, the
ability to output digital data is often necessary to control an SUT or
simulate input data..

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Reference

 NI Tutorials
 http://www.ni.com/

 National Instruments Measurement Fundamentals series

 Datasheet of NI 655x series

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