Digital System Design Using Verilog (21EC32)

EXPERIMENT:01:
To Simplify the given Boolean expressions and realize using Verilog program

Aim: To Simplify the given Boolean expressions and realize using Verilog program

Programming Language: Verilog HDL

Program:
module ckt1(a,b,c,d,f);
input a,b,c,d;
output f;
wirex,y,z;
assign x=a&b;
assign y=c&d;
assign z=x|y;
assign f=~z;
endmodule

Output:

Dept. of ECE,KLS VDIT,Haliyal Page 1

 Digital System Design Using Verilog (21EC32)

EXPERIMENT:02

To realize Adder/Subtractor(Full) Half circuits using Verilog data flow description

Aim:- To realize Adder/Subtractor(Full) Half circuits using Verilog data flow description

Programming Language: Verilog HDL

Program:
module halfadder(a,b,sum,carry);
input a,b;
output sum,carry;
assign sum=a^b;
assign carry=a&b;
endmodule
Output:

module fulladder(
input a,
input b,
input c,
output sum,output carry, inout x, inout y, inout z);
assign sum=a^b^c;
assign carry=(a&b)|(b&c)|(c&a);
endmodule
Output:

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 Digital System Design Using Verilog (21EC32)

module halfsubtractor(
input a,
input b,
output difference,
output borrow
);
assign difference=a^b;
assign borrow=(~ a)&b;

endmodule

Output:

module fullsubtractor(A,B,C,diff,borrow );
input A,B,C;
output diff, borrow;
wire p,q,r;
assign diff=A^B^C;
assign p=(!A)&C;
assign q=(!A)&B;
assign r=B&C;
assign borrow=p|q|r;
endmodule
Output:

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 Digital System Design Using Verilog (21EC32)

EXPERIMENT:03:
To realize 4 bit ALU using verilog Program
Aim:- To realize Adder/Subtractor(Full) Half circuits using Verilog data flow description

Programming Language: Verilog HDL

Program:
module alu_4(a,b,en,cin,opcode,out);
input en,cin;
input [3:0] a,b;
input [3:0] opcode;
output reg [3:0] out;
always@(a,b,en,opcode)
begin
if (en==1)
case (opcode)
4'b0000:out=a;
4'b0001:out=a+1;
4'b0010:out=b;
4'b0011:out=b+a;
4'b0100:out=a*b;
4'b0101:out=a-b;
4'b0110:out=~a;
4'b0111:out=a+b+cin;
4'b1000:out=~(a&b);
4'b1001:out=~(a|b);
4'b1010:out=a^b;
4'b1011:out=~(a^b);
4'b1100:out=a&b;
4'b1101:out=a|b;
4'b1110:out=~b;
endcase
else out=4'bx;
end
endmodule

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 Digital System Design Using Verilog (21EC32)

Output:

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 Digital System Design Using Verilog (21EC32)

EXPERIMENT:04
To realise the following code converters using Verilog behavioural description

AIM: To realise the following code converters using Verilog behavioural description

Programming Language: Verilog HDL

Program:

module b_g(b,g);
input [3:0] b;
outputreg [3:0]g;
always@(b,g)
begin
g[3]=b[3];
g[2]=b[3]^b[2];
g[1]=b[2]^b[1];
g[0]=b[1]^b[0];
end
endmodule

Output:

Program:

module b_g(g,b);
input [3:0] g;
output [3:0]b;
assign b[3]=g[3];
assign b[2]=g[3]^g[2];
assign b[1]=g[3]^g[2]^g[1];
assign b[0]=g[3]^g[2]^g[1]^g[0];
endmodule
Output:

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 Digital System Design Using Verilog (21EC32)

EXPERIMENT:05

To realize using Verilog Behavioural description 8:1 Multiplexer, 8:3 priority Encoder.

AIM: To realize using Verilog Behavioural description 8:1 Multiplexer, 8:3 priority Encoder.

Programming Language: Verilog HDL

Program:

module mux8_1(en,s,d,y);
input en;
input [2:0]s;
input [7:0]d;
outputreg y;
always@(en,s,d)
begin
if(en==1)
case(s)
3'd0:y=d[0];
3'd1:y=d[1];
3'd2:y=d[2];
3'd3:y=d[3];
3'd4:y=d[4];
3'd5:y=d[5];
3'd6:y=d[6];
3'd7:y=d[7];
default:y=1'bx;
endcase
else
y=1'bz;
end
endmodule
Output:

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 Digital System Design Using Verilog (21EC32)

Programming Language: Verilog HDL

Program:

module encoder83wp(en,din,dout);
input en;
input [7:0]din;
outputreg [2:0]dout;
always@(en,din)
begin
if(en==1)
case(din)
8'b10000000:dout=3'b111;
8'b01000000:dout=3'b110;
8'b00100000:dout=3'b101;
8'b00010000:dout=3'b100;
8'b00001000:dout=3'b011;
8'b00000100:dout=3'b010;
8'b00000010:dout=3'b001;
8'b00000001:dout=3'b000;
default:dout=3'bxxx;
endcase
else
dout=3'bzzz;
end
endmodule

Output:

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 Digital System Design Using Verilog (21EC32)

Program:

module encoder83p(en,din,dout);
input en;
input [7:0]din;
outputreg [2:0]dout;

always@(en,din)
begin
if(en==1)
casex(din)
8'b1xxxxxxx:dout=3'b111;
8'b01xxxxxx:dout=3'b110;
8'b001xxxxx:dout=3'b101;
8'b0001xxxx:dout=3'b100;
8'b00001xxx:dout=3'b011;
8'b000001xx:dout=3'b010;
8'b0000001x:dout=3'b001;
8'b00000001:dout=3'b000;
default:dout=3'bxxx;
endcase
else
dout=3'bzzz;
end
endmodule

Output:

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 Digital System Design Using Verilog (21EC32)

EXPERIMENT:06

To realize using Verilog behavioural description 1:8 Demux, 3:8 Decoder, 2 bit Comparator

AIM: To realize using Verilog behavioural description 1:8 Demux, 3:8 Decoder, 2 bit Comparator

Programming Language: Verilog HDL

Program:

module demux(in,s0,s1,s2,d0,d1,d2,d3,d4,d5,d6,d7);
input in,s0,s1,s2;
output d0,d1,d2,d3,d4,d5,d6,d7;
assign d0=(in & ~s2&~s1&~s0);
assign d1=(in & ~s2&~s1&s0);
assign d2=(in & ~s2&s1&~s0);
assign d3=(in & ~s2&s1&s0);
assign d4=(in & s2&~s1&~s0);
assign d5=(in & s2&~s1&s0);
assign d6=(in & s2&s1&~s0);
assign d7=(in & s2&s1&s0);
endmodule

Output:

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 Digital System Design Using Verilog (21EC32)

Program:

module decoder(a,b,c, d0,d1,d2,d3,d4,d5,d6,d7);

inputa,b,c;
output d0,d1,d2,d3,d4,d5,d6,d7;
assign d0=(~a&~b&~c);
assign d1=(~a&~b&c);
assign d2=(~a&b&~c);
assign d3=(~a&b&c);
assign d4=(a&~b&~c);
assign d5=(a&~b&c);
assign d6=(a&b&~c);
assign d7=(a&b&c);
endmodule
Output:

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 Digital System Design Using Verilog (21EC32)

Program:

module comp(x,y,xlty,xgty,xeqy);
input [1:0] x,y;
output reg xlty,xgty,xeqy;
always@(x,y)
begin
xlty=1'b0;
xgty=1'b0;
xeqy=1'b0;
if(x==y)
xeqy=1;
else if(x>y)
xgty=1;
else
xlty=1;
end
endmodule

Output:

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 Digital System Design Using Verilog (21EC32)

AIM: To realize using Verilog behavioural description 1:8 Demux, 3:8 Decoder, 2 bit Comparator

Programming Language: Verilog HDL

Program:
module jk_ff1(j,k,clk,q,qb);
inputj,k,clk;
outputregq,qb;
initial
begin
q=1;
end
always@(posedgeclk)
begin
case({j,k})
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
2'b11:q=~q;
endcase
qb=~q;
end
endmodule
Output:

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 Digital System Design Using Verilog (21EC32)

Program:

module sr_ff1(s,r,clk,q,qb);
input s,r,clk;
output reg q,qb;
initial
begin
q=1;
end
always@(posedgeclk)
begin
case({s,r})
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
2'b11:q=1'bx;
endcase
qb=~q;
end
endmodule

Output:

Program:

module d_ff1(d,clk,q,qb);
inputd,clk;
outputregq,qb;
always@(posedgeclk)
begin
case(d)
1'b0:q=0;
1'b1:q=1;
endcase
qb=~q;
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 Digital System Design Using Verilog (21EC32)

end
endmodule
Output:

Program:

odule t_ff(t,clk,q,qb);
input t,clk;
output reg q,qb;
initial
begin
q=1;
end
always@(posedgeclk)
begin
case(t)
1'b0:q=q;
1'b1:q=~q;
endcase
qb=~q;
end
endmodule

Output:

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 Digital System Design Using Verilog (21EC32)

EXPERIMENT:08
To realize counter up/down(BCD and Binary) using Verilog Behavioural description

AIM: To realize counter up/down(BCD and Binary) using Verilog behavioural description

Programming Language: Verilog HDL

Program:
module bin_count(clk,reset,load,data,q);
parameter n=4;
inputclk,reset,load;
input [n-1:0] data;
outputreg [n-1:0]q;
always@(posedgeclk)
begin
if(reset)
q=4'b0000;
else if(load)
q=data;
else
q=q+1;
end
endmodule
Output:

Program:

Module downbin_count(clk,reset,load,data,q);
parameter n=4;
input clk,reset,load;
input [n-1:0] data;
output reg [n-1:0]q;
always@(posedgeclk)
begin
if(reset)
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 Digital System Design Using Verilog (21EC32)

q=4'b1111;
else if(load)
q=data;
else
q=q-1;
end
endmodule
Output:

Program:
module bcdup(clk,reset,q);
parameter n=4;
input clk,reset;
output reg [n-1:0]q;
always@(posedgeclk)
begin
if(reset)
q=0;
else if(q<9)
q=q+1;
else
q=0;
end
endmodule

Output:

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 Digital System Design Using Verilog (21EC32)

Program:
module bcddown(clk,reset,q);
parameter n=4;
input clk,reset;
output reg [n-1:0]q;
always@(posedge clk)
begin
if(reset)
q=4'b1001;
else if(q>0)
q=q-1;
else
q=4'b1001;
end
endmodule
Output:

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 Digital System Design Using Verilog (21EC32)

EXPERIMENT:09
To interface a stepper motor the FPGA/CPLD and rotate the motor in the specified direction by
N steps

AIM: To interface a stepper motor the FPGA/CPLD and rotate the motor in the specified direction by N steps

Programming Language: Verilog HDL

Program:

module stepper_motor(clk, dir_ctr1, speed, out);

input clk;
input dir_ctr1;
output [3:0] out;
input speed;
reg [3:0] out=4'b0111;
reg clk1;
reg [30:0] divclk=31'd0;
always@(posedgeclk)
begin
divclk=divclk+1;
end
always@(speed)
begin
case(speed)
1'b0:clk1=divclk[13];
1'b1:clk1=divclk[18];
endcase
end
always@(posedge clk1)
begin
if(dir_ctr1==1)
begin
case(out)
4'b0111:out=4'b1011;
4'b1011:out=4'b1101;
4'b1101:out=4'b1110;
4'b1110:out=4'b0111;
endcase
end
else
begin
case(out)
4'b1011:out=4'b0111;

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 Digital System Design Using Verilog (21EC32)

4'b0111:out=4'b1110;
4'b1110:out=4'b1101;
4'b1101:out=4'b1011;
endcase
end
end
endmodule

NETLIST:

NET "out[3]" LOC = P119;

NET "out[2]" LOC = P118;
NET "out[1]" LOC = P117;
NET "out[0]" LOC = P114;
NET "clk" LOC = P51;
NET "dir_ctr1" LOC = P22;
NET "speed" LOC = P24;

OUTPUT:

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 Digital System Design Using Verilog (21EC32)

EXPERIMENT:10
To interface a Relay or ADC to the FPGA/CPLD and demonstrate

AIM: To interface a Relay or ADC to the FPGA/CPLD and demonstrate

Programming Language: Verilog HDL

Program:
module seven_seg(d,en,fnd);
input [3:0]d;
output en;
output [7:0]fnd;
reg [7:0]fnd;
assign en = 1;
always@(d)
begin
case(d)
4’d0: fnd = 8’b01110110;
4’d1: fnd = 8’b00000110;
4’d2: fnd = 8’b01011011;
4’d3: fnd = 8’b01001111;
4’d4: fnd = 8’b01100110;
4’d5: fnd = 8’b01101101;
4’d6: fnd = 8’b01111101;
4’d7: fnd = 8’b00000111;
4’d8: fnd = 8’b01111111;
4’d9: fnd = 8’b01101111;
default: fnd= 8’b00000111;
endcase
end
endmodule

NETLIST:
NET “en” LOC=P2;
NET “d[0]” LOC=P35;
NET ”d[1]” LOC=P29;
NET ”d[2]” LOC=P27;
NET ”d[3]” LOC=P21;
NET “fnd[7]” LOC=P19;
NET “fnd[6]” LOC=P18;
NET “fnd[5]” LOC=P16;
NET “fnd[4]” LOC=P15;
NET “fnd[3]” LOC=P13;
NET “fnd[2]” LOC=P12;

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 Digital System Design Using Verilog (21EC32)

NET “fnd[1]” LOC=P11;

NET “fnd[0]” LOC=P10;

Output:

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 Digital System Design Using Verilog (21EC32)

EXPERIMENT:11EXPERIMENT:07
To interface DAC to the FPGA/CPLD for waveform generationTo realize using Verilog
behavioural description Flip Flop a) JK Type b) SR Type c) T Type d) D Type

AIM: To interface DAC to the FPGA/CPLD for waveform generation

Programming Language: Verilog HDL

Program:

module sine(clk, dout);

input clk;
output [7:0] dout;
//wire clk1;
reg [7:0] temp;
reg [7:0] a [0:47];
integer i;
reg [7:0] dout;

tstcnt t1(.clkin(clk), .clkout(clk1));// .clkout

always @ (posedge clk1)

begin

a[0] = 8'h80;
a[1] = 8'h90;
a[2] = 8'hA1;
a[3] = 8'hB1;
a[4] = 8'hC0;
a[5] = 8'hCD;
a[6] = 8'hDA;
a[7] = 8'hE5;
a[8] = 8'hEE;
a[9] = 8'hF6;
a[10] = 8'hFB;
a[11] = 8'hFE;
a[12] = 8'hFF;
a[13] = 8'hFE;
a[14] = 8'hFB;
a[15] = 8'hF6;
a[16] = 8'hEE;
a[17] = 8'hE5;
a[18] = 8'hDA;
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 Digital System Design Using Verilog (21EC32)

a[19] = 8'hCD;
a[20] = 8'hC0;
a[21] = 8'hB1;
a[22] = 8'hA1;
a[23] = 8'h90;
a[24] = 8'h80;
a[25] = 8'h70;
a[26] = 8'h5F;
a[27] = 8'h4F;
a[28] = 8'h40;
a[29] = 8'h33;
a[30] = 8'h26;
a[31] = 8'h1B;
a[32] = 8'h12;
a[33] = 8'h0A;
a[34] = 8'h05;
a[35] = 8'h02;
a[36] = 8'h00;
a[37] = 8'h02;
a[38] = 8'h05;
a[39] = 8'h0A;
a[40] = 8'h12;
a[41] = 8'h1B;
a[42] = 8'h26;
a[43] = 8'h33;
a[43] = 8'h40;
a[44] = 8'h4F;
a[45] = 8'h5F;
a[46] = 8'h70;
a[47] = 8'h80;

if(clk1 == 1)
begin
if(i == 47)
i = 0;
else
i = i + 1;
temp = a[i];
dout = temp;

end
end
endmodule
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 Digital System Design Using Verilog (21EC32)

module tstcnt(clkin, clkout);

input clkin;
output clkout;

reg clkout;
reg [4:0] cnt = 5'b00000;
reg check=1'b0;
reg t=1'b0;
always @(posedge clkin)
begin
cnt = cnt + 1;
if(cnt == 5'b11110)
begin
check = !check;
cnt = 5'b00000;
end
end
always @(posedge check)
begin
t = !t;
clkout = t;
end
endmodule

NETLIST:
NET "dout[7]" LOC = P138;
NET "dout[6]" LOC = P139;
NET "dout[5]" LOC = P134;
NET "dout[4]" LOC = P137;
NET "dout[3]" LOC = P132;
NET "dout[2]" LOC = P133;
NET "dout[1]" LOC = P127;
NET "dout[0]" LOC = P131;
NET "clk" LOC = P51;
OUTPUT:

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 Digital System Design Using Verilog (21EC32)

EXPERIMENT:12
To interface switches and LEDs to the FPGA/CPLD and demonstrate its working

AIM: To interface switches and LEDs to the FPGA/CPLD and demonstrate its working

Programming Language: Verilog HDL

Program:

module fulladder(
input a,
input b,
input c,
output sum,
output carry,
inout x,
inout y,
inout z
);

assign sum=a^b^c;
assign carry=(a&b)|(b&c)|(c&a);
endmodule

NETLIST:
NET "a" LOC = P22;
NET "b" LOC = P24;
NET "c" LOC = P27;
NET "sum" LOC = P21;
NET "carry" LOC = P23;

OUTPUT: Output is observed on the Basys 2 Kit

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