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Detailed Notes On Data Hazards, Structural Hazards, and Control Hazards

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116 views1 page

Detailed Notes On Data Hazards, Structural Hazards, and Control Hazards

Uploaded by

satyaki.mandal2005
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Detailed Notes on Data Hazards, Structural

Hazards, and Control Hazards

Abstract
This document provides comprehensive notes on the topics of data hazards, structural
hazards, and control hazards, which are critical concepts in computer architecture and
instruction pipelining. It includes detailed explanations, examples, and techniques for
identifying different types of data hazards. Additionally, it presents important questions and
answers that may be relevant for examination purposes.

1. Data Hazards
Data hazards occur when instructions that depend on the results of prior instructions are
executed in a pipeline. There are three main types of data hazards: Read After Write (RAW),
Write After Read (WAR), and Write After Write (WAW).

1.1 Types of Data Hazards


• Read After Write (RAW): This occurs when an instruction needs to read a value that
has not yet been written by a previous instruction.
• Example:

ADD R1, R2, R3 ; R1 = R2 + R3


SUB R4, R1, R5 ; R4 = R1 - R5 (RAW hazard because R1 is not yet updated)

• Write After Read (WAR): This occurs when an instruction writes to a location before a
previous instruction has read from it.
• Example:

MOV R1, R2 ; R1 = R2
ADD R2, R3, R4 ; R2 = R3 + R4 (WAR hazard because R1 is read before R2 is
written)

• Write After Write (WAW): This occurs when two instructions write to the same
location, and the order of writes is important.

• Example:

MOV R1, R2 ; R1 = R2
MOV R1, R3 ; R1 = R3 (WAW hazard because the final value of R1 depends on
the order)

1.2 Techniques to Identify Data Hazards


• Data Dependency Analysis: Check the instruction sequence for dependencies
between registers.
• Pipeline Simulation: Simulate the pipeline execution to observe when hazards occur.
• Dependency Graphs: Create a graph where nodes represent instructions and edges
represent dependencies.

2. Structural Hazards
Structural hazards occur when hardware resources are insufficient to support all concurrent
operations in a pipeline.

2.1 Example of Structural Hazards


• Example: Consider a scenario where a single memory unit is used for both instruction
fetch and data access.

LOAD R1, 0(R2) ; Fetch instruction


STORE R1, 0(R3) ; Fetch data (structural hazard if both access memory
simultaneously)

2.2 Techniques to Identify Structural Hazards


• Resource Allocation Analysis: Review the architecture to ensure that all required
resources are available.
• Pipeline Resource Usage Charts: Create charts to visualize resource usage over time.

3. Control Hazards
Control hazards arise from the pipelining of branches and other instructions that change the
program counter (PC).

3.1 Example of Control Hazards


• Example:

BEQ R1, R2, LABEL ; Branch if R1 == R2


ADD R3, R4, R5 ; This instruction may be incorrectly fetched if the branch
is taken

3.2 Techniques to Identify Control Hazards


• Branch Prediction: Use techniques to predict the outcome of branches to minimize
stalls.
• Delayed Branch: Reorganize instructions to fill the delay slots after a branch.

4. Important Questions and Answers

Q1: What is a data hazard? Provide an example.


A1: A data hazard occurs when an instruction depends on the result of a previous instruction
that has not yet completed.
• Example:

ADD R1, R2, R3


SUB R4, R1, R5 ; RAW hazard

Q2: Explain the difference between RAW, WAR, and WAW hazards.
A2:
• RAW (Read After Write): An instruction reads a value before it is written by a previous
instruction.
• WAR (Write After Read): An instruction writes to a location before a previous
instruction reads from it.
• WAW (Write After Write): Two instructions write to the same location, and the order
of writes matters.

Q3: What are structural hazards? Give an example.


A3: Structural hazards occur when hardware resources are insufficient to support all
concurrent operations.
• Example: A single memory unit being used for both instruction fetch and data access.

Q4: How can control hazards be mitigated?


A4: Control hazards can be mitigated using branch prediction techniques and reorganizing
instructions to fill delay slots.

Q5: Describe a technique to identify data hazards.


A5: One technique is data dependency analysis, where the instruction sequence is checked
for dependencies between registers.

By understanding these concepts and examples, students can effectively prepare for exams
on data hazards, structural hazards, and control hazards in computer architecture.

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