COMPUTER ORGANIZATION AND

ARCHITECTURE

Reshma M R, Dept of CSE, RSET

Text Book

“Computer Organization “ by Carl

Hamacher, Zvonko Vranesic , and
Safwat Zaky. 5th ed

Reshma M R, Dept of CSE, RSET

Syllabus
• Module 5: I/O Subsystem and RISC-V architecture
• I/O organization: accessing of I/O devices interrupts, interrupt hardware –Direct
memory access. Working principle of USB based I/O devices. PCI and USB
communication. Introduction and organization of Hard disk, disk accessing, disk
formatting, RAID structures.
• Introduction to RISC-V architecture, instruction set.
• Course Outcome 5:
• CO 5: Summarize the concept of I/O susbsystem, interrupts and working principle
of USB based devices and hard disk (Cognitive Knowledge Level: Understand)

Reshma M R, Dept of CSE, RSET

I/O Subsystem

Reshma M R, Dept of CSE, RSET

Introduction
• One basic feature of computers is that it can exchange data with devices.
• In certain applications, input to a computer may come from a sensor switch, a
digital camera, a microphone, or a fire alarm.
• Output may be a sound signal sent to a speaker, or a digitally coded command that
changes the speed of a motor, opens a valve, or causes a robot to move in a
specified manner.
• In short, computers should have the ability to exchange digital and analog
information with a wide range of devices in many different environments.

Reshma M R, Dept of CSE, RSET

Introduction
• Data can be in memory, or it can come from a device like keyboard, camera or
microphones etc.
• Consider the keyboard. Every time a key is pressed the terminal sends a binary
coded character to the computer. The fastest possible speed of entering
information depends on the person’s typing speed.
• However, the processor is extremely fast.
• When input information is passed to the CPU via a keyboard, CPU will remain
idle most of the time.
• Similarly processed data may be produced as output to a screen, or printed etc.

Reshma M R, Dept of CSE, RSET

Input-Output Interface

• The components of a computer system

communicate with each other through
an interconnection network.

• The interconnection network consists

of circuits needed to transfer
information between the processor, the
memory unit, and a number of I/O
devices.

Reshma M R, Dept of CSE, RSET

Input-Output Interface
• Input/Output interface provides a method for transferring information between internal storage and
external I/O devices.
• Special communication links are required between CPU and peripheral since:
1. The manner of operation on peripherals (electromechanical/ electromagnetic devices) are
different from that of the CPU (electronic device). Conversion of signal values maybe
necessary.
• Electromechanical Devices: These are devices that combine electrical and mechanical
processes to perform a function. They typically involve moving parts. Examples includes:
Printers, Hard Disk Drives (HDD),Optical Drives
• Electromagnetic Devices: These devices use electromagnetic principles to perform
functions. They may not necessarily involve moving parts but rely on the interaction of
electricity and magnetism. Examples include: Speakers, Microphones
• CPU- It's an electronic device made up of integrated circuits, where calculations and
logical operations are carried out using electrical signals.

Reshma M R, Dept of CSE, RSET

Input-Output Interface
2. The data transfer rate of peripherals is usually slower than that of the transfer
rate of the CPU. Hence some synchronization mechanism is required.
3. Data codes and formats in peripherals are different from the word formats in
CPU and memory.
4. The operating modes of peripherals are different from each other, and each
must be controlled separately.
• To resolve these differences, computer systems use special hardware components
called interface units to supervise and synchronize all I/O transfers.
• They act as an interface between the processor bus and the peripheral device.

Reshma M R, Dept of CSE, RSET

Input-Output Interface

Reshma M R, Dept of CSE, RSET

I/O Device Interface
• An I/O device is connected to the interconnection network by using a circuit, called the
device interface, which provides the means for data transfer and for the exchange of status
and control information needed to facilitate the data transfers and govern the operation of
the device.
• The interface includes some registers that can be accessed by the processor.
• Data register may serve as a buffer for data transfers,
• Status register hold information about the current status of the device, and
• Control register store the information that controls the operational behavior of the device.
• These data, status, and control registers are accessed by program instructions as if they
were memory locations.
• Typical transfers of information are between I/O registers and the registers in the
processor.

Reshma M R, Dept of CSE, RSET

I/O Device Interface
Figure illustrates how the keyboard and display devices are connected to the processor from the
software point of view.

Reshma M R, Dept of CSE, RSET

I/O bus and Interface Modules
Address lines

Bus Data lines

Control lines

Address Control Data and I/O

decoder circuits status registers interface

Input device

Reshma M R, Dept of CSE, RSET

I/O bus and Interface Modules
• I/O device is connected to the bus using an I/O interface circuit which has:
- Address decoder, control circuit, and data and status registers.
• Address decoder decodes the address placed on the address lines thus enabling the device to
recognize its address.
• Control Circuit Each peripheral has its own controller that operates the particular electromagnetic
device.
• For example, printer controller controls paper motion, print timing, and the selection of
printing characters.
• Data register holds the data being transferred to or from the processor.
• Status register holds information necessary for the operation of the I/O device.
• Data and status registers are connected to the data lines, and have unique addresses.
• I/O interface circuit coordinates I/O transfers.
Reshma M R, Dept of CSE, RSET
I/O bus and Interface Modules
• When the processor places a particular address on address lines, the device
interface that recognize this address activates the path between the bus lines and
the device it controls.
• The device then responds to the command issued on the control lines.
• The processor request either a read or write operation via control lines and the
requested data are transferred over the data lines.

Reshma M R, Dept of CSE, RSET

Handling I/O operations in computer systems
▪ Program-Controlled I/O (Polling)
▪ Memory-Mapped I/O
▪ Isolated I/O.
▪ Interrupt-Driven I/O
▪ Direct Memory Access (DMA)

Reshma M R, Dept of CSE, RSET

Program-Controlled I/O
• Programmed I/O operations are the result of I/O instructions written in the
computer program. This method is known as program-controlled I/O.
• Each data item transfer is initiated by an instruction in the program. Usually, the
transfer is to and from a CPU register and peripheral.
• Transferring data under program control requires constant monitoring of the
peripheral by the CPU.
• Polling I/O: When the processor reads the status flag to determine its state, we say
that the processor polls the I/O device.
• Once a data transfer is initiated, the CPU is required to monitor the interface to see
when a transfer can again be made.
• It is up to the programmed instructions executed in the CPU to keep close tabs on
everything that is taking place in the interface unit and the I/O device.

Reshma M R, Dept of CSE, RSET

Program-Controlled I/O
• Examples:
• Reading data from a keyboard or a mouse where the CPU continuously polls the
device for keypresses or mouse movements.
• Writing data to a printer where the CPU initiates the print operation, checks the
printer status, and transfers data in small chunks.

Reshma M R, Dept of CSE, RSET

Program-Controlled I/O
Drawbacks:

1. Inefficiency: Programmed I/O can be inefficient, especially for high-speed

devices or large data transfers, as it keeps the CPU busy and may lead to a
waste of processing time.

2. Limited Concurrency: The CPU is dedicated to managing the I/O operation,

limiting its ability to perform other tasks concurrently.

Reshma M R, Dept of CSE, RSET

Program-Controlled I/O Example

• Consider a task that reads characters typed on a keyboard, stores these data in the
memory, and displays the same characters on a display screen.
• In addition to transferring each character from the keyboard into the memory,
and then to the display, it is necessary to ensure that this happens at the right
time.
• An input character must be read in response to a key being pressed.
• For output, a character must be sent to the display only when the display
device is able to accept it.

Reshma M R, Dept of CSE, RSET

Program-Controlled I/O Example

Reshma M R, Dept of CSE, RSET

Data Transfer Rates in I/O (keyboard, display,
processor)
• Keyboard to Computer: • Processor Speed:
• Limited by user typing speed. • Executes billions of instructions
• Typically, a few characters per per second.
second. • Much faster than both keyboard
• Computer to Display: and display transfer rates.
• Higher transfer rate than keyboard • The difference in speed between the
input. processor and I/O devices creates the
• Can transmit and display several need for mechanisms to synchronize
thousand characters per second. the transfer of data between them. One
solution to this problem involves a
signaling protocol.

Reshma M R, Dept of CSE, RSET

Registers in the keyboard and display interfaces.

• Register STATUS contains two control flags,

SIN and SOUT, which provide status
information for the keyboard and the display
unit, respectively.
• The two flags KIRQ and DIRQ in this register
are used in conjunction with interrupts.
• The KEN and DEN bits are in register
CONTROL.
• Data from the keyboard are made available in
the DATAIN register, and data sent to the
display are stored in the DATAOUT register.

Reshma M R, Dept of CSE, RSET

Status Flags for I/O Devices
• Keyboard Input (SIN Flag):
• SIN Flag: Part of the status register in the keyboard interface circuit.
• Set when a character is entered at the keyboard.
• Cleared (set to 0) once the character is read by the processor.
• Data Validation:
• Software checks the SIN flag to ensure valid data is read.
• Implemented in a loop that repeatedly checks the status register.
• Reading Input:
• When SIN = 1, the program reads from the input data register.
• Output Operations (SOUT Flag):
• Similar procedure for output, using the SOUT flag to control data transmission.

Reshma M R, Dept of CSE, RSET

Memory-mapped I/O.
• In memory-mapped I/O, both memory and I/O devices use the same address space.
• Here assign some of the memory addresses to I/O devices. The CPU treats I/O devices
like computer memory.
• The CPU either communicates with computer memory or some I/O devices depending on
the address. Therefore, we reserve a part of the address space for I/O devices, which is not
available for computer memory.
• In the case of memory-mapped I/O, all the buses are the same for both memory and
I/O devices. Therefore, building a CPU that uses memory-mapped I/O is easier and
cheaper.
• Additionally, such CPUs consume less power due to reduced complexity.
• One advantage of memory-mapped I/O is that we don’t need separate instruction
sets for accessing I/O devices. Instructions used for accessing memory can be easily used
for accessing I/O devices.

Reshma M R, Dept of CSE, RSET

Memory-mapped I/O.

• Unified Address Bus:

• Uses the same address bus for both memory and I/O devices.
• I/O device memory and registers (I/O registers) are mapped to specific address
values.
• Accessing I/O Devices:
• CPU accesses can refer to either physical RAM or I/O device memory.
• Standard memory access instructions also work for I/O device access.

Reshma M R, Dept of CSE, RSET

Memory-mapped I/O.
• Device Monitoring:
• Each I/O device monitors the CPU's address bus.
• Devices respond when CPU accesses an address assigned to them.
• Data bus connects to the specific device’s hardware register as needed.
• Address Reservation:
• Certain CPU address ranges are reserved for I/O, not general memory.
• Temporary or Permanent Reservation:
• Temporary: Example – in some systems they switch between I/O and memory.
• Permanent: Fixed allocation for some systems.

Reshma M R, Dept of CSE, RSET

Memory-mapped I/O.
• With memory-mapped I/O, any machine instruction that can access memory can
be used to transfer data to or from an I/O device.

• For example, if DATAIN is the address of a register in an input device, the

instruction
Load R2, DATAIN , reads the data from the DATAIN register and loads
them into processor register R2.

• Similarly, the instruction

Store R2, DATAOUT , sends the contents of register R2 to location
DATAOUT, which is a register in an output device.
Reshma M R, Dept of CSE, RSET
Memory-mapped I/O
• It can be more efficient for data transfers as it allows for direct memory access,
reducing the need for protocol translation between the CPU and I/O devices.

• It also provide faster response times for I/O operations as they are treated the same
as memory access, reducing overhead in communication.

• It can lead to potential conflicts between memory and I/O devices if not properly
managed, as both share the same address space.

• Memory mapped io is commonly used in modern computer systems due to its

efficiency and ease of implementation

Reshma M R, Dept of CSE, RSET

Isolated I/O
• In the case of isolated I/O, we provide a separate address space other than a
memory address space to I/O devices.
• The addresses of I/O devices are also referred to as ports.
• I/O devices and memory use the same address and data bus.
• However, the control bus is different for data and memory
• Therefore, isolated I/O becomes costlier compared to memory-mapped I/O.
• The isolated I/O technique has its own dedicated instruction set for accessing I/O
devices.
• The CPUs that use isolated I/O are bigger and more complex to build.

Reshma M R, Dept of CSE, RSET

For I/O devices, it doesn’t matter whether memory mapped or isolated I/O is implemented. I/O devices
behave in the same manner independent of the I/O method implemented internally.

Reshma M R, Dept of CSE, RSET

Accessing I/O devices
• Recall that the rate of transfer to and from I/O devices is slower than the speed of
the processor. This creates the need for mechanisms to synchronize data transfers
between them.

• Program-controlled I/O:
• Processor repeatedly monitors a status flag to achieve the necessary
synchronization.
• Processor polls the I/O device.

Reshma M R, Dept of CSE, RSET

Accessing I/O devices
Two other mechanisms used for synchronizing data transfers between the processor
and memory:
▪ Interrupts
• Synchronization is achieved by having the I/0 device send a special signal over
the bus whenever it is ready for a data transfer operation.
▪ Direct Memory Access
• Used for high-speed I/0 devices.
• It involves having the device interface transfer data directly to or from the
memory, without continuous involvement by the processor.

Reshma M R, Dept of CSE, RSET

Interrupts
• In program-controlled I/O, when the processor continuously monitors the status of
the device, it does not perform any useful tasks.
• An alternate approach would be for the I/O device to alert the processor when it
becomes ready.
• By sending a hardware signal called an interrupt to the processor.
• At least one of the bus control lines, called an interrupt-request line is
dedicated for this purpose.
• Processor can perform other useful tasks while it is waiting for the device to be
ready.

Reshma M R, Dept of CSE, RSET

 Interrupts
• Processor is executing the instruction located
at address i when an interrupt occurs. Program 1
Interrupt Service
• Routine executed in response to an interrupt routine

request is called the interrupt-service routine. 1

• When an interrupt occurs, control must be 2

transferred to the interrupt service routine.

• But before transferring control, the current Interrupt
occurs i
here
contents of the PC (i+1), must be saved in a i +1
known location.
• This will enable the return-from-interrupt M
instruction to resume execution at i+1.
• Return address, or the contents of the PC are
usually stored on the processor stack.
Reshma M R, Dept of CSE, RSET
Interrupts
 Treatment of an interrupt-service routine is very similar to that of a subroutine.
 However, there are significant differences:

 A subroutine performs a task that is required by the calling program.

 Interrupt-service routine may not have anything in common with the program
it interrupts.

 Interrupt-service routine and the program that it interrupts may belong to

different users.

Reshma M R, Dept of CSE, RSET

Interrupts

 As a result, before branching to the interrupt-service routine, not only the PC,
but other information such as condition code flags, and processor registers
used by both the interrupted program and the interrupt service routine must be
stored.

 This will enable the interrupted program to resume execution upon return from
interrupt service routine.

Reshma M R, Dept of CSE, RSET

Interrupts
 Saving and restoring information can be done automatically by the processor or
explicitly by program instructions.

 Saving and restoring registers involves memory transfers:

 Increases the total execution time.
 Increases the delay between the time an interrupt request is received, and the
start of execution of the interrupt-service routine. This delay is called interrupt
latency.

Reshma M R, Dept of CSE, RSET

Interrupts
 In order to reduce the interrupt latency, most processors save only the minimal
amount of information:

 This minimal amount of information includes Program Counter and processor

status registers.

 Any additional information that must be saved, must be saved explicitly by the
program instructions at the beginning of the interrupt service routine.

Reshma M R, Dept of CSE, RSET

Interrupts
• When a processor receives an interrupt-request, it must branch to the interrupt
service routine.
• It must also inform the device that it has recognized the interrupt request.
• This can be accomplished in two ways:
• Some processors have an explicit interrupt-acknowledge control signal for this
purpose.
• In other cases, the data transfer that takes place between the device and the
processor can be used to inform the device.

Reshma M R, Dept of CSE, RSET

Interrupt hardware
•

INTR is an
active low
signal.

Reshma M R, Dept of CSE, RSET

Interrupts

 Interrupt-requests interrupt the execution of a program, and may alter the intended
sequence of events:

 Sometimes such alterations may be undesirable, and must not be allowed.

 For example, the processor may not want to be interrupted by the same device
while executing its interrupt-service routine.

 Processors generally provide the ability to enable and disable such interruptions as
desired.

Reshma M R, Dept of CSE, RSET

Interrupts

 One simple way is to provide machine instructions such as Interrupt-enable and

Interrupt-disable for this purpose.

 To avoid interruption by the same device during the execution of an interrupt

service routine:
 First instruction of an interrupt service routine can be Interrupt-disable.
 Last instruction of an interrupt service routine can be Interrupt-enable.

Reshma M R, Dept of CSE, RSET

The sequence of events involved in handling an interrupt
request from a single device:
1. The device raises an interrupt request.
2. The processor interrupts the program currently being executed and saves the
contents of the PC and status register PS registers.
3. Interrupts are disabled by clearing the IE bit in the PS to 0.
4. The action requested by the interrupt is performed by the interrupt-service
routine, during which time the device is informed that its request has been
recognized, and in response, it deactivates the interrupt-request signal.
5. Upon completion of the interrupt-service routine, the saved contents of the PC
and PS registers are restored (enabling interrupts by setting the IE bit to 1), and
execution of the interrupted program is resumed.

Reshma M R, Dept of CSE, RSET

Handling Multiple Devices

 Multiple I/O devices may be connected to the processor and the memory via a
bus. Some or all of these devices may be capable of generating interrupt requests.

 Each device operates independently, and hence no definite order can be

imposed on how the devices generate interrupt requests?

Reshma M R, Dept of CSE, RSET

Handling Multiple Devices
• How does the processor know which device has generated an interrupt?

• How does the processor know which interrupt service routine needs to be
executed?

• When the processor is executing an interrupt service routine for one device, can
other device interrupt the processor?

• If two interrupt-requests are received simultaneously, then how to break the tie?

Reshma M R, Dept of CSE, RSET

Handling Multiple Devices
 Consider a simple arrangement where all devices send their interrupt-requests
over a single control line in the bus.

 When the processor receives an interrupt request over this control line, how does
it know which device is requesting an interrupt?

 This information is available in the status register of the device requesting an

interrupt:
 The status register of each device has an IRQ bit which it sets to 1 when it
requests an interrupt.

Reshma M R, Dept of CSE, RSET

Handling Multiple Devices

• Polling

• Vectored Interrupts

• Interrupt Nesting

Reshma M R, Dept of CSE, RSET

Handling Multiple Devices: Polling

 Interrupt service routine can poll the I/O devices connected to the bus. The first
device with IRQ equal to 1 is the one that is serviced.

 Polling mechanism is easy, but time consuming to query the status bits of all the
I/O devices connected to the bus.

 An alternative approach is to use a vectored interrupts

Reshma M R, Dept of CSE, RSET

Handling Multiple Devices: Vectored Interrupts
• To reduce the time involved in polling , a device requesting an interrupt may
identify itself directly to the processor.

• Device can do so by sending a special code (4 to 8 bits) the processor over the
bus

• Code supplied by the device may represent a part of the starting address of the
interrupt-service routine.

Reshma M R, Dept of CSE, RSET

Vectored Interrupts
• The remainder of the address is obtained by the processor based on other
information such as the range of memory addresses where interrupt service
routines are located.

• The Interrupt Service Routine for a device must always starts at the same location.

• Usually, the location pointed to by the interrupting device is used to store the
starting address of the interrupt-service routine.

• The processor reads this address, called the interrupt vector and loads it into the
PC
Reshma M R, Dept of CSE, RSET
Handling Multiple Devices: Interrupt Nesting
• Previously, before the processor started executing the interrupt service routine for
a device, it disabled the interrupts from the device.

 In general, same arrangement is used when multiple devices can send interrupt
requests to the processor.
 During the execution of an interrupt service routine of device, the processor
does not accept interrupt requests from any other device.
 Since the interrupt service routines are usually short, the delay that this causes
is generally acceptable.

Reshma M R, Dept of CSE, RSET

Interrupt Nesting

 However, for certain devices this delay may not be acceptable.

▪ Which devices can be allowed to interrupt a processor when it is executing an

interrupt service routine of another device?

▪ I/O devices are organized in a priority structure:

▪ An interrupt request from a high-priority device is accepted while the
processor is executing the interrupt service routine of a low priority device.

Reshma M R, Dept of CSE, RSET

Interrupt Nesting : Priority Scheme
• A priority level is assigned to a processor that can be changed under program
control.

• Priority level of a processor is the priority of the program that is currently

being executed.
• When the processor starts executing the interrupt service routine of a device,
its priority is raised to that of the device.
• If the device sending an interrupt request has a higher priority than the
processor, the processor accepts the interrupt request.

Reshma M R, Dept of CSE, RSET

Interrupt Nesting : Privileged Instruction
• Processor’s priority is encoded in a few bits of the processor status register.

• Priority can be changed by instructions that write into the processor status
register.
• Usually, these are privileged instructions, or instructions that can be executed
only in the supervisor mode.
• Privileged instructions cannot be executed in the user mode.
• Prevents a user program from accidentally or intentionally changing the
priority of the processor.

Reshma M R, Dept of CSE, RSET

Interrupt Nesting : Privileged Exception

• If there is an attempt to execute a privileged instruction in the user mode, it causes

a special type of interrupt called as privilege exception.

• A multiple-priority scheme can be implemented easily by using separate Interrupt

Request and Interrupt Acknowledgement lines for each device.

Reshma M R, Dept of CSE, RSET

Interrupt Nesting: Multiple-priority scheme

IN T R 1 INTR p
Processor

Device 1 Device 2 Device p

INTA1 INTA p

Priority arbitration

Implementation of interrupt priority using individual Interrupt

Request and Interrupt Acknowledgement lines

Reshma M R, Dept of CSE, RSET

Interrupt Nesting
• Each device has a separate interrupt-request and interrupt-acknowledge line.

• Each interrupt-request line is assigned a different priority level.

• Interrupt requests received over these lines are sent to a priority arbitration circuit
in the processor.

• If the interrupt request has a higher priority level than the priority of the processor,
then the request is accepted.

Reshma M R, Dept of CSE, RSET

Simultaneous Requests
• Which interrupt request does the processor accept if it receives interrupt requests
from two or more devices simultaneously?.

• If the I/O devices are organized in a priority structure, the processor accepts the
interrupt request from a device with higher priority.

• However, if the devices share an interrupt request line, then how does the
processor decide which interrupt request to accept?

Reshma M R, Dept of CSE, RSET

Simultaneous Requests

• Polling scheme (software solution)

• Daisy chain scheme (hardware solution)

Reshma M R, Dept of CSE, RSET

Polling scheme
• Simplest mechanism is polling

• If the processor uses a polling mechanism to poll the status registers of I/O devices
to determine which device is requesting an interrupt.

• In this case the priority is determined by the order in which the devices are polled.

• The first device with status bit set to 1 is the device whose interrupt request is
accepted.

Reshma M R, Dept of CSE, RSET

Daisy chain scheme
• Devices are connected to form a daisy chain.
• Devices share the interrupt-request line, and interrupt-acknowledge line is
connected to form a daisy chain.
• Here the INTA signal propagates serially through the devices.
• When devices raise an interrupt request, the interrupt-request line is activated.
• The processor in response activates interrupt-acknowledge.
• Received by device 1, if device 1 does not need service, it passes the signal to
device 2.
• Device that is electrically closest to the processor has the highest priority.
• This scheme requires considerably fewer wires than the individual connections.

Reshma M R, Dept of CSE, RSET

Daisy chain scheme
INTR

Processor

Device 1 Device 2 Device n

INTA

Devices share the interrupt-request line, and interrupt-acknowledge line is

connected to form a daisy chain fashion, such that the INTA signal propagates
serially through the devices

Reshma M R, Dept of CSE, RSET

Daisy chain scheme
• When I/O devices were organized into a priority structure, each device had its own
interrupt-request and interrupt-acknowledge line.

• When I/O devices were organized in a daisy chain fashion, the devices shared an
interrupt-request line, and the interrupt-acknowledge propagated through the
devices.

• A combination of priority structure and daisy chain scheme can also used.(general
structure)

Reshma M R, Dept of CSE, RSET

 Arrangement of priority groups
INTR 1

• Devices are organized into

INTA1
Device Device
groups.
• Each group is assigned a
Processor

IN T R p different priority level.

• All the devices within a single
Device Device
group share an interrupt-request
INTA p
line, and are connected to form
Priority arbitration
circuit a daisy chain.

Arrangement of priority groups

Reshma M R, Dept of CSE, RSET

Controlling device requests
 Only those devices that are being used in a program should be allowed to generate
interrupt requests.
 To control which devices are allowed to generate interrupt requests, the interface
circuit of each I/O device has an interrupt-enable bit.
 If the interrupt-enable bit in the device interface is set to 1, then the device is
allowed to generate an interrupt-request.
 Interrupt-enable bit in the device’s interface circuit determines whether the
device is allowed to generate an interrupt request.
 Interrupt-enable bit in the processor status register or the priority structure of
the interrupts determines whether a given interrupt will be accepted.

Reshma M R, Dept of CSE, RSET

Direct Memory Access
• Direct Memory Access (DMA):

• A special control unit may be provided to transfer a block of data directly

between an I/O device (an external device) and the main memory, without
continuous intervention by the processor. This approach is called Direct
Memory Access or DMA

• Control unit which performs these transfers is a part of the I/O device’s interface
circuit. This control unit is called as a DMA controller.

Reshma M R, Dept of CSE, RSET

Direct Memory Access
• DMA controller performs functions that would be normally carried out by the
processor when accessing the main memory:

• For each word transferred, it provides the memory address and all the control
signals.

• To transfer a block of data, it increments the memory addresses and keeps

track of the number of transfers.

Reshma M R, Dept of CSE, RSET

Direct Memory Access

 DMA controller can transfer a block of data from an external device to the
processor, without any intervention from the processor.

 However, the operation of the DMA controller must be under the control of a
program executed by the processor. That is, the processor must initiate the
DMA transfer.

Reshma M R, Dept of CSE, RSET

Direct Memory Access

• To initiate the DMA transfer, the processor informs the DMA controller of:

• Starting address,
• Number of words in the block.
• Direction of transfer (I/O device to the memory, or memory to the I/O device).

• On receiving this the DMA controller proceeds to perform the requested operation.

Reshma M R, Dept of CSE, RSET

Direct Memory Access

• Once the DMA controller completes the transfer of entire block (DMA transfer), it
informs the processor by raising an interrupt signal.

• When a DMA transfer is taking place the program that request the transfer cannot
continue and the processor can be used to execute another program.

• After the DMA transfer is completed, the processor can return to the program that
requested the transfer

Reshma M R, Dept of CSE, RSET

Registers in a DMA interface
• DMA Controller registers that are accessed by
the processor to initiate transfer operations.
• Two registers are used for storing the starting
address and the wordcount.
• The third register contains status and control
flags.
• The R/W bit determines the direction of the
transfer.
• When this bit is set to 1 by a program
instruction, the controller performs a read
operation, that is, it transfers data from the
memory to the I/O device.
• Otherwise, it performs a write operation.

Reshma M R, Dept of CSE, RSET

Registers in a DMA interface

• When the controller has completed transferring a block of data and is ready to
receive another command, it sets the Done flag to 1.

• Bit 30 is the Interrupt-enable flag, IE.

• When this flag is set to 1, it causes the controller to raise an interrupt after it
has completed transferring a block of data.

• Finally, the controller sets the Bit 31 (IRQ bit) to 1 when it has requested an
interrupt.

Reshma M R, Dept of CSE, RSET

DMA Controller in Computer Architecture

Reshma M R, Dept of CSE, RSET

 Use of DMA controllers in a computer system
• DMA controller connects a high-speed network to
Main the computer bus.
Processor
memory
• Disk controller, which controls two disks also has
System bus
DMA capability. It provides two DMA channels.
Disk/DMA DMA
controller controller Printer Keyboard • It can perform two independent DMA operations, as
if each disk has its own DMA controller.

Disk Disk Network • The registers to store the memory address, word
Interface
count and status and control information are
duplicated.

Reshma M R, Dept of CSE, RSET

Use of DMA controllers in a computer system
• To start a DMA transfer of a block of data from the main memory to one of the
disks, a program writes the address and word count information into the registers
of the corresponding channel of the disk controller.
• It also provides the disk controller with information to identify the data for future
retrieval.
• The DMA controller proceeds independently to implement the specified operation.
• When the DMA transfer is completed, this fact is recorded in the status and
control register of the DMA channel by setting the Done bit.
• At the same time, if the IE bit is set, the controller sends an interrupt request to the
processor and sets the IRQ bit.
• The status register can also be used to record other information, such as whether
the transfer took place correctly or errors occurred.

Reshma M R, Dept of CSE, RSET

DMA controllers

 Processor and DMA controllers have to use the bus in an interwoven fashion to
access the memory.

 DMA devices are given higher priority than the processor to access the bus.

 Among different DMA devices, high priority is given to high-speed peripherals

such as a disk or a graphics display device.

Reshma M R, Dept of CSE, RSET

DMA controllers
 Processor originates most memory access cycles on the bus.

 DMA controller can be said to “steal” memory access cycles from the bus. This
interweaving technique is called as “cycle stealing”.

 An alternate approach is to provide a DMA controller an exclusive capability to

initiate transfers on the bus, and hence exclusive access to the main memory. This
is known as the block or burst mode.

Reshma M R, Dept of CSE, RSET

DMA Transfer Modes
• Burst Mode
• When the CPU gives the DMA controller access to the system bus, the DMA
controller transfers the whole data block in one contiguous sequence.
• Once completed, control of the bus reverts back to the CPU.
• When the data is being transferred to the memory or from the memory, the CPU
remains idle for relatively long periods of time or the CPU is in a kind of HOLD
state.
• The CPU exits from this state only after the DMA request signal is withdrawn
from the I/O device.
• The hold duration depends on the speed of the memory, I/O device, and number of
bytes to be transferred.
Reshma M R, Dept of CSE, RSET
DMA Transfer Modes
• Cycle-Stealing Mode
• The CPU after receiving the DMA request signal from the peripheral, will attend
to the current instruction, it is doing and suspends its operation for the next time
slice (machine cycle).
• During the next time slice, the DMA transfer takes place and one word is
transferred between the peripheral device and the main memory.
• On completion of the transfer, the CPU can resume to its normal operation. DMA
transfers are essentially time-sliced with the operations of the main memory.
• Here, the DMA controller can be regarded as “stealing” memory cycles from the
CPU. Hence, this technique is known as cycle stealing.

Reshma M R, Dept of CSE, RSET

DMA Transfer Modes
• Transparent mode
• The DMA controller transfers data only when the CPU is executing operations that
don't use system buses.
• With this DMA transfer method, the CPU doesn't have to stop performing its
operations.
• Transparent mode DMA operations takes the longest to transfer data blocks, but
it's the most efficient mode in terms of system performance.

Reshma M R, Dept of CSE, RSET