J Comput Electron

DOI 10.1007/s10825-017-0963-1

Novel 8-bit reversible full adder/subtractor using a QCA

reversible gate
Moein Kianpour1 · Reza Sabbaghi-Nadooshan2

© Springer Science+Business Media New York 2017

Abstract Conventional digital circuits consume a consider- 1 Introduction

able amount of energy. If bits of information remain during
logical operations, power consumption decreases consider- Quantum-dot cellular automata (QCA) are good replace-
ably because the data bits in reversible computations are not ments for CMOS devices on the nanoscale. After decades
lost. The types of reversible gate used in quantum compu- of growth, the minimum size in CMOS technology remains
tations are quantum-dot cellular automata (QCA), nuclear limited. This limitation has promoted the rapid development
magnetic resonance, and optical computations. QCA systems of molecular devices on the nanoscale. Researchers have
offer low power consumption, high density, section regular- reported that QCA can be used to create devices of high
ity and support new devices designed for nanotechnology. density, low power consumption, very high switching speed
A QCA-based reversible gate has minimal delay, complex- and ability to serve as a pipeline. QCA was first postulated in
ity and considering the potential quality of a QCA pipeline, 1993 [1] and was fabricated in 1997 and is expected to play an
computes at maximum speed. The present study designed important role in nanotechnology [2]. Optimized designs for
a novel 3 × 3 reversible gate that is universal and testable. area, complexity and delay in QCA can be provided for com-
A reversible logic gate is also designed based on the major- mon reversible gates such as the controlled-NOT (CNOT),
ity gate in the QCA and as a QCA reversible (QR) gate. A Toffoli and Fredkin gates [3–5].
new 8-bit reversible full adder/subtractor based on the QR Several reversible gate plans have been presented based on
gate in QCA with a minimum number of cells and area com- QCA [6–10]. Ma et al. [7] implemented reversible gates for
bines both designs for implementation of a reversible full QCA and denoted them QCA1 and QCA2. They continued to
adder/subtractor in QCA. The performance of these gates use impracticable next near-neighbor coplanar wire crossing,
was compared with testable Fredkin and Toffoli gates and which was first introduced in 1994. Subsequent studies have
improved performance of logic functions in terms of com- identified weaknesses with this type of wire crossing because
plexity and delay over those of the Fredkin and Toffoli gates. it has very low excitation energy between the ground state
and the first excited state which decreases its resistance to
Keywords Adder/subtractor · Defect · Fault tolerant · fabrication variation, thermal effects and stray charge. More
Majority gate · Quantum-dot cellular automata (QCA) · recently developed wire crossings do not exhibit these short-
Reversible gate comings.
This paper introduces a new design for a QCA reversible
gate (QR) in which the majority gate is implemented and
B Reza Sabbaghi-Nadooshan simulated in QCA using a robust vertical and horizontal
[email protected] crossing [11]. A novel 8-bit full adder/subtractor based on
1 a QR gate in QCA with a minimum number of cells and
Young Researchers and Elite Club, Islamic Azad University,
Central Tehran Branch, Tehran, Iran area combines both designs. Optimized implementation of
2 CNOT, Fredkin and Toffoli gates are presented in which the
Electrical Engineering Department, Islamic Azad University,
Central Tehran Branch, Niayesh Building, Emam Hasan complexity, size and delay are optimized to improve effi-
Blvd., Pounak, Tehran, Iran ciency.

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 J Comput Electron

Section 2 provides a background of the devices. Sec- values. It is assumed that tunneling out of the cell is not pos-
tion 3 proposes a reversible gate in QCA. Section 4 presents sible because of the existence of large potential barriers.
the proposed QR gate and adder/subtractor for the QR There are four classes of QCA implementation: metal-
gate. In Sect. 5, implementation of the reversible 8-bit full island [13–15], semiconductor [16,17], molecular [18,19]
adder/subtractor in QCA and defect analysis is presented. and magnetic [20–22]. More promising implementations
Section 6 reports the results of simulation. Section 7 con- have been proposed that are based on nanomagnets and
cludes the paper. molecules. In the magnetic case, single-domain nanometer
pill-shaped magnets exhibit up and down stable magnetic
states [20,23]. Figure 1a shows the QCA single-domain
2 Background nanomagnets and nanomagnet QCA majority voter gate. Lent
theory [1] states that the smallest and best-performing QCA
2.1 Reversible computing cell can be implemented with a molecular system. A QCA
cell could be physically implemented using a molecular sys-
Output carry calculation in common computers is irre- tem with two or less centers, a charge configuration within
versible; once a logic block generates the output bits, the the molecule that encodes the logical state and the electro-
input bits are destroyed. This process consumes power in static repulsion that provides the device–device interaction.
the system. Landauer [4] showed that each bit of data Molecular implementation is expected to reach very high
lost in irreversible logic computation generates K B T × frequencies (THz) and exceptional compactness [18,24].
Ln(2) thermal energy (K B = Boltzmann’s constant, T = Figure 1b shows possible molecules for QCA and the molec-
absolute temperature). The amount of energy wasted on ular QCA majority voter.
erased bits for the current clock speed in computers is not con- In the molecular scale QCA, the electronic charge was
siderable; however, if clock speed increases, the frequency arranged to store and transmit information. The binary data
of lost bits will increase. can be coded as -1 and 1 polarities for 0 and 1, respectively,
Reversible logic circuits avoid energy waste by not count- to create the binary in the QCA (Fig. 1c). If two cells are adja-
ing the calculation data, thereby recovering energy into the cent, the Coulomb interaction between the electrons causes
system [12]. Bennett [3] found that very low power con- the cells to have equal polarization and equal portions of the
sumption is possible in logic circuits if only one circuit is left-side cell. The most essential logic gate in the QCA is the
combined with the logic gates. A gate is logical reversible majority gate. The logic equation for a majority gate (1) is:
if, for each distinct input, a distinct output exists. Reversible
gate input can be determined by its output [3]. A reversible M(A, B, C) = AB + AC + BC (1)
logic gate should have equal numbers of input and output.
Reversible gates are balanced; a circuit combining reversible Holding the polarization of one majority gate input
gates with no constants in its input satisfies the balance func- constant at 1 or 0 achieves either an OR or AND gate, respec-
tion. Reversible gates can satisfy a non-balanced function tively. Another useful gate in the QCA is the NOT gate, or the
only using garbage outputs. same inverter. Two common examples and one new example
Reversible computations analyze the ratio between con- of this gate are shown in Fig. 1e. Using the AND, OR and
sumed energy and logic computation. At the logic level, they NOT gates, any combination logic circuits can be designed
are applied by establishing a one-to-one layout between the and implemented. In Fig. 1f, several QCA cells are located
input and output of a circuit. Reversible computation has next to adjacent to one another and form a wire in QCA that
been widely studied. In most designs, the analysis is based is either 45◦ or 90◦ . Both wires are frequently used in cross-
on mathematics, is independent of the technology and a overs and arrays [25–29].
gate with reversible computation at the logic level has been QCADesigner is generally used to simulate the QCA cir-
provided. In the less applied analysis, modern technology cuits. Only normal cells (in four zones), rotate cells, fix
offering computational reversibility has been used. polarization cells and input/output cells are used in the
design. They are illustrated in Fig. 2a, b, d, e.
2.2 QCA overview
2.3 QCA clocking
The main QCA unit is a cell that contains four quantum dots
located at the apexes of a quadrangle. In each cell, 2 electrons All circuits recommended in the QCA require a clock for
can be positioned only in the diametric mode in accordance simultaneity, to control the data currents and to provide the
with Coulomb electrostatic interaction. These electrons are required power for the circuit setup. QCA computations are
controlled by potential barriers and could be displaced by tun- applied by controlling the tunneling with four clock signal
neling, control of the potential barriers, or creation of binary phases (Fig. 3). Clocking in the QCA is performed by con-

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Fig. 1 a Single-domain nanomagnets and nanomagnet QCA majority voter gate, b possible molecule for QCA and molecular QCA majority voter,
c basic QCA logic devices: QCA cell, d majority voter (MV), e inverter, f binary wire and inverter chain

Fig. 2 QCADesigner cells: a normal cells (in four zone), b rotate cells, c fix polarization cells, d input/output cells

trolling the potential barriers between the adjacent quantum method is logically irreversible because the data are lost in
dots. The clock used in the QCA has switch, relax, release the minority input during computation. Bennett clocking pro-
and hold phases. Each phase is 90◦ behind the other. vides a practical study of reversible computation using QCA.
During the switch phase, potential barriers between the It is also possible to design a system using Bennett clocking
quantum dots gradually rise and the QCA cell is placed in with zero power consumption.
one of the two polarization modes according to its adjacent The clock frequency used for the magnetic QCA is 100
cell. During the hold phase, barriers between the quantum MHz, which is the best theoretical frequency obtained using
dots remain at their highest levels, which prevents electron adiabatic switching. It is theoretically possible to obtain a
tunneling where the QCA cell remains at the same polariza- clock frequency of about 1 GHz, and a molecular QCA can
tion. During the release and relax phases, barriers between operate at a frequency of 1 THz. This is the absolute best case
the quantum dots decrease and are minimized in the relax scenario that does not take into account the speed of the drive
mode and the electrons can move inside the cell and displace circuits and technological issues caused by molecular circuit
along the cell. This clock signal may be generated by an fabrication [31,32]. For the molecular case, energy consump-
inductor electric field via CMOS wires at the lower layer of tion for each molecule is 2 eV per switching and the energy
the QCA in embedded form [2,30]. dissipation is very high [31,32]; because the frequency cho-
In the QCA, control of the saving and deletion of data sen is 1 THz, an electric field of 1.5 V/nm is used for clock
in the cells is done using one of two clocking methods. loss estimation [31,32]. When the clock period lowers to 10
Landauer clocking logical irreversibly deletes the data, but GHz, the energy dissipation is lower than kTln(2), which is
power consumption during saving and deletion can be option- in consistent that there is no limitation of energy dissipation
ally decreased. In addition, the majority gate function in this for reversible computing.

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computation are not lost, which leads to the development of

reversible gates. Major problems for synthesis by reversible
logic are as follows:

• Fan-out is unpermitted.
• Feedback from gate outputs to the inputs is unpermitted.

A logic synthesis technique that uses a reversible gate

should have the following characteristics [12]:

• Using the minimum garbage outputs.

• Using the minimum input constants.
• Using the minimum area.
Fig. 3 Four phases of the QCA clock
• Using the minimum number of gates.

Table 1 Truth table of the A B X Y Several reversible gates have been developed. Three
CNOT gate
important types are the CNOT, Toffoli and Fredkin gates
0 0 0 0
[33,34]. A reversible gate of considerable importance in
0 1 0 1
quantum computing is the 2-bit CNOT. The truth table for
1 0 1 1
CNOT is shown in Table 1, and the circuit icon is shown in
1 1 1 0
Fig. 4. The effect of the controlled-NOT gate is to conduction
the bit value of the second bit if and only if the first bit is set
to 1. In this paper, implementation of the CNOT gate using
3 Reversible gate QCA technology required 81 cells that occupied an area of
0.08 µm2 . When implementing the CNOT gate in QCA, its
Conventional digital circuits consume a considerable amount delay was 1 clock cycle (4 clock phases).
of power. In order to prevent them from destroying the data In a Toffoli gate, all the inputs from 1 to (n-1) pass through
bits during logic operation, they are designed so that the the output with no change and the nth output is controlled by
power consumption can decrease. The data bits in reversible 1 to (n −1) inputs. When all the inputs from 1 to (n −1) equal

Fig. 4 a CNOT gate schematic,

b CNOT gate, c CNOT gate in
QCA

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Table 2 Truth table of the A B C X Y Z controlled by A. These two inputs can be swapped using
Toffoli gate another input by swapping control. Figure 7b depicts the opti-
0 0 0 0 0 0 mized implementation of a Fredkin gate in QCA. In this
0 0 1 0 0 1 paper, implementation of the Fredkin gate using QCA tech-
0 1 0 0 1 0 nology required 94 cells that occupied an area of 0.09 µm2 .
0 1 1 0 1 1 As observed in Fig. 7, the delay of the Fredkin gate is 0.75
1 0 0 1 0 0 clock cycles (3 clock phases), which is an improvement over
1 0 1 1 0 1 previous studies.
1 1 0 1 1 1
1 1 1 1 1 0
4 Novel QCA reversible gate
Table 3 Truth table of the A B C X Y Z 4.1 Proposed QR gate
Fredkin gate
0 0 0 0 0 0
The proposed logic 3-input 3-output reversible gate based
0 0 1 0 1 0
on the majority gate in QCA is composed of three 3-input
0 1 0 0 0 1
majority gates. It is evident that this design requires minimal
0 1 1 0 1 1
area, complexity and delay [35].
1 0 0 1 0 0
The QR (QCA Reversible gate) has an output function as
1 0 1 1 0 1
follows:
1 1 0 1 1 0
1 1 1 1 1 1 • X = M(A, B, C) = AB + AC + BC;
• Y = M(A, B  , C  ) = AB  + AC  + B  C  ;
• Z = M(A , B  , C) = A B  + A C + B  C.

Table 4 is the QR gate truth table. The logic layout of this

reversible gate in QCA is shown in Fig. 8a, and the imple-
mentation of the QR gate in QCA is shown in Fig. 8b. The
QR gate consists of 123 QCA cells and occupies an area of
0.10 µm2 . Figure 8 shows that the delay of the QR gate is 0.5
clock cycles (2 phases).
As shown in Table 4, the input pattern corresponding to an
output pattern can be exclusively singular. The implementa-
tion of this reversible gate only requires three majority gates
and is less complex with less delay than the other reversible
gates in the QCA. The 3-input 3-output reversible gate is
Fig. 5 a Toffoli gate schematic, b Fredkin gate schematic
more generalized than those of previous reversible computa-
tions. The QR gate allows the multiple tasks of the majority
1, the nth input is inverted and passes through its output, oth- gate to be embedded in one gate at the same time.
erwise the main signal passes. Tables 2 and 3 are truth tables
for Toffoli and Fredkin gates, and Fig. 5 shows the gates. 4.2 Proposed reversible full adder/subtractor with QR
The Toffoli gate [33,34] shown in Fig. 6a comprises 3 gate
inputs and 3 outputs. The optimized implementation of the
Toffoli gate in QCA technology is shown in Fig. 6b. In this The reversible full adder/subtractor is a combinational cir-
gate, the A and B inputs pass through the first and second cuit which performs arithmetic operations, i.e., addition and
outputs and the third output controls the inversion of C using subtraction, with binary digits. The present design uses a
A and B. The Toffoli gate proposed for QCA consists of 100 hierarchical circuit. First, a new QR gate based on QCA was
cells and occupies an area of 0.10 µm2 . When implementing designed in which the reversible full adder and subtractor
the Toffoli gate in QCA, its delay is 1.25 clock cycles (5 clock were developed. A series connection of two QR gates and
phases), which is an improvement over previous studies. one CNOT gate can sum or subtract three bit digits simulta-
The Fredkin gate [33,34] is shown in Fig. 7a. Input A neously. Figure 9 shows the logical block of this 3-bit binary
passes through the first input, and inputs B and C are swapped reversible full adder/subtractor. This circuit includes 3 inputs
in order to obtain the second and third outputs, which are and 5 outputs. Two input variables denoted as A and B show

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Fig. 6 a Toffoli gate, b Toffoli

gate in QCA

Table 4 Truth table of the QR A B C X Y Z

gate
0 0 0 0 1 1
0 0 1 0 0 1
0 1 0 0 0 0
0 1 1 1 0 1
1 0 0 0 1 0
1 0 1 1 1 1
1 1 0 1 1 0
1 1 1 1 0 0

= (AB + A B  )C + (A B + AB  )C 
= (AB + A B  + AC  + A C  + BC 
Fig. 7 a Fredkin gate, b Fredkin gate in QCA
+ B  C  )C + (A B + AB  )C 

= (AB + AC  + BC  ) + (A B  + A C 
two bits by adding or subtracting the value. Third input C 
+ B  C  ) C + (A B + AB  )C 
is the carry or borrow value resulting from the previous or 
next location and having a lower or higher value. Outputs = (AB + AC  + BC  ) + (A B  + A C 

G1 and G2 are garbage. Two outputs are necessary because + B  C  ) C+(A C  +B  C  )(AC  + BC  )

the sum or difference of three binary digits falls between 0 = (AB + AC  + BC  ) + (A B  + A C 
and 3, but numbers 2 and 3 need two binary digits. Three 
+ B  C  ) C + (A C  + B  C 
outputs denoted as sum/difference, Cout and Bout are for the
sum or difference, carry or borrow digits. The truth table of + A B  )(AC  + BC  + AB)
 
the reversible full adder/subtractor is shown in Table 5. = M M(A , B  , C  ), C, M(A, B, C  )
 
The Sum/Deduce (2), Cout (4) and Bout (5) value follows = M M(A, B, C), C, M(A , B  , C) (2)
these logical equations:
Cout = AB + AC + BC = M(A, B, C) (3)
    
Sum/Deduce = A ⊕ B ⊕ C = ABC + A B C Bout = A B + A C + BC = M(A , B, C)
   
+ A BC + AB C = M(A, B  , C  ) (4)

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Fig. 8 a Logic layout of QR

gate, b QR gate in QCA

5 Reversible 8-bit full adder/subtractor

implementation in QCA

5.1 8-Bit reversible adder/subtractor implementation in

QCA

The 8-bit reversible binary full adder/subtractor is a combi-

national circuit which performs arithmetic operations, i.e.,
Fig. 9 Reversible full adder/subtractor by QCA reversible (QR) gate
addition and subtraction, with binary digits designed as a
hierarchical circuit. The reversible QCA gate was designed
based on the majority gate in which the reversible full
Table 5 Truth table of a new reversible full adder/subtractor by QCA
adder/subtractor was developed. Using a series connection
reversible (QR) gate of 8 reversible full adder/subtractors, the sum or difference
of two 8-bit digits was obtained.
A B C Sum/Deduce Cout Bout
The 8-bit reversible full adder/subtractor is shown in
0 0 0 0 0 0 Fig. 11. A 2-to-1 multiplexer was used to select the mode
0 0 1 1 0 1 of operation of the circuit. In the add/sub selector, if the
0 1 0 1 0 1 mode is “0,” the subtraction operation occurs and, if it is
0 1 1 0 1 1 “1,” the add operation occurs. The QCA layout of the 8-bit
1 0 0 1 0 0 reversible full adder/subtractor can be seen in Fig. 12. The
1 0 1 0 1 0 circuit was designed and simulated for functional behav-
1 1 0 0 1 0 ior using QCADesigner (ver. 2.0.3). The proposed 8-bit
1 1 1 1 1 1 reversible adder/subtractor consists of 5489 cells covering
an area of 10.07µm2 .

The logical circuit with the layout of the reversible full 5.2 Defect analysis and proposed QCA reversible gates
adder/subtractor based on a QR gate in QCA is presented in
Fig. 10. The proposed reversible full adder/subtractor based Considerable progress has been made in the molecular manu-
on a QR gate is implemented in only one layer. It requires 399 facture of QCA, where each QCA cell is a molecule. Defects
cells and 8 clock phases (2 clock cycles) to generate correct in manufacturing can occur during the chemical synthesis
outputs and occupies an area of 0.50 µm2 . and deposition phases. Studies have shown that defects are

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Fig. 10 Reversible full adder/subtractor based on QCA reversible (QR) gate in QCA

Fig. 11 8-Bit reversible full adder/subtractor by QCA reversible (QR) gate

Fig. 12 8-Bit reversible full adder/subtractor in QCA

more likely to occur in the deposition phase and can result in results. The results show that the implementation of a testable
missing cells in the substrate [36,37]. Toffoli, Fredkin and QR reversible gate should be considered
The Toffoli, Fredkin and QR reversible gates were inves- and designed [34,38–41].
tigated for missing cells and possible defects. QCADesigner The tables list the set values of each input logic reversible
was used to investigate the 8 possible input vectors and the gate and its specified output without defects. In each case,
possibility of missing cells in the majority gates. Figure 13 one targeted cell is missing cell during simulation. In the
shows the Toffoli, Fredkin and QR cells that have having presence of defects, the output will be defects-free state or
possible missing cells. Tables 6, 7 and 8 show the respective have a specific defect.

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Fig. 13 QCA layout of possible missing cells of a Toffoli, b Fredkin and c QR gates

The simulation results were used to develop a minimal test Figure 14 shows the simulation of a Toffoli gate which
set to detect a single missing cell defect with main coverage reaches output using a 5-clock phase delay. Figure 15 shows
for each reversible gate. the simulated Fredkin gate which reaches output using a 3-
clock phase delay.
Figure 16 shows the simulation results of the proposed QR
6 Simulation result gate that reaches output in 0.5 clock cycles. In these figures,
all modes are followed exactly.
Table 9 presents a brief description of each parameter used for Figure 17 depicts the simulations results of the proposed
a simulation engine in a bistable approximation [2,28,30,42– 1-bit reversible full adder/subtractor based on QR gate in all
44]. modes.

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Table 6 Simulation results for defects in the Toffoli gate
Input vector Fault free out- Output of missing cell of Toffoli gate ((F): Faulty Output, (T ): True Output)
put
T1 (T ) T2 (F) T3 (T ) T4 (F) T5 (F) T6 (F) T7 (F) T8 (F) T9 (F) T10 (F) T11 (F) T12 (F) T13 (F) T14 (F) T15 (F) T16 (F)

A0 = 000 A0 = 000 A0 A1 A0 A0 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1
A1 = 001 A1 = 001 A1 A0 A1 A0 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1
A2 = 010 A2 = 010 A2 A2 A2 A2 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3
A3 = 011 A3 = 011 A3 A3 A3 A2 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3
A4 = 100 A4 = 100 A4 A5 A4 A4 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5
A5 = 101 A5 = 101 A5 A4 A5 A4 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5
A6 = 110 A7 = 111 A7 A7 A7 A7 A7 A7 A7 A7 A7 A7 A7 A7 A7 A7 A7 A7
A7 = 111 A6 = 110 A6 A6 A6 A6 A6 A7 A6 A6 A6 A6 A7 A6 A6 A7 A7 A7

Table 7 Simulation results for defects in the Fredkin gate

Input vector Fault free out- Output of missing cell of Fredkin gate ((F):Faulty Output, (T ):True Output)
put
F1 (F) F2 (F) F3 (F) F4 (T ) F5 (F) F6 (T ) F7 (T ) F8 (F) F9 (T ) F10 (F) F11 (F) F12 (F)

A0 = 000 A0 = 000 A2 A2 A2 A0 A2 A0 A0 A2 A0 A2 A2 A2
A1 = 001 A2 = 010 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2
A2 = 010 A1 = 001 A3 A3 A3 A1 A3 A1 A1 A3 A1 A3 A3 A3
A3 = 011 A3 = 011 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3
A4 = 100 A4 = 100 A6 A6 A6 A4 A6 A4 A4 A6 A4 A6 A6 A6
A5 = 101 A5 = 101 A7 A7 A7 A5 A7 A5 A5 A7 A5 A7 A7 A7
A6 = 110 A6 = 110 A6 A6 A6 A6 A6 A6 A6 A6 A6 A6 A6 A6
A7 = 111 A7 = 111 A7 A7 A7 A7 A7 A7 A7 A7 A7 A7 A7 A7
J Comput Electron
 Table 8 Simulation results of defect for QR gate
Input vector Fault free out- Output of missing cell of QR gate ((F):Faulty Output, (T ):True Output)
J Comput Electron

put
Q 1 (F) Q 2 (T ) Q 3 (F) Q 4 (T ) Q 5 (F) Q 6 (F) Q 7 (T ) Q 8 (F) Q 9 (T ) Q 10 (F) Q 11 (F) Q 12 (F) Q 13 (F) Q 14 (F) Q 15 (T )

A0 = 000 A3 = 011 A3 A3 A7 A3 A3 A3 A3 A3 A3 A3 A2 A2 A3 A3 A3
A1 = 001 A1 = 001 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A0 A1 A1
A2 = 010 A0 = 000 A4 A0 A4 A0 A4 A2 A0 A2 A0 A2 A1 A0 A0 A1 A0
A3 = 011 A5 = 101 A5 A5 A5 A5 A5 A5 A5 A7 A5 A5 A5 A5 A4 A5 A5
A4 = 100 A2 = 010 A2 A2 A2 A2 A2 A2 A2 A0 A2 A2 A2 A2 A3 A2 A2
A5 = 101 A7 = 111 A3 A7 A3 A7 A3 A5 A7 A5 A7 A5 A6 A7 A7 A6 A7
A6 = 110 A6 = 110 A6 A6 A6 A6 A6 A6 A6 A6 A6 A6 A6 A6 A7 A6 A6
A7 = 111 A4 = 100 A4 A4 A0 A4 A4 A4 A4 A4 A4 A4 A5 A5 A4 A4 A4
Parameter

Clock low
Cell width
Cell height

Clock high
Dot diameter

Radius of effect

Layer separation
Number of samples

Relative permittivity
Convergence tolerance

Clock amplitude factor

Maximum iteration per sample

2

100
12.9
5 nm

0.001
Value

65 nm
18 nm
18 nm
Table 9 Parameters model in the QCADesigner simulator

11.5 nm
3.8e−23 J
9.8e−22 J

Fig. 14 Simulation results for the proposed Toffoli gate in QCA

Fig. 15 Simulation results for the proposed Fredkin gate in QCA

50,000–1,000,000

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Table 10 Comparison between the Toffoli, Fredkin and QR gates pro-

vided in this paper and two prior QCA reversible gates [7]
Fredkin Toffoli QR QCA1 [7] QCA2 [7]

Delay (×10−10 s) 0.75 1.25 0.5 0.5 0.5

Complexity (#cell) 94 100 123 146 147
# MV 6 4 3 3 3
Area (µm2 ) 0.09 0.10 0.10 0.16 0.16

Table 11 Proposed reversible full adder/subtractor based on QR gate

in QCA
Area (µm2 ) Complexity Delay (×10−10 s) # QR
(#cells)

Proposed 0.50 399 2 2

reversible full
Fig. 16 Simulation results for the proposed QR gate in QCA adder/subtractor

Table 12 Comparison 8-bit adder/subtractor in QCA

Area Complexity Delay # Reversible
(µm2 ) (#cells) (×10−10 s) gate

Previous design 10.47 5786 27.25 Not reversible

[45]
Proposed design 10.07 5489 23 24

It can be seen that the proposed 8-bit reversible adder/

subtractor is more efficient in terms of area, complexity, delay
and reversible layout compared to 8-bit adder/subtractor
developed in [45].

7 Conclusion

Fig. 17 Simulation results for the proposed reversible full A new extendable design for a reversible gate (QR) in QCA
adder/subtractor based on QR gate in QCA has been proposed and explained. The new reversible full
adder/subtractor based on a QR gate in QCA uses a minimum
number of cells, area and delay. Toffoli and Fredkin gates
Optimized implementation was used to design the Toffoli, were designed and implemented with minimum delay, com-
Fredkin and QR gates in QCA. In Table 10, the 3 reversible plexity and area in QCA. The application of the QR gate and
gates and 2 QCA reversible gates from a previous study [7] reversible full adder/subtractor for the design and implemen-
were compared for delay, complexity, the number of majority tation of an 8-bit reversible adder/subtractor was explained.
gates and area. This new 8-bit reversible adder/subtractor was compared to
Table 11 shows the area, complexity, delay and num- those in prior works and was found to significantly improve
ber of QR gates in the proposed 1-bit reversible full delays, area and power consumption because both the 8-
adder/subtractor based on QR gate. bit adder and subtractor are reversible circuits. This 8-bit
Table 12 compares the area, complexity, delay and number reversible adder/subtractor can be used in processors with
of reversible gates in proposed 8-bit reversible adder/subtractor high operating speeds. This circuit is applicable to the core
with 8-bit adder/subtractor from previous studies [45]. of high-speed ALU processors.

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