Proceedings of the Third International Conference on Electronics and Sustainable Communication Systems (ICESC 2022)

IEEE Xplore Part Number: CFP22V66-ART; ISBN: 978-1-6654-7971-4

Analysis of Parallel Prefix Adders with

Low Power and Higher Speed
2022 3rd International Conference on Electronics and Sustainable Communication Systems (ICESC) | 978-1-6654-7971-4/22/$31.00 ©2022 IEEE | DOI: 10.1109/ICESC54411.2022.9885617

Deepak Mittal
Electronics and Communication
Department
GLA University
Mathura, India
[email protected]

Timing and power efficiency are the most crit ical issues for
Abstract— The addition of binary digits is regarded as one of the high-performance applications like adders. The binary
most essential operations in computer mathematics. To enhance addition operation may be expressed in many ways. When
the adder's efficiency, it must be both time and power efficient.
speed and space economy are important, a tree structure, such
Parallel prefix adders are more efficient than conventional
adders. Kogge-stone, Brent-kung, Ladner, and Fischer are just a as a parallel prefix structure, is utilized. Parallel prefixes
few of the adders that appear in this piece of art. Constructing an connect basic VLSI cells [9]. In th is research, we will
effective adder using the Brent Kung, Kogge-stone, and Ladner compare both carry look ahead adders and traditional add ers.
Fischer algorithms requires the use of parallel prefix The ripple carry adder, the Brent Kung adder, the Kogge stone
architecture. A comparison of the power consumption, delay, adder, the Ladner and Fischer adder, and are all known for
and transistor count of prefix adders is done in this research. their impressive amounts of power and speed. These adders
Keywords— Parallel prefix adder, Delay reduction, Digital logic may also be found in a variety of other configurations. There
structures, Digital design. are various approaches to dealing with the carry and sum
difficult ies at each bit location, and they are all different
I. INT RODUCT ION designs. D. Nikolas and G. Dimitrakopoulos speed up parallel
One of the most fundamental actions in computer science is prefix addition by saving one piece of logic [2]. Kogge-Stone
the addition of two binary data. When performing floating covers more territory than Brent–Kung, but it performs better
point operations, VLSI integer adders are often employed in with less fan out at each stride. Another issue with Kogge–
the data pipelines and address generators. As a direct result of Stone adders is their inability to be connected to a co mputer
this, adders are crucial co mponents of both general-purpose [13-15].
computers and digital signal processing computers. They are
also used to create encryption and hashing methods. There are II. APPROACHES OF PARALLEL PREFIX
several techniques and software implementations available for ADDITION
doing binary addition. In order to perform operations quickly,
tree structures, like parallel-prefix adders, are essential. Apply the associative operator 'o' to the issue that has turned
Parallel-prefix adders are essential to the operation of VLSI; into a parallel p refix problem. We develop a parallel prefix
adder and exp lain what a carry look ahead adder acco mplishes.
these adders rely on basic cells and ensure that consistent
connections are maintained between them [1]. As a result, For each of these terms, the definitions are as follows:
they are critical. Prefix structures allow for trade-offs in cell So= Po (Exor) Co
count, logic levels, and cell fan-out. This article co mpares the
most efficient adder designs. The carry-look ahead equations S1= P1 (Exor) C1
have been published in many variants. These articles feature S2 =P2 (Exor) C2
Ling carries, which simp lify carry co mputation and may result
in faster architectural designs. Most of the time, adders are S3 =P3 (Exor) C3
used in today's integrated circuits. Many adder designs have Ci= g i (OR) ki.
been designed to fulfil time and area efficiency requirements,
fro m ripple -carry adders to CLA, condit ional-sum, and Co =Co
parallel-p refix adders. Carry-skip and carry-select designs are C1=go (OR) po Co
small and have low latency. All of these ideas may be seen as
different techniques to calculate a carry signal at each b it point C2 =p 1 go (OR) g 1 (OR) p 1poCo
in the output. Ling [8] proposed that the encoding of the carry C3 = p 2 g 1 (OR) g 2 (OR) p 2 p 1 go (OR) p 2 p1p 0 C0
be divided between two signals rather than using a single
signal to encode the carry at each bit location. This would There are three types of carry-generated bits: "gi," "pi," and
simp lify the carry calculat ion unit by removing part of the the half-sum b it hi, all of which are co mputed at the pre-
complexity it normally has [5].

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 Proceedings of the Third International Conference on Electronics and Sustainable Communication Systems (ICESC 2022)
IEEE Xplore Part Number: CFP22V66-ART; ISBN: 978-1-6654-7971-4

processing step of the transmission process. Generate is we may say it functions as a buffer.
calculated as follows:
gi = ai (AND) bi
Propagate is calculated as follows:
pi= ai (OR) bi

The half sum bit is calculated as follows:

hi = (Exor)bi

The sum is calculated as follows:

Ci-1 = hi (Exor) Si

The letter "o" denotes an operator, while the symbol "O" (a)
denotes a node. The graph's edges are made up of pairs of To determine the prefix of two b it groups, the Brent Kung tree
input signals (gi, p i). A parallel prefix adder is seen in Brent structure is employed. These are essential in order to
Kung's artwork, wh ich shows an 8-bit Kogge stone. [2, 7, and successfully calculate the prefix for the four bit groups. The
8] exh ibit Kogge and Brent Kung adders. [3] The "o" operator four bit group is used to find an eight bit group. As a direct
and node's internal gate structure is shown. Kogge Stone consequence of this, the tree required '2(log2 N) - 2' stages to
developed this algorithm. It is larger, has more be complete. This build ing is shaped like a fan with two stages
interconnections, and uses simp ler circuitry, but it has a lo wer on each stage [2].
fan out and is sufficiently deep in operation. Brent Kung
adders have fewer co mputational nodes and a smaller area
since there are fewer interconnections, but their structure has
the greatest depth, which increases the circuit's latency when
compared to other structures.
III. IMPLEMENTATION
The parallel prefix adder structure of the bits Ki is shown for
design implementation. We'll use some examples.
K1= p1 (AND) g0
(b)
K2= P2 (AND) g1 (OR) P2 (AND) P1 (AND) g0 The Brent Kung and Sklansky adder Tree structures have been
combined to create the Ladner Fischer Tree structure. For odd
K3= P3 (A ND) g2 (OR) P3 (AND) P2 (A ND) g 1 (OR) P3 bits, it co mputes the prefix, while for even bits, it adds one
(AND) P2 (AND) P1 (AND) g0 step.

K4= P4 (A ND) g3 (OR) P4 (AND) P3 (A ND) g 2 (OR) P4

(AND) P3 (AND) P2 (AND) g1 (OR) P4 (AND) P3 (AND)
P2 (AND) P1 (AND) g0

K5 = P5 (AND) g4 (OR) P5 (AND) P4 (AND) g3 (OR) P5

(AND) P4 (AND) P3 (AND) g2 (OR) P5 (AND) P4 (AND)
P4 (AND) P3 (AND) P2 (AND) g1 (OR) P5 (AND) P4 (AND)
P3 (AND) P2 (AND) P1 (AND) g0 (OR) P5 (AND) P4 (AND)
P3 (AND) P2 (AND) P1 (AND) P0 (AND) Cin

Then we can write as Ki+1 = Pi+1 . (g i (OR)Ki) (c)

Each level of the Kogge-Stone adder tree has two fans. Th is Fig.1.(a) Diagram of Kogge Stone adder parallel prefix structure, (b)
will increase the size of the wire between the two stages. Diagram of Brent Kung adder parallel prefix structure, (c) Diagram of
Within the black bubble's internal circu itry, there are three Ladner- Fischer adder parallel prefix structure.
AND gates: one for generation and one each for propagation.
When a white bubble produces the same output as its input,

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 Proceedings of the Third International Conference on Electronics and Sustainable Communication Systems (ICESC 2022)
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The related prefix to the Carry look ahead adder is Kogge Prefix parallel adders like the Brent–Kung adder also include
stone adder. The Kogge–Stone adder (KSA or KS) is a a parameter called "carry-look-ahead" (CLA). He and his
parallel look-ahead adder. The Brent–Kung prefix adder is an partner Hsiang Te Kung came up with the concept in 1982. It
example of a parallel prefix adder (BKA), as are the Han– improved the adder's structure and decreased wire congestion.
Carlson (HCA) and Lynch–Swart zlander (LSTA) adders The Kogge–Stone adder was outperformed by this adder in
(STA) [6]. terms of speed and chip area use (KSA). Co mpared to ripple-
Despite being significantly larger than the Brent–Kung adder, carry adders, it's also a lot faster (RCA). The name o f these
the Kogge–Stone adder has less fan-out at each stage, early mu lti-bit adders comes fro m the ripple effect caused by
resulting in better performance for standard CMOS process the carry bit as it moves from right to left in the addition
nodes. However, wire congestion is a co mmon problem with process. These adders were the first of their kind. First ripple-
Kogge–Stone adders. To utilise the Lynch–Swartzlander carry adders produced. The length of the bit being added
architecture, the process node must be capable of handling determined the time required for addit ion. The carry is
Manchester carry chain imp lementations. The Lynch – calculated concurrently in Brent–Kung adders, which
Swart zlander design is less spreading out and does not suffer considerably reduces adding time. More research on Brent–
fro m cable congestion. The fundamental difficulty in Kung adders and other parallel adders has been conducted in
optimising parallel prefix adders is the same as the one attempt to reduce the amount of power utilised and chip area
addressed in Thomas Lynch's dissertation in 1996: needed while enhancing speed [11]. Th is has made these
Optimization of variable b lock size, mult i-level, and carry- adders acceptable for use in low-power applications. Brent–
skip adders [5]. Kung adders are made in a regular pattern to save ch ip size
The diagram illustrates a Kogge–Stone adder with four bits of and manufacturing t ime. It is possible to add an n -bit integer
data. There are "promote" and "generate" bits at every level, in the allotted time using just the available chip space, making
as previously stated. The final phase (vertically) is where the it an excellent choice adder for space constraints and
last generate bits, also known as the carry, are created. These performance optimization. Because of its symmetry and
bits are then XORed with the first propagate after the input, consistent manufacturing structure, it may be emp loyed in
which are represented by the red boxes, to generate the sum pipeline designs. When using parallel adders, the critical route
bits. To get the first (least impo rtant) sum b it, for examp le, we is determined by co mputing the carry fro m the least
use XOR to co mbine the value "1" in the red bo x on the far significant bit LSB to MSB and then making an effort to
right with the value "0" in the carry-in bo x, which ult imately reduce it as much as possible [12].
results in a value of "1." In the second fro m right bo x, a "0" is
produced when the XOR operation is performed on propagate
(also a "0") and C0 (also a "0"), which determines the second
bit [8].

Fig. 2 Kogge stone adder schematic

Fig.4 Brent Kung adder schematic

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 Proceedings of the Third International Conference on Electronics and Sustainable Communication Systems (ICESC 2022)
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IV. SIMULATION RESULTS

Ladner-parallel Fischer's prefix adder is called so that the The Kogge-stone parallel prefix adder, Brent-Kung parallel
addition process can be carried out. For the purpose of prefix adder, and Ladner Fischer parallel prefix adders are
performing the arith metic operation, it appears to be evaluated for power consumption and speed. Below are the
structured in a tree-like manner [4]. The Ladner-Fischer power d issipation and delay characteristics of many adders.
adder is used for high-performance addition. The black We may readily co mpare these efficiency features by using
and grey cells that make up the Ladner- Fischer adder [3]. this table.
Each dark co mpart ment is equipped with two AND gates T able 1 Delay and power measurements
and one OR gate [2]. Mult iplexers are circuits that have
several inputs but only one output. Each grey cell Name of Power Delay Numbe r of
contains just one AND gate. As stated in equation 1, Pi the dissipation in calculation in Transistors
represents propagate and is made up of a single AND adder microwatts nano seconds
gate [5]. Gi stands for generate, and it is made up of one
Kogge Stone 7.22 59.02 564
AND gate and one OR gate [6, as shown in equation 2] adder
[14].
Brent Kung 3.98 37.88 378
Pi = Bi AND Bi−1 − − − − − (1) Adder

Gi = A i OR [Bi AND A i−1 ] – (2) Ladner 2.27 36.98 402

Fischer
Adder
Gi denotes generate and it consists of one OR gate and
AND gate given in equation 3.
Simp ly put, the Ladner Fischer adder uses 74.7 percent less
Gi−2 = A i−2 OR [Bi−2 AND A i−1 ] − (3) electricity and 218 percent less power than the parallel prefix
adder developed by Brent Kung. Ladner Fischer parallel
prefix adder outperformed both Brent Kung adder and Kogge
stone parallel prefix adder by a margin of 2.65 percentage
points and 56 percentage points, respectively. Kogge's adder
uses 218 percent more power than Ladner Fischer's. Brent
Kung adder consumes 74.87 percent more energy than Ladner
Fischer adder. Parallel prefix adder co mparisons between the
Kogge Stone and Brent Kung parallel p refix adders yield
savings of 49.2 percent and 6.349 percent, respectively, in
transistor count.

CONCLUSION
In this wo rk, the architecture of a parallel prefix adder is
demonstrated. Ladner Fischer's parallel prefix adder is faster
and uses less power than Brent Kung's and Kogge Stone's.
The Ladner Fischer parallel prefix adder consumes
significantly less power than other types of adders. Brent
Kung's parallel prefix adder has fewer transistors than Ladner
Fischer's and Kogge Stone's.

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