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FULL NAME OF STUDENT: TAWANDA MAGWENZI PIN:P2135871A

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COURSE NAME: Computer Architecture COURSE CODE: BSEH351

ASSIGNMENT NO. e.g. 1 or 2: 1 DUE DATE: 19 April

ASSIGNMENT TITLE: ASSIGNMENT 1

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Question 1

(a) With an aid of a diagram, discuss the Memory Hierarchy in computer system
regarding Speed, Size and Cost [10 Marks]
The Memory Hierarchy in a computer system organizes memory components based on their
speed size and cost
Registers: These are small, high speed memory units located within the CPU. Registers Store
frequently used data and instructions. They have the fastest access time but limited storage
capacity(16-64 bit)
Cache Memory: Cache memory is small fast memory unit close to the CPU which stores
recently accessed data from main memory, cache memory is more expensive and has limited
size.
Main memory (Random Access Memory) is the primary memory of a computer system. It has
larger storage capacity than cache memory but slower. Random Access Memory holds data
and instructions currently in use by the CPU
Secondary Storage (Hard Disk Drive , Solid State Drive): Secondary storage provides non
volatile memory with even larger capacity. Access time is slower compared to Main memory.

(b) What is Virtual Memory? Explain the need for Virtual Memory [10 Marks]
Virtual memory is a memory management technique used by operating systems which
allows a computer to temporarily increase the capacity of its main memory (Random Access
Memory) by utilizing secondary memory, such as a hard drive or solid-state drive.
Address Translation .In virtual memory, the addresses used by a program are distinct from
the addresses used by the memory system to identify physical storage locations .The virtual
memory manager dynamically translates logical addresses into physical addresses during
runtime. Virtual memory creates an illusion of a memory space larger than the actual
physical memory. It allows processes to operate with only some portions of their address
space in memory at any given time.

Need for Virtual Memory

The need for virtual memory arises due to several reasons:
Scarcity of Physical Memory:
Physical RAM is limited in size. Virtual memory compensates for this scarcity by using
secondary storage such as a hard disk as an extension of RAM.

2. Multitasking and Process Isolation:

Modern operating systems support multitasking, where multiple processes run
concurrently.
Each process requires its own memory space. Virtual memory ensures that each process has
its own mapping, allowing them to coexist without interference.

3.Flexible Address Space:

Virtual memory allows programs to use a non contiguous address space. Each program can
store data wherever it wants, making memory allocation more flexible.

4.Debugging and Security:

Virtual memory facilitates debugging by providing options to check for unallocated memory
and null pointers. It enhances data security by isolating processes from one another.

(c) Sketch the internal organization of CPU out with its functionalities and block diagram
[10 Marks]

1.Input Unit:
The input unit receives data from devices like keyboards, mice, and scanners. It processes user-
provided data, converting it into binary format for computer comprehension. Transformed data is
then transmitted to the computer's main memory.

2.Memory Unit:
The memory unit stores instructions, data, and intermediate results. It plays a crucial role in data
storage and processing.

3. Control Unit (CU):

The control unit coordinates communication within the CPU. It decides which circuits need
activation, ensuring seamless execution of instructions.

4. Arithmetic Logic Unit (ALU):

The ALU performs arithmetic and logical operations. It operates on data fetched from primary
storage under the control of the control unit.

5. Registers and Buses:

Registers store temporary data during processing. Buses facilitate data movement between different
components.

6.Input Unit: Receives user data, converts it to binary, and transmits it to memory.

7.Memory Unit: Stores and processes data.

9. CPU: Accesses relevant data from primary storage, performs operations using the ALU, and
ensures seamless functionality.

10. Output Unit: Receives the finalized processed output.

(d) Describe the role of the 5 registers of the simple machine [10 Marks]
1.Memory Data Register:
The MDR stores data that is either sent to or fetched from memory. When the CPU needs to
read data from memory or write data to memory, it interacts with the MDR. It acts as a
temporary buffer for data during memory operations.

2. Current Instruction Register :

The CIR holds the actual instruction that is being decoded and executed by the CPU. When
an instruction is fetched from memory, it resides in the CIR during execution. The CPU
interprets the opcode and operands from the CIR to perform the appropriate operation.

3.Accumulator :
The accumulator serves as a central point for arithmetic and logical operations within the
CPU. It fetches data from memory and stores intermediate results during calculations.
Common arithmetic operations (addition, subtraction, multiplication, division) take place in
the accumulator. The final result may be stored in the accumulator or transferred to other
registers or memory locations.

4. Interrupt Register :
The IR manages requests from input or output devices. When an input or output device
needs attention it triggers an interrupt. The CPU responds by saving the current state of
execution and handling the interrupt request.

5. Program Counter Register:

The program counter keeps track of the memory address of the next instruction to be
fetched and executed. As the CPU executes each instruction in sequence, the program
counter is updated to indicate the next instruction's address in memory. This process
continues until the program's execution is complete.

Question 2
(a) With an aid of a diagram, explain what the term “pipelining” means. In your explanation,
outline the benefits and basic operation of a pipelined architecture compared with a non-
pipelined architecture. [10 Marks]

Pipelining is a technique used to enhance the performance of processors by breaking down

the execution of instructions into smaller stages. Each stage operates concurrently, allowing
multiple instructions to progress through the pipeline simultaneously.
Operation of Pipelining:
1. Instruction Fetch :
The first stage fetches the next instruction from memory. The fetched instruction resides in
the instruction register .

2. Instruction Decode :
In this stage, the opcode (operation code) of the instruction is decoded. Operand addresses
are determined.

3. Address Generation :
The AG stage calculates memory addresses for data access. It prepares to fetch operands.

4. Data Fetch :
Operands (data) are fetched from memory or registers. These operands are needed for the
execution phase.
5. Execution :
The actual operation specified by the instruction like addition and subtraction takes place.
ALU (Arithmetic Logic Unit) performs the computation.
Benefits of Pipelining:
1. Increased Instruction Throughput:
Pipelining allows multiple instructions to be in different stages simultaneously. As a result,
more instructions are executed per clock cycle, improving overall throughput.
2.Faster Execution:
Although individual instruction execution time remains the same, pipelining reduces the
overall program execution time. Instructions overlap, leading to better utilization of CPU
resources.
3. Higher Clock Frequencies:
Pipelined CPUs can operate at higher clock frequencies than non-pipelined ones. This boosts
overall performance.
Pipelined Architecture Non-Pipelined Architecture
Increased instruction throughput Instructions are executed sequentially
without overlapping stages
Faster ALU design No concurrency, resulting in lower
throughput
Overall performance improvement Longer execution time for programs
Higher clock frequencies

Diagram to illustrate pipelining

(b) Explain Daisy-Chaining priority and Parallel priority Interrupt with its hardware diagram.
[10 Marks]
Daisy-Chaining Priority Interrupts
The daisy-chaining method, the devices that can request an interrupt are connected in a serial
manner. The arrangement is governed by the priority of these devices. It works as illustrated
below
1. Configuration:
Devices are connected one after the other, forming a chain. The device with the highest
priority is placed first, followed by the second highest priority device, and so on. The lowest
priority device is placed at the end of the chain.

2. Interrupt Request Line:

All devices share a common interrupt request line that connects to the CPU. When no
interrupts are pending, this line remains in a HIGH state. If any device raises an interrupt, it
places the interrupt request line in a LOW state.

3. CPU Acknowledgment :
The CPU acknowledges the interrupt request from the line. It then enables the interrupt
acknowledge line in response.

4. Propagation through Devices:

The interrupt acknowledge signal is received at the Priority In , input of the first device.
If the device has not requested the interrupt and it passes this signal to the next device
through its Priority Out (PO) output (PI = 1 and PO = 1).
- However, if the device had requested the interrupt (PI = 1 and PO = 0), it consumes the
acknowledge signal and blocks its further use by placing a LOW signal at its PO output.

Diagram illustrating the daisy-chaining arrangement:

------------------- ------------------- -------------------

| Device 1 (Highest)| -> | Device 2 | -> | Device 3 |
------------------- ------------------- -------------------
| PI PO | | PI PO | | PI PO |
|1 0 | |1 1 | |1 1 |
------------------- ------------------- -------------------

Parallel Priority Interrupts

In a parallel priority system, each device has its own interrupt line.

1. Individual Interrupt Lines:

Each device has a dedicated interrupt line connecting it to the CPU. These lines operate in
parallel.

2.Priority Encoding:
Devices are assigned unique priority levels. The device with the highest priority has its
interrupt line activated first.

3. Interrupt Acknowledgment:
When an interrupt occurs, the CPU acknowledges the highest-priority interrupt line. The
corresponding device's service routine is executed.

4.Masking and Unmasking:

Devices can be masked (disabled) or unmasked (enabled) based on their priority.
The CPU can selectively enable or disable specific devices' interrupt lines.
Diagram illustrating parallel priority interrupts:

Device 1 (Highest)

CPU

Device 2

Device 3 (Lowest)

To conclude daisy-chaining prioritizes devices in a serial manner, while parallel priority

assigns individual interrupt lines based on priority levels. Both methods ensure efficient
handling of multiple interrupts in a system.

(c) Explain inter processor communication and synchronization in a shared multiprocessor

environment. [10 Marks]
1.Inter-Processor Communication :
The Inter Processor Communication refers to the exchange of data between different
processors within a multiprocessor system. It enables communication and coordination
among processors, allowing them to share information, collaborate, and perform tasks
collectively. It has many form some of which are the shared memory. The processors
communicate by accessing a common shared memory region. They read and write data
directly to this shared memory. Message Passing in message passing the processors
exchange messages through predefined communication channels. These channels can be
implemented using hardware or software mechanisms.

2. Synchronization:
Synchronization ensures that processes or threads execute in a coordinated manner,
adhering to specific order or timing constraints. It is Important because synchronization
prevents race conditions, deadlocks, and other concurrency related issues. It ensures
mutually exclusive access to shared writable data by the use of tools such locks and
semaphores ,Barriers ,Monitors and clock synchronisation. Locks and Semaphores allow
processes to acquire and release locks, ensuring exclusive access to critical sections. Barriers
synchronize processes at specific points, ensuring they all reach a common point before
proceeding. Monitors encapsulate shared data and provide synchronized access methods.
Clock Synchronization ensures that clocks across processors are consistent.

Inter Processor communication and synchronization are essential for efficient operation in
shared multiprocessor systems, ensuring coordinated communication and preventing
conflicts

(d) Illustrate the mapping process involved in transformation of data from main to Cache
memory. [10 Marks]
. Cache mapping refers to the technique used to bring data from the main memory into the cache
memory. It ensures that frequently accessed data resides in the cache, improving overall system
performance. The goal is to identify the cache line where a specific main memory block should be
placed .The main memory is divided into equal-sized partitions called main memory blocks then the
cache lines are divided into equal partitions called cache lines. The number of bytes or words in one
block is called the block size. The number of cache lines is determined by the ratio of cache size to
the block or line size.

The Mapping Technique

There are three common cache mapping techniques:

Direct Mapping: In this method, each main memory block is mapped to exactly one cache line. The
cache line number is determined by the block number modulo the total number of cache lines.

Fully Associative Mapping : Here, any main memory block can be placed in any cache line. The
entire cache is considered a single set.

Set Associative Mapping: The cache is divided into multiple sets, and each set contains a fixed
number of cache lines. A main memory block can be placed in any line within a specific set.

Direct Mapping

The physical address is divided into three parts:

Tag Bits: Identify the main memory block.

Cache Line Number: Represents the cache line where the content is present.

Byte Offset: Specifies the byte within the cache line.

Mapping Function:

The cache line number is calculated as K mod N, where:

K is the main memory block number.

N is the number of cache lines.

To illustrate

For example we have a direct mapped cache with 8 cache lines indexed from 0 to 7. Each cache line
holds a 32-byte block.

If a main memory block with block number 25 needs to be mapped:

25 mod 8 = 1, so it goes to cache line 1.

The tag bits help identify which main memory block is present in cache line 1.

Question 3

(a) With examples, Explain four segment CPU pipeline and Timing of instruction
pipeline. [10 Marks]

A CPU pipeline is a technique that overlaps the execution phases of different instructions to improve
throughput. In a four-segment instruction pipeline, the instruction cycle is divided into four
segments, each handling specific tasks:

1. Instruction Fetch (IF):

 Fetches the next instruction from memory. Utilizes a FIFO (First-In-First-Out) buffer to hold fetched
instructions.

2.Instruction Decode and Effective Address Calculation (ID/EA):

Decodes the fetched instruction. Calculates the effective address (if applicable).

3. Operand Fetch :

Retrieves operands (data) from memory.

4.Instruction Execution (IE):

Executes the operation specified by the instruction.

The four segments work in parallel, allowing multiple instructions to progress simultaneously.
However, pipeline efficiency can be affected by memory access conflicts or branch instructions.

The timing of an instruction pipeline depends on the duration of each segment. For example

Fetch: 10 ns

Decode: 6 ns

Execute: 8 ns

Write: 8 ns

Once the pipeline is full, the flow of instructions is determined by the longest stage duration (in this
case, 10 ns). The pipeline operates as follow

Fetch | Decode | Execute | Write

10 ns | 6 ns | 8 ns | 8 ns

--------------------------------

I7 | I6 | I5 | I4

: |: |: |:

I1 | out | |

1 to I7 represent instructions The pipeline processes instructions in parallel, improving overall

throughput.

d. Demonstrate the pipeline organisation for following example Ai*Bi+Ci for i =1,2,3,……
[10 Marks]
1. Instruction Fetch (IF):

Fetch the next instruction ( Ai) from memory. Store it in the FIFO buffer.

2. Instruction Decode and Effective Address Calculation . Decode the instruction ( Ai).

Calculate the effective address if needed.

3.Operand Fetch :

Fetch operands (Bi and Ci) from memory and store them in appropriate registers.
4. Instruction Execution : Perform the multiplication (Ai * Bi). Add the result to Ci.

Repeat the pipeline for subsequent instructions (i = 2, 3, ...).

A1*B1=AB+C1=AB+C

A2*B2=2((AB)+C)

A3+B3=3((AB)+C))

References:

Cache Mapping Techniques - GeeksforGeeks. https://www.geeksforgeeks.org/cache-mapping-

techniques/.

Priority Interrupts | (S/W Polling and Daisy Chaining). https://www.geeksforgeeks.org/priority-

interrupts-sw-polling-daisy-chaining/.

https://computersciencewiki.org/index.php/Registers_within_the_CPU

Virtual Memory in Operating System - GeeksforGeeks. https://www.geeksforgeeks.org/virtual-

memory-in-operating-system/.