ee a Memories and Asynchronous : Sequential Logic SYLLABUS Memories : Introduction, Random-Access Memory, Memory Decoding, Error Detection and correction Read-only memory, Programmable Logic Array, Programmable Array Logic, Sequential Programmable Devices. Asynchronous Sequential Logie = Introduction, Analysis Procedure, Circuits with Latches, Design procedure, Reduction of state and Flow Tables, Race-Free state Assignment, Hazards, Design Example. Concept of basic memory structure Study of RAM cell, organi 0, working of SRAM and DRAM Study of ROM cell, organization and types of ROM Introduction to programmable logic devices SEN EAE A Circuit implementation using PLA, PAL ond ROM < 3 & 3 2 $ 2 = 3 3 a 2 g 3 zc ¥ 8 3 £ < Analysis and design Y Concept of Cycles and Races V- Types of hazards and hazard free relations Y ” Design example of Asynchronous Sequential Circuits ‘ used to transfer it whenever. needed for processing. \ary information and 4d in digital system are ROM and RAM. RAM stores ‘Memory units store the bin It's a collection of cells. Memories that PLA, PAI ore vse! Information for later use. ROM, Lare the programmable logie devices. al crits contain « combinational circuit ond delay elements. These delay “Track loop Sinee, cock i absent, the design of circuit i a bit 4d 10 any other circuits. Asynchronous sequential tables and flow tables. The races caused in the Asynchronous sequenti tlements are connected to form a feedbac! complex but speed of operation is higher compare \d designed using transit yhent techniques. drevits can be analyzed an crevits are reduced by race free state assignt 7 ‘ a TENTS. LSTenTOS MN INEERING STUDENTS180 51 MEMORIES. Si introduction’ Qt. Discuss about types of semiconductor : momory? Ans: Semiconductor Memory A physical device used for encoding, storing and retrieving information is known as memory. Semiconductor memory is an electronic.deviee used to store data and also used as computer memory. It is referred as primary memory, as CPU usually accesses information from it (code and data). Read Only Memory (ROM) Read Only Memory is abbreviated as “ROM”. It is a memory device which stores the binary data ‘permanently irespective of the power status i.e, whether it is ON or OFF. It is non-volatile in nature. The figure below represents a ROM inputs ‘n’ outputs. Pen ROM Figure In POM, the binary data is written only once during the manufacturing process. In general, the data ‘once written cannot be erased. The various types of ROM’s include, PROM, EPROM, EEPROM and flash memory. 1. PROM Programmable ROM(PROM) is one time programmable non-volatile device. In this, the, programming is done by connecting the required fuses. . Initially the memory contains all logic O's. Wherever logic ‘1’ is required, that fuse is connected by passing high voltage pulse. PROM is less reliablé when compared to masked ROM. EPROM Erasable Programmable ROM (EPROM) is a memory device which can be programmed repeatedly by erasing the previous data, ‘The data is erased by exposing the entire chip {0 ultraviolet light for a specified time. Then the programming can be repeated. EEPROM Electrically Erasable Programmable ROM (EEPROM) is a memory device which can be programmed repeatedly by erasing the previous data using electrical charge. In EEPROM, specific bytes of the datg can be erased one at atime, Ly +s outputs “inputs (Gata) (eddeess) * 3. + DIGITAL ELECTRONICS [JNTU-HYDERABAD Flash ROM “This is also a memory device which is used ‘erase and program the selective portion of th, data Ithas an in-built single transistor circuit, which enables the block of memories to érase by consuming less power. 4 ° Random Access Memory (RAM) ‘The memory unit in which transfer of information tor from any random memory location uses same access time is known as Random Access Memory (RAM). tis, volatile in nature. _ | Based on the mode of operation, RAM ICs are classified as, 1. SRAM ‘The RAM in which stored information is valid only when power is available is known as static RAM, It uses flip-flops which require atleast 4 to 6 transistors (hold only 1 bit of data) in order to store data. It does not require refreshment of memory unit as data can be retained until the power is ON. Since it uses cache RAM, its speed of operation and power consumption is high. Ithas less packing density. NVRAM Non-volatile RAM (NVRAM) isa random access memory which is used as data memory to store the information when power is tumed OFF. Itcan function as both SRAM and EEPROM. Its contents can be retained ‘even if the switch is reloaded or power is turned OFF. It continuously monitors V., by using control circuitry. When V,,is less than the tolerant conditions, the circuitry switehes automatically to its internal power source and hence retains the NV-RAM contents, Therefore it requires battery backup. In NVRAM, byte level erasing ‘of memory alone is possible with low accessing speed. 2 DRAM The RAM in which binary information is stored as ¢lectrie charge on capacitors is known as dynamic RAM In this, capacitors are used as data storage elements which reduces the using of number of transistors to buil the cell. It fequires refreshment memory unit to restore the data. The packing density of DRAM is high, since, ituses main memory its speed of operation is moderate. ‘The power consumption of DRAM is high. 3. The semiconductor memory is widely used as main memory digital processing system which is classified as shown in figure. WARNING: Xerox/Photocopying of this book is a CRIMINAL act. Anyone found guilty is LIABLE to face LEGAL proceedings.Classification of Sericenducter Memery “whatare the primary types of memories in digital systems, and how do programmable fogic devices like ROM and CMOS FPGAS contribute to the design of digital systems? inst Memory Unit ‘The memory unit is an essential component ip igital systems for storing and retrieving binary Eeraation for processing. During data processing, ‘Efomation stored in the memory is transferred to Seale registers in the processing unit. Processed ‘is ae subsequently transferred back to memory for (poage. It serves a5 a middle man for the exchange of ‘pformation between input and output devices and the ces processing unit. ‘Types of Memories Digital systems consist of two primary memory types: RAM (Random-Access Memory) and ROM (Read-Only Memory). RAM is utilized for read and ‘srt operations to store fresh data. ROM is utilized for ‘cessing pre-existing information, which can only be rea, no altered. Programming Logic Devices (PLDs) Programming Logic Devices (PLDs) are electronic components that can be programmed to reform specific logic functions. They are commonly ‘ed in digital circuit design to implement complex logic perations. PLDs offer flexibility and reconfigurability- __ ROM is classified as a type of programmable ltgic device (PLD). PLDs are integrated circuits with ittemal logic gates connected through electronic paths like fuses. In their original state, all fuses are ‘tc Programming a PLD involves blowing specific eae along paths to create the desired logic function Pe utttion. Other examples of PLDs include PLA "erammable Logic Array), PAL (Programmable y Logi eld Gi Anup) “Bi and FPGA (Field-Programmable Gate is complex internal sroctare. Maltiple-iapt OF P® are symbolized by a single line ewer g te gee. # By rs fee, ae depicted (1). The graphical representation simplibes ete SPF depiction and is consistently wtilized in aay lope diagrams => HID Conventional Amy logic symbol symbol Figare (Ni Conventional and Array Lope Diagres f° ‘OR Gate (CMOS FPGAs CMOS FPGAs stands for Complemerszry Meta Oxide Semiconductor Field- Programmable Gate ASS ‘These FPGAs are configured by downloading 3 Sea of bits into the device, configuring tensmission E255 to establish internal connectivity for a specified loge function, whether combinational or sequential. Array Logic Diagrams In order to represent the internal logic diagram of 2 PLD concisely, a special gate symbology for exray logic is employed. For instance, the representation of mukiple- input OR gates involves single line exering the gate with input lines drawn perpendicular to it, connected through internal fuses. This graphical represectation is consistently ese in my le ras oe om 5.4.2Random Access Memory, Memory © Decoding 9 Q3. Briefly expl andom A Briefly explain Random Access Memory (RAM). An: RAM isan acronym for random 2ecess memory. ‘This type of memories can be used to perform both read! write operations. I is possible to access all the memory locations in the RAM at the same speed to perform both read and write operations. RAM is a volatile memory, hence stores data temporarily. It stores data related to program instructions and intermediate result of the program that are used temporarily. The data stored in the RAM can be read 2s many number of times as possible. A new data, which is written inthe any of the RAM locations, over-writes the existing data present in those locations. SPECTRUM ALLIN-ONE JOURNAL FOR ENGINEERING STUDENTS182 The Nook tiara 0 Control lines W address + Hines Read Write pio) 4 Memory units (2 wonts) mn! data output lines WW ddata input tines Figure A random access memory unit contains input Tines, output lines address selection lines and control ines as Shown in figure The *n? data input lines are used to write the binary information to be stored in the memory, when the control tine Write is active. ‘The ‘nr’ data output lines are used to read the information stored in the memory, when the control line Read is active. The." address lines are used to select a specific ‘word location (among the 2! words of memory) to which information has to be written or from where information has to be read. Salient Features of RAM 1. RAM is a volatile memory (i. stored information on power cut). ARAM basically performs two operations. They are, Read Operation: The process in which stored information is transferred outside the memory is called read operation. Write Operation: The process in which new information is stored into the memory is known as write operation. Based on the mode of operation, RAM ICs are classified as, Static RAM (SRAM): The RAM in which storéd information is valid only when power is available “is known as static RAM. It is usually made up of internal latches. Dynamic RAM (DRAM): The RAM in which binary information is stored as electric charge on capacitors is known as dynamic RAM ‘The discharge capacitor with time leads to the discharge of stored information. By recharging the capacitor the stored information can be retrieved. Explain memory READ and WRITE operation with neat timing diagram. Ans: , it looses the @ @ Gi) a4. ‘The two operations performed by RAM include, 1, Read : 2 Write WARNING: Xerox/Photocopying of this book is a CRIMINAL DIGITAL ELECTRONICS [JNTU. HYDERABAD) Hen The process in which stored information i transferred outaide the memory is KHown as ‘regg: ‘operation The steps involved in read operation are, ‘The binary address of the required data is applied onto the address lines. ‘The read signal is applicd. This will take the bit from the memory location and puts them on the output lines. Large integrated circuits consisting of several memory chips, are provided with two control signals one for chip selection using memory enable or chip select and other to determine the memory operation. | Ifmemory enable is low, chip is not selected and IW operations arc not performed. If memory enable is high, then read or write operations are performed based on the corresponding input control signal. The memory operations from these control inputs are illustrated in table below. Control inputs to memory chip Meme | Ri | Memory operation 0 x = 1 0 | Write to selected location 1 1 _ | Read from selected location 2. Write ‘The process'in which new information is stored into memory is known as ‘write? operation. The steps involved in write operation are, (The binary address of the required data is applied onto the address lines. (ii) The data bits to be stored are applied on the input + lines. (iii) The ‘write’ signal is applied. This stores the bits present on input lines to the specified address. ‘The two memory cycles that perform by the RAM are write and read cycles. These operations can be performed with the help of Memory Unit (MU) and Central Processing Unit (CPU). CPU is an external device which controls the memory operations. Since, memory unit does not have its own internal clock to control these operations. In order to select and read the word, memory uses access time and to complete the write operation it uses cycle time. CPU has to provide control signal to the memory for internal clocked synchronization with memory cycles. That means, when the CPU is communicating with a memory its access and cycle times will not exceed the time period of fixed CPU clock cycles. ‘act. Anyone found guilty is LIABLE to face LEGAL proceedings._g; Memories and Asynchronous Sequen: | Zaps an example in which the clock 1 su We |i gis2oms ["* SO MHz wn the CPU is communicating with memory, then, its access and cycle times | user eau c grad operations to terminate the storage ofthe selected word within 1 only 20 ns for one clock » ycle, sires two-and-balf or een cycle, Hence, it requires 183 frequency of CPU is 50 MHz. Then te time period of each elock prt 8 ate three clock cycles for each word ne waveforms : fF timing waveforms of memory operation a quis soi. Thus, the time period of mem af ats are the three clock cycles of 20 ns fe edon inate write operation, CPU provides unit, inorder to ; order to save data se kept stable so thatthe memory can enable and geadnsie ee bring comet The address inputs When! rian high level and read/write signals changes to low level, then the memory performs ae operation ‘memory enable and read/write signal switches to the high level, then the memory feos ead operation: Fig Feresenis write and read eycles along with ther timing waveform. <— 20nsec —> te shown in figures (a) and figure (b), in which clock frequency on cycle and each clock cycle are $0 ns and 20 ns respectively. post Clock TI =) = = Bee Address valid - Memory ensble YF Read/wtite — Initiate writing Latched ea © Clock TI RD st a Memory address ‘Address valid Memoryenable—/\ cued =Sttst=“‘t‘ié‘s;<‘t‘i<«< tite read Reade ee busca YT (b) Read Cyele Figures Timing Waveforms of Memory Cycle “The address inputs have to be held stable for short time ({e, at least 50 ns) after deactivation of control signals. Therefore, after termination of the third clock cycle, memory write cycle gets completed. Then, again CPU ‘2naccess memory and the next 7, eycle stars to operate for next selected word. = Explain the organization of RAM with diagrams. ns: vie gM is an acronym for Random access memory This type of memories can be used to perform both read ma eeation. tis possible'to access all the memory locations in the RAM at the same speed to perform both read 'wtite operations. RAM is a volatile memory, hence stores data temporarily. It stores data related to program Pinas and intermediate resalt ofthe program that are used temporarily. Figure (1) shows the block diagram "SPECTRUM @LLIN-ONE JOURNAL FOR ENGINEERING STUDENTS184 DIGITAL ELECTRONICS [JNTU-HYDERABAD) . Control lines ri "tt address | "> fines Read Write - ‘n' data input lines [> ‘n’ data output fines Memory units (2 words) Figure (1) Te gontains m-data input lines, data output fines, k-address fines and the control inputs (ie., Read and Write), The *n* data input lines cary the information into the memory which is to Be stored and the r-data outpuy lines carries out the stored information from the memory. The K-address lines selects the desired word from the bi acoads available in the memory. The two control inputs performs the-desired operation on the memory ithe ead input transfer the binary information into the memory and the write input transfer the binary information ow Sfmemory. The memory unit specifies the total available words and their bits per word. The address line selects one word mong the available words in the memory through a k-bit address. Address is an identification oumbs: given to each word. Wher a A-bit address is given to the address line a particular word is selected with the help of internal decoder from the memory. “The size of the memories are changed greatly i.e 10-bit address is needed for 1024 words, 32-bit address is needed for 2" words. Usually, the size of memory is represented in terms oF kilo(k) or Mega(M) or Giga(G) Bytes Where Kilo bytes stores 2" (Le., 64k = 2"), Mega stores 2" (i¢., 2M=2") words and the Giga stores 2! (ic. for 4G = 2 words). Figure (2) shows the content of 102416 memory where 1024 are with 16 bits per each word i, 2 bytes. the total words available in a memory Memory adress Bina Decimal Memory content “esata 0000000000 o 00h 0000000001 1 oth ‘000000010 2 o10n nine: 1024 [reorretoearaTos) | aro» sunninit6 1022 [oooor ror o0oT1 119} seen iin, 1023 f fete ToooTeoTeT aPPn igure (2) Each word is identified by their decimal address i.e., from 0 to 1023 and the corresponding binary addres» contains 10 bits. The binary address of first word is ten 0°s and the last word address contains ten 1"s (since, the 1025 decitnal address is equivalent to ten I's (1111111111) in binary). A particular word is chosen from the memory by their binary address. When the word undergoes read or write, then the memory perform the operation on all 16-bits like a single unit. While in 64k x 10 memory. It contains 16-bit address and 10 bits per word. That means the number of bits in address depends on the capacity of the memory (i.e, total number of words jt contains) and does not depends oF the number of bits in each word. The number of bits in the address can be known from the relation 2'2 m. Where, m — Total number of words k— Number of address bits required to fulfill the condition. ‘to face LEGAL proceedings. WARNING: XeroxiPhotocopying of this book is a CRIMINAL act. Anyone found guilty is LIee rentiate Static and fe a © raw the circuits of one eel ern explain its working pri inciple, nces between Static RAM ang Dynamic k e AM fhe RAM in which tored information is ,alid only when power is available is known as static RAM. in SRAM. flip flops are lysed as data storage [clements. are used as, elements, it does, not require refreshment of memary junit as the data can be retained until the power is ON. The speed of operation is high. It is used for cache RAM. It has less packing, density. |The power consumption of SRAM is high, It requires refreshment of memory unit to Testore the data, The speed of, 1 ©peration is moderate, It is used for main memory, It has hii igh packing density. + ‘The power consumption of DRAMis less, itis difficult to construct. | It is simple to construct. It does not require maintenance. Itrequires maintenance. 10. [It is expensive. SRAM Cell Figure (1) shows the internal circuit diagram of SRAM cell, Bit line i ‘It is economical. Bit line Latch circuit Word fine W : Figure (1: SRAM Cell “revit Description The circuit of SRAM cell. contains three ee ae aan two vertical as shown in figure (1). The 1 lines are’ parallel to each other and denoted by ; lines. The srg, This Vertical lines are known as bit SEotial ie is known a word line, ternal t0 these SPECTRUM ALL-IN-ONE JOURNAL Tne 185 ate two transi Witha latch ee anitors which forme iP Connections 'WONOT gates that, input of one NOT gate becomes ther NOT 7 Bate and vice versa ACKOSS the ci the transist ‘ors Femain in closed state. Hence the latch SMCUM Fetains or holds their states In order to, made high, the signal Similarly t fead the state 1 of transistors, “His » a8 4 result the transistors get closed causing {10 g0 high correspondingly i to go low. © read state 0, /is made low with i’ to go high. Morder to perform write operation i. changing the transistors to the suitable states can te done by iB appropriate values to bit lines i and i and tivating the wordline. In this way, the state gets stored in the latch circuit. DRAM Cell ‘The working of DRAM can be described by ing a single transistor DRAM which consists consideri of a single transistor and a single capacitor as shown in figure (2) - Word line Transistor Capacitor FS | Bit line ee Figure (2) A Single Transistor, Single Capacitor DRAM ‘The above circuit represents a single transistor DRAM or a single transistor, single capacitor DRAM. Here, the usage of capacitor is to store the charge ot state of the transistor. Apart from the transistor and a capacitor, the circuit consists of two perpendicular lines, with horizontal line representing a “word line” and a vertical line representing a “bit line’. The usage ofthese lines can be observed during the working of the cell. As the above circuit represents a memory cell, it’s functionality is to either store or release the prestored data. z In order to store the data in the capacitor, the bit line is fixed to a certain value which causes Some charge * to get stored on the capacitor. On the other hand, while retrieving the prestored value, the bit line is first charged and the word line is activated, which causes the charge to flow out from the capacitor through the word line. FOR ENGINEERING STUDENTS186 DIGITAL ELECTRONICS [JNTU-HYDERABAD| Working ‘To store the data in the cell, the ch: ON and applying an appropriate voltage to the of current (measured in pico amperes). At the same time, the capacito Teakage resistance. Thus, the data from the cell ean be read until the be read, its ther the capacit arge must he stored in the capacitor. This is done by turning the transisty tht line. When the transistor is turned OFF, it conducts small amoun y atarts discharging, duc to this current and the ischarge to some threshold value, apacitor di nsistor will be turned ON, Then, the sense or'a charge is more than the threshold value, ‘This will fully charge the capacitor corresponding to logic ae is Tess than the threshold value, then the bit line will be 1e of the capacitor corresponding to logic *0". snever they are read. If data is to be read ultaneously When the data sfored in the selected cell is 10 amplifier which is connected to the bit line, checks whet IF it is, then it will provide full voltage to the bit line. 1. If the sense amplifier finds that the eapacitor's chat pulled to ground level, This will completely remove the charn “The contents of a cell are automatically cleaved or refreshed wh from a selected row, then the contents ofall the cells present in this row will be read and refreshed G7. Explain memory decoding. Ans: Memory Decoding, The process of selecting the ¢ storage space is known as “memory “memory decodet™. Basically, a memory unit requires both the storage components as well as the decoding circuits to ensure its proper operation, The decoding operation ofa memory unit can be illustrated By ‘considering the internal construction ‘of RAM (Random Access Memory). . Internal Construction of RAM 5 x ; RAM is basically composed of m * storage cells associated witha decoding circuit (for locating individual words). ‘ sHere, ‘m” and Example _ The logical construction of a 16-bit RAM depicting the he input address from a large memory area or ‘orrect memory word given by th rms this action is known as a decoding”. The module or circuit which perfor | ¢>| f 1 Decoder Word 2 Memory —] EN enable t - t Word 3 t T +t Read/write OR gate Output Data ym of a4 x 4 (16-bit) RAM Figure: Logi WARNING: Xerox/Photocopying of this book is a CRIMINAL act, Anyone found guilty is LIABLE t0 LEGAL proceedsae cells. Since, A MeMOTY Of 4 wWorde ns Tes, therefore, a 2 * 4 decoder ig es eng operation of a code can be ie memery Enable opt fe) Reed two employed. abled or IreN aiathjecodet is enabled and depending on the inn 1g given, one ont of the four words ae selected If 28 oz all the decoder outputs turn out 10 be zero and seord is selected: When a word is selected, the read/write input xonmines the type of operation (read oF write) ta formed When a read operation is to be performed, the pits ofthe selected word are passed tothe oun foo Pe through OR gates. When a write operation is to be performed, the jus present atthe input lines is given to the Binary Ss(BC's) of selected Word. When no binary cells are they are disabled, such that their binary values remains unchanged. samples of Memory Decoding Schemes 1, Atwo-dimensional coincident decoding scheme is used in large memories for more efficient decoding. id ‘Address multiplexing is widely employed in D-RAM integrated circuits. How does the simplicity of DRAM cells with one transistor and capacitor allow. for higher memory density? Also, what is the role of address multiplexing in large-capacity DRAMs, using a 64K-word . memory as an example? Ans: Introduction to Memory Cells In Figure (1), the SRAM (Static Random-Access Memory) memory cell is illustrated with six transistors. However, for higher memory density, a different approach is taken with DRAM (Dynamic-Random- Accéss Memory) cells, which contain a single MOS transistor and a capacitor. Despite the advantage of higher density, DRAM cells require periodic refreshing ‘due to charge discharge from the capacitor over time. Select Bt | = Output Read/write 187 Input —>[BC}> output Readwrite ta (II: Memory Cell Advantages of DRAM over SRAM DRAMSs, with their simpler cell structure, achieve higher density, enabling four times more memory capacity on a chip compared to SRAMS. Additionally, the cost per bit of DRAM storage is significantly lower, making it a preferred technology for large memories in Personal digital computers. DRAMS also have lower Power requirements, contributing to cost savings. Address Decoding and Multiplexing Due to their large capacity. DRAMS use a two- dimensional array for address decoding, often with multiple arrays in larger memories. To reduce the number of pins in the IC package, designers employ address multiplexing. This involves using one set of address input pins for both row and column addresses. Ina two-dimensional array, the row address is applied fist, followed by the column address, using the same set of pins. : Mlustration with a 64K-Word Memory The text introduces a 64K-word memory configuration, organized as a two-dimensional array of 256 rows by 256 columns. This is illustrated in figure (2). Address multiplexing is achieved through two address strobes: Row Address Strobe (RAS) and Column Address Strobe (CAS). The 16-bit address is applied in two steps using RAS and CAS. Initially, both strobes are in the high state. The 8-bit row address is applied, and RAS is transitioned to 0, loading the row address into the row address register. RAS also enables the row decoder to select a specific row. After a settling, time, RAS returns to the high state. av Bit column “register 7m eas totter ft tl et ¥ oan oat \ddress Multiplexing for a 64K DRAM SPECTROM ALL-IN-ONE JOUR! NAL FOR ENGINEERING STUDENTS188 Next, the §-bit column address CAS is set to 0. This transfers the column address into the column register and enables the column decoder. With both parts of the address in their respective register the decoders select the specific cell, and a read or write ‘operation can be performed. CAS returns to the high state before initiating another memory operation. 51413 "Error Detection and Correction’ Q9, Explain about memory decoding error detection and correction. Ans: Error Detecting and Error Correcting Codes (The codes that are used to detect the presence of errors caused by noise during transmission through a channel are called error detecting codes. Example: Parity code, Gi) The codes that are ised to reconstruct the original, error-free data are called error correcting codes. Example: Hamming code. S_Acode is said to be error detecting code only if its minimum distance is two or more. Generally, the errors are detected and corrected: using a simple technique called Hamming code. ‘Hamming code use parity bits at certain portions in the code. U Aparity bit is an extra bit included with a binary message to gnake the number of one’s either odd oreven. +. Parity check codes are used for detecting errors. ‘The parity bits are classified into two types, namely, 1. Odd parity - 2. Even parity. 1. Odd Parity: If the number of 1’s in the data to be transmitted including the parity bit is an odd number, then the parity bit is referred to as odd parity. 2. Even Parity: If the number of 1’s in the data to be transmitted including the parity bit is an even number, then the parity bit is referred to as even. parity. ‘© The limitation of the parity code with respect to detection and correction of bit errors is that, “Parity bit-is guaranteed only to detect an odd number of bit errors ic., 1,3, 5...” Ifeven number of bits is flippéd, the parity bit appears to be correct even though the data is corrupted. DIGITAL ELECTRONICS [JNTU-HYDERABAD) G10, Explain In detall the usage of Hamming, codes for error detection and error correction. Ans: 4+ ° Hamming code is a technique used for detecting and correcting errors. 4 Thistechniqué not only detects the errors butalso, finds the exact bit that contains an error. «© When digital information is transmitted from one system to another system an error may occur due to the presence of noise. As a result the digital information may change from Oto I of vice-versa, 4 In Hamming code, in order to detect an error, a q parity bit is added to the information that has to be transmitted. a 4 This addition of parity bit makes the number of 1’s in information into cither even or odd. 4 4% At receiver, the parity bit present in received | information is verified by comparing it with the | transmitted information. i “If it does not relate with the transmitted one an” error takes place, then erroneous bit is corrected _ by replacing 1 by 0 or vice-versa depending on _ the error. “The Hamming code can be generated by _ following the steps. 1. The number of parity bits used by the Hamming code depends on the nuniber of data bits. 2. Its expressed as, V2X+P+1 Where, P—Number of parity bits X—Number of data bit Q11. With the help of the generalized form of the Hamming code, explain how the number of parity bits required to transmit a given number of data bits? | An: Hamming code comprises of certain parity bits. The number of parity bits used by the Hamming code depends on the number of data bits. For example, the number of parity bits used by the Hamming code for the given number of data bits are given below, : 2PontP+1 Where, P —Number of parity bits and n— Number of data bits. For example, In a 4-bit Excess-3 message, the Hamming code uses 3 parity bits (7 2° 4+ 3 +1 satisfies) for detecting and correcting the single bit errors. Therefore, the total code consists of 7-bits.parity bits can be placed in powers of; ‘Therefore, the general 7-bit Hammis, sabi Exeess-3 MESSAZES i828 follows, 12,4, imming code for Di, Dis Dy Pu Dy P,P, Where, D - Data bits and P ~Parity bits, Now, for the 4-bit Excess-3 message 1 ot 0 or Oare esigned to the parity bits to forma 7-bit Hamming eo copa The parity bit P, checks the bits located at a jtions 1, 3, 5 and 7. So, P, should be ass j ass Fat bit locations 1, 3, S and 7 must have Giese even of ity. Similarly, P, checks for locations 2, 3, 6 and Tand P, checks for 4, 5, 6 and 7. Thus, a 7-bit Hamming code is generated for a {bit Excess-3 message by assigning values to the three represents parity bits. Example: The given data bits are 0101. The Hamming code can be generated by following the steps. Step 1: The data has 4 information bits. Then the are, Step 2: In this step, a bit location table is Three parity bits aré required and to! number of parity bits can be obtained by using the expression, 2P2X+P+1 Where, P —Number of parity bits _X — Number of information bits, Let, P=3 Then, 2 =P =Band X+pt1=4434+1=8 2P > X+ P+ 1 condition is satisfied. tal code bits X+P=443=7 constructed from the given code. Parity Bit-p, ° ; ‘can be obtained by checking the bit locations +3, S and 7. There is only one binary | in this roup, % So, P, should be replaced by * Parity Bit-P, © Similarly P, checks bit locations 2, 3, 6 and 7. There are two Is in this group for even parity. * So, parity bit P, should be replaced by ‘0° for even parity Parity Bit-P, © P,checks bit locations 4, 5, 6and 7. There is only one 1 in this group. ‘ ” So, parity bit P, should be replaced by I for even Parity. ‘The obtained parity bts are then replaced in the bit location table. Therefore, the generated hamming code is 101101 Qiz. Given the 8 bit data word 10111001, generate the 12 bit composite word for the Hamming code that corrects and detects single errors. Step Ans: Inorder to generate the 12-bit composite word for the Hamming code we add four parity bits tot he 8-bit data word. The 4 parity bits are located at position’s 20, 2!, 2? and 2? from left as shown below. P,[P,]D,]P.{P.]P.]D, |] Pe|Po| Dio | Pur | Drs 1/ foal f:tololo P, has to be selected such that bits 1, 3, 5, 8,7, 9, 11 have even parity ic, P; 110110 must have been parity. So, P, P, has to be selected in such a way that its 2,3, 6.7, 10, 11 have even parity ie, , 11100 must have even parity. So, Py= 1+ "p, has to be selected such that bits 4,5, 6, 7, 12 have even parity i¢., 011 must have even parity. So, P= 1 P, has to be selected such that bits 8, 9, 10, 11, 2 have even parity . So, P, Word is 111101101001 71101101001)DIGITAL ELECTRONICS [JNTU-HYDERABAD) fe bit error occurred in each code amming code. 1110111 “Julylug-24, (R18), QA(a) M9] 190 G13. Decode the following message assuming word when it is transmitted through a no 0011011, 1101101. Ans: ‘The message received is, 1110111001 10111101101 . z . ‘Since cach Hamming code is of 7 bits length. The received message can be segregated into four 7-bit words (received), They are, 1. 110111 2. OOLTOIT 3. 1101101 The single error in each of these codes can be obtained as shown below: that at mosta singl isy channel using 7-bit H LL Error in 111011 Bit designation > pe) PLP] Ps | | Pe | error code His TTabalalalele Received message 1 1 1 0 1 1 1 Cheek for P, (1,3,5,7) 1 1 1 1 0 Check for P, (2,3,6,7) 1 1 : 1 1 . Check for P,' (4,5,6,7) 1 1 1 0 1 surred at bit position *4". The error code is 160 that means error has occ the actual code is 1111111. Hence, complement the bit at position “4”. So, 2 Errorin 0011011 Bit Designation Dy, Dy Pa Ds, saPays, Bun Biron cogs Bit location, 7 eg ee el 1 18-101 100 ott 10,9 Received message 0.00 2b Oat 1 Check for P, (1,3,5,7) 0:7 1 0 1 ° [Check for P, (2,3,6,7) oo 0.0 1 QO. Os 1 al ° Check for P, (4,5,6,7) ‘The error is at bit position ‘2’. Hence, So the actual message is 100101 1001100111001 100011001. 3. Error in 1101101 the correct message code is 0011001. Bit designation | D, | D, | D, | P.-| Ps | Ps | Pi | Error code _ [Bitlocation 7 silaeaig| se |e [et th | afo ] sr | 100 | oir | oto | oo Received message pfafofrfupofa Check for P, (1,3,5,7) | 1 0 1 ‘ya ° Check for P, (2,3,6,7) | 1 | 1 Eto a Check for P,(4,5,6:7) | 1 | 1] tft ' 0 The error code is 010 that means érror has occurred at bit position 2. Hence, the correct message code is 1101111. , G14. A 12-bit Hamming code word containing 8 bits of data and 4 7 Parity bits is read from memory. What is the original 8-bit word if the 12-bit read cut is 1010 1001 1101. Ans: - : AugJSep-21, (R18), 24) M7] The given 12-bit Hamming code is, 1010 1001 1101. Generation of 12-bit Hamming code involves 8 data bits and 4 parity bits. The bit pattern for the given data is, [eT To Te To. Po. [oT To To Lrtetifofifofofifil: From the table, the data bits ., 8-bit word is, 11001101. WARNING: Xerox!Photocopying of this book isLogic Generate the 13-bit co bit compos detects doubl errors, rn sand 13 analy located at positions 1, 2, 4, and 8. These positions are shy " are used for the original data. ote ea Patty. Parity bits at positions 1, 2, 4, and 8 ensure an even ans Consist of positions 1, 3, 5, 7,9, 11, and 13; positions 2, 3,6, 7 10. Fi Positions 8, 9, 10, and 11. : , lata word: O1011011, : : 1-5: Ue ven the B-bit data word O10T107 hat corrects single errors _ pa 13-bit Hamming code, the extra AE of 2. Bis 35.6 7.9, 1,11, 12, re gilt pe additional bits’ values are det sunt positions 4, 5, 6,7, 12, and 13; ‘Given Original 8. p 1: Assign Positions pl! swPi"pi P2 DI Pa D2 D3 D4 P8 Ds. D6 D7 Ds PI3 more Ore OL et ot os culate Parity Bits PI, P2, P4, P8: Party bi step? C2 P2, D4, P8: Parity bits PI, P2, PA, and PB are calculated by performing XOR Sens on specifi dt is a allows PL=XOR G, 5.7.9, 1)=XOR(0,1,1, 1,1) <0 p2=XOR (3, 6, 7, 10, 11) = XOR (0,0, 1,0, 1 p4=XOR (5,6, 7, 12)=XOR (1, 0,1, 1) =1 pS =XOR (®, 10, 11, 12)=XOR (1, 0,1, 1)=1 sep3: Insert Parity Bits into the Data Word : pl P2 DI P4 D2 D3 D4 Ps Ds-D6 D7 D8 PIB prP2 0 P4 1 0 1 PRT oO 1 1. PB oO. 0 1 10 1 ton 1. PB P13 is a pari alculated over specific positions in the code word. Calculation of P13 PI3=XOR of bits 1, 2, 3,4, 5, 6,7, 8,9, 10, 11, 12 P13 =XOR(I, 2, 3, 4, 5, 6, 7, 8,9, 10, 11, 12) : P13 = XOR(O, 0, 0, 1, 1,0, 1, 1, 1,0,1, 1) $0, P13 i8 calculated to be 1 based on the XOR of the specified bits. Therefore, the final 13-bit code word is "0001101 110111," containing both the original data bits and the calculated parity bits. é Gig. Obtain the 15-bit Hamming code word for the 11-bit data word 11001001010. ‘Ans: Ina 15-bit Hamming code, the extra bits are usally located at positions 1,2, 4, and 8. These positions are smliples of 2. Bits 3, 5, 6, 7,9, 10, 11, 12,13, 14 and 15 are used for the original data, “The additional bits' values are determined by parity. Party bits at positions 1, 2, 4, and 8 ensure an even ‘umber of 1s in specific groups. The groups consist of positions 3, 5, 7, 9, 11,13 and 1; positions 3,6, 7, 10, 11, Ii and 15; positions 5, 6, 7, 12, 13, 14 and 15; and positions 9, 10, 11, 12, 13, 14 and 15. Given Original 11-bit data word: 11001001010 = Step 1: Assign Positions Pl P2 Di P4 D2 D3 D4 P8 DS D6 D7 D8 D9 DIO Dil PLP) 1 Pa. dO OPE 0 OL OD. 8. Step2: Calculate Parity Bits PL, P2, P4,P8: Party bits PI, P2; PA, and PB are calculated by performing XOR operations on specific data bits as follo . P1=XOR (3, 5, 7,9 11, 13, 15) XOR (1, 1,0, 1,0,0,0)=1 P2=XOR (3, 6,7, 10, 11, 14, 15 XOR (I, 0, 0, 0,0, 1,0)=0 P4=XOR (5, 6, 7, 12,.13, 14 15) XOR(1,0,01,0,1,0)=1 P8= KOR (, 10,11; 12,13, 14,15) = XOR(L, 0,05 10 D1 Step3: Insert Parity Bits into the Data Word Pi p2 D1P4 D2 D3 D4 PS DS D6 D7 DS D9 DIO Dil Meee a eeege de Dee 0: REIT, Oeste OH EAD Te eR ey 9 TBO oO Ot PG : ‘Therefore, the final 15-bit code word is "10111001 1001010, containing both the original data bits and the : | FOR ENG! NEERING STUDENTS ‘SPECTRUM ALL-IN-ONE JOURNAL192 i 5ALa" Read Only Memory Q17. Whatis ROM? Explain tho operation of It. Ans: ROM . Read only memory is abbreviated as “ROM h stores the binary data It is a memory device W permanently irespective ofthe power status jc, whether it is ON of OFF ic, it is non-volatile Figure (1) represents a ROM with ‘nm outputs. inputs ‘a RAE kot Figure (1): ROM TnROM, the bit too during the process of manufact written can’t be erased. Operation of ROM outputs (ata) ry data is written only once that g. The data once Here, the transistor is connected to ground by a switch. Hence, whenever the switch is closed, the value of the transistors switches to zero élse it remains ‘1’. Ii order to read the status of a cell, the word line is turned high. Asa result, ifthe switch of the transistor is closed, 4 value ‘0" flows out of the circuit. Similarly, ifthe switch remains open, the transistor supplies a value ‘1”. There is no write operation possible with ROMs, since data is added to it only while it is being manufactured, “ Q48. Explain the organization of ROM with relevant diagram. Ans: ROM For answer refer Unit-5, QU7, Topic: ROM. ‘The Basic ROM consists of a decoder of size n* 2 and a memory array as shown in figure (2). Decoder Memory array 2* nx2s n input words < m bits lines m output lines Figure (2) DIGITAL ELECTRONICS [JNTU-HYDERABAD inorder toi 1A oryanization, consider an example of W208 ROM, A 3278 ROM cantains input lines for address and # output fines. Ht prevvides 32. words, where each word represents # data bits, The internal logic of a 927% ROM is as shore in figure (4, CECH 5 +32 decoder 24 { 4, 29 30 eleE _— uw Figure (3) This contains a 5*32 decoder. It decodes 5 inputs into 32 different outputs, where each output provides the address of memory. These 32 outputs are given to the each eight OR Gates. So, each output of decoder acts as an input to each of the eight OR gates. Therefore 322 gives 256 internal connections which are programmable. When the two lines are connected intemally then it acts as a switch that may be closed or opened. This meeting point of two lines is known as crosspoint. Truth table signifies the.binary information stored in a ROM. The truth table illustrated in figure (4) specifies the binary information stored by the ROM of size 32*8. It stores 32 words and size of each word is 8-bit. Each of the 32 word location can be accessed by 5 inputs J,, I,, and /,. The words stored in all 32 address locations are accessed by the outputs 4, 10 4, Inputs Outputs LUE A AAA AAA, Ay ©0000 10110110 00001 00011101 90010 11000101 Ooo1r tor 1roo010 1100 00001001 PDOs Neg he 9 20 (061 0 11110 ©1001010 LVittu oorroo yy Figure (4) WARNING: Xerox/Photocopying ofthis book is a CRIMINAL acl ‘Anyone found guilty is LIABLE to LEGAL proceedinas.A648 ROM is a combinational The 6 inputs are called address inputs j CUPUS and an erable input as shown in figure (1) ‘sre called as data outputs ie. AD,-AD_ 4 ACA, 648 Enable input Rom [—>AD,-An, Figure (1: 64. 8 Rom The enable input (EN ) is an active low pin. When an active low Signal is applied to this pin, the 64 « & ROM store the truth table of 6-inputs, outputs combinational logic function. 312 = 8 ROM is implemented by using cight “64-8 ROM" and a 3-4 decoder to enable one of the eight “648 ROM” chips ic., an 3%8 decoder selects one of the eight ROM chips depending on the three input bits. Thus, toully there are 9 input bits which provide the required 512 x 8 ROM configuration as shown in figure (2), A, 0 - a 1 a— near} 38 3 i 4 EN. ia oer es Scie ew : ; i it "64 x BROM" Chips : IM by using Eight “64 sare BE tion of 512 x BRO ; - Figure mle using @ ROM tha accepts 22 Bt number and generates an - a ‘ el corm mumber equal to the square of he gi utput binary i! i f input would be the Ans: . 3-bit mimber as input and square of “To design a combinational circuit which Stan abc dean8f a5 he abs. pt Sutput, consider x, y and z as the 3-bits of the RNAL FOR ENGINEERING STUDENTS SPECTROM ALLAN-ONE J00194 Table The logic of the combinational circuit is given in the table. The output is square of the input number. It can be observed from the table that minterms for the output expression obtained are as follows, . Em(6, 7) Em4, 5,7) Em(3, 5) Em(2, 6) 7 Em(1, 3, 5,7) The block diagram of the combinational cireuit using 8 x 4 ROM is as shown in figure (1). ‘ a x 8x4 b, y ROM “ z p—d |O—e f Figure (1): Block Diagram The circuit implementation using ROM is illustrated in figure (2). 0 -————__——_+——_ 1 x 7 3:8 0093 i. ¥™) Decoder 4 2 5 1 6 7 Y ab le. diie..'f Figure (2) : Combinational Circuit Using ROM WARNING: XeroxiPhotocopying of this book DIGITAL ELECTRONICS [JNTU-HYDERABAD] Q21. Explain different types of ROM in detail, Ans: ROM For answer refer Unit-5, Q17, Topic: ROM. Advantages 4 Itis more reliable than RAM © Itis non-volatile The data stored in it is permanent and cannot be changed % Itis cheaper than RAM Iisa static memory so it does not need to refresh each time, ‘% _ Ithelps to boot the operating system. Disadvantages It is very slow Itis capable of only reading the data ‘It is unable to store large amounts of data % Ifchanges are required in data it is not possible. The different types of ROM are, 1. Programmable Read Only Memory (PROM) 2. Erasable Programmable Read Only Memory (EPROM) 3. Electrically Erasable Programmable Read Only ‘Memory (EEPROM) 4. Flash Memories 1. PROM + Programmable ROM(PROM) is one time programmable non-volatile device. In this, the programming is done by connecting the required fuses. ‘Initially the memory contains all logic 0's. Wherever logic ‘1° is required, that fuse is More costlier than other ROM chips. 4 Flash Memory This is also a memory device which is used to erase and progfam the selective portion of the dato. @ — Ithasan in-built single transistor circuit, which ‘enables the block of memories to erase by ‘consuming !ess power. Advantages Flash devices have greater density 4b High capacity and a lower cost pe Bit 4. Uses only single power supply voltage: & Consumes less power. Disddvantages They are prone to damage physically % ‘They are slow since they rewrite every block of da ‘ es a) jh the flash memory 19 DEO" 8 card, casing itto be used with a variety ‘of applications.” ese are used 16 patel ee . They are now sealable with several memory S17°S like 8, 32, and 64 Mbyte: a" 7 4 wort Hada : isk drives. But it's storage capacity is less than Giga byte. However, io renee an insensitivet0 vibration. These are developed * they have high speed ‘of operation, ©aos DIGITAL ELECTRONICS [JNT! Q22. Differentiate RAM and ROM. YDERABAD) Ans: The differences between RAM and ROM are mentioned below: ROM RAM 1, ]Read Only Memory (ROM) is a combinational] 1. [Random Access Memory (RAM) contains circuit [sequential circuits elements called flip flops. 2. [ROM allows data to be written only once and read] 2. [RAM allows data to be read and written any number Jany number of times. of items. 3. | The general block diagram of ROM is, 3. | The general block diagram of RAM is, ; Address bus, ———— n inputs —o |» m outputs — Data bus Read ROM K=> Write > 4 Chip select 4. |ROM isa non-volatile memory. 4, |RAM is volatile memory. S. ROM is used for permanent storage. 5. RAM is used for temporary storage. 6. ]ROM is less expensive than RAM. 6. |RAM is much expensive than ROM. 7. ]ROM is a low-speed memory. 7. |RAM isa high speed memory. 8. | The size of ROM is larger than RAM. 8. | The size of RAM is smaller than ROM. 9. |ROM stores critical programs for example the] 9. |RAM stores operating system application programs [program that boots the computer. and data or currently running processes. 10. | Types of ROM 10. | Types of RAM \) Programmable Read-Only Memory (PROM). (i) Dynamic Random Access Memory (DRAM). Gi) Erasable Programmable Read Only Memory (ii) Synchronous Dynamic Random Access (EPROM). Memory (SDRAM). |Gii) Electrically Erasable Programmable Read (iii) Static Random Access Memory (SRAM). ‘Only Memory (EEPROM). . (Gv) Flash memory. ‘ “Table Q23. Given a 32 x 8 ROM chip with an enable input, show the external connection necessary to construct a 128 x 8 Rom with four chips and a decoder. Ans: 32% 8ROMisacombinational circuit with S-inputs, 8-outputs and an enable input as shown in figure (1). The S-inputs are called as address inputs ie, 4,- A, and 8-outputs are called as data outputs i.e., AD,- AD, AA, 328 [=p a0,-An, KOM Enable input EN, Figure (1) The Enable Input (EN ) is an active low pin. When an active low signal is applied to this pin, the 32 «8 ROM will store a truth table of 5-inputs, 8-outputs combinational logic function. To implement 128 x 8 ROM, we need four “32 « 8 ROM” and a 2 = 4 decoder which has to enable one of the four “32 x 8 ROM” chips ie., we can use an 2 4 decoder, which will select one of the four ROM chips depending on the two input bits. Thus, totally we have 7-input bits which will provide the required 128 x 8 ROM ‘configuration as shown in figure (2). WARNING: Xerox/Photocopying of this book is a CRIMINAL act. Anyone found guilty is LIABLE to face LEGAL proceedings.197 ROM CHIP L Figare (2) a the operation of 16-bit ROM array with neat diagram. ans 1A 16-bit ROM is constnucted (bedel Paper, atta) |Apty 23. 1, 21010) ED "using an array of memory cells, each capable of storing a single bit cont «ot Te ea elas in ows and cohimns, forming the ROM array. The adress tines, also known gether ae icular coh pif row inthe array, hie the deta lines, sso own the columm sos. elect * an aaa pee ROM array is as shown in figure. To choose any one of the 16 bits we ges (Ay a Av Ay) red Te lowe ro A ooh Mecoder DL er ile the higher order two bits (A, A.) are decoded through the decoder DH eat the 4 column sen: ic t and con sense alii. The dade mati # mde y comes ‘one diode with a switch non : in address a 3 Column Data output Figure FIGINEERING STUDENTS GONE JOURNAL FOR FI198 Memory Ga The memory cells in a 16-bit ROM are implemented using electronic switches, typically transistors, which can be cither in an “on” state (representing a logical high or 1") or an “off” state (representing a logical low or “0”), These cells are fanged in a grid-like fashion to form the ROM array. Address Decoding To access a specific memory location in the ROM array, the desired address is provided to the address lines. The address decoding, ry within the ROM uses Combinations of logic gates to decode the address and determine the corresponding row and column to be accessed. Control Signals The operation ofa 16-bit ROM is controlled by various signals, including the chip enable (CE) signal, ‘the output enable (OE): ‘signal, and the write enable (WE) signal. These signals help regulate the data flow and enable the ROM to perform its intended functions, Working Principle of a 16-bit ROM. The working principle ofa 16-bit ROM involves the retrieval of stored data based on the Provided address. When an address is input to the ROM, the address lines are activated, causing the corrésponding row address to. be selected. Simultaneously, the column address Jines enable the desired column within the selected row. Read Operafion During’ a read operation, the selected memory cell in the ROM array activates its data line, allowing the stored information to be accessed. The output data is, then available on the data lines for further processing by the system. This read operation is essential for retrieving relevant instructions and data stored in the ROM array. Working of 16-bit ROM Array For illustration the diode D,, is connected in betweén column 1 and row 2. The output is enabled through applying logic 1 at the CS input that is chi select. Programming a ROM implies to selectively open and close the switches in seric’s along with the diodes. For illustration, if the switch of diode D,, is into closed position and if the address input is 0110, the row 2 is activated linking this to the column 1. As,well the sense amplifier of column 1 is enabled that provides logic 1 output if the chip is selected means C: as logic 1 is stored at the address 0110. Conversely, if the switch of diode D,, is open, logic 0 is stored on the address 0110. WARNING: Xerox/Photocopying of this book is a CRIMINAL act. Anyone found guilty is LIABLE to fa DIGITAL ELECTRONICS {INTU-HYDERABAD 5.1.5 Programmable Logic “Array, é Programmable Array Logic 3 025. Write a brief note on PLDs, Ans: Programmable Logic Devices (PLDs) A programmable logic device is an int logic circuit which is user. ‘Programmable. It is ‘basically composed of programmable gates arranged in the form of AND array and OR array. Based on the arrangement of programmable ates, PLDs are divided into three types. They are, () Programmable Read Only Memory (PROM) Gi) Programmable Logic Array (PLA) (ii) Programmable Array Logic (PAL), () Programmable Read Only Memory (PROM) PROM is a combinational PLD with fixed AND array and programmable OR array as shown in figure (1). The fixed AND array is constructed as a decoder whereas the programmable OR array Provides the implementation of boolean functions in the form of sum-of-minterms. a Fixed AND A | Programmatic A. onere >| ray (Decoder OR array Figure (1) Gi) Programmable Logic Array (PLA) A programmable logic array is a combination of Programmable AND array and programmable OR array as shown in figure (2). In this device, the product terms of AND array can be shared with OR array for SOP (Sum of Products) implementation. Iapus—+ Progammable | rrogrammabie Ay o a ‘AND anay ORarray Figure (2) (iii) Programmable Array Logic (PAL) A programmable Array Logic (PAL) formed by combining a programmable AND array and a fixed OR array as shown in figure (3). The Programming of AND array provides the product terms for boolean functions. 1. It shows ts—p-| Programmable A | fined A 5 oupins Tipo emer aes . igure (3) LEGAL proceedings.199 4 logic diagra Draw the gram of progra G26 gic array. Explain its operation eee ns Ane" ene Programmable Logic Array (PLA) jg LA) is a ‘ device, contain ational logic ¢ + containing a two fe senna “AND" and progranmable “OR ay ! re PLA does not perform complete decoding A ji ag and does not produce all the minterms. The sane’ eooder iS replaced by an array of AND gates, ‘The block diagram of PLA with ‘m* inputs and gcouuts i 8 shown in figure (1), combi ec | 1 I 2%" |programmable| }. [Programmable gt y ft BL] aNDamy OR array =z fe Wy k word lines n output lines , Figure (1): PLA . The PLAS are programmed’in order to achieve sm of product logic expressions. In PLA, an array of AND" gates produce the oduct terms of the applied inputs, and an aray of “OR” eesproduce the “sum of products” logical expressions Ferexample, a PO+PR OR+PR PO+PR ' PR Then, the corresponding PLA programming table isshown in table. Product | Inputs Outputs Term [pg r[f ff % PQ, [Lr ef ed@ ar |- 0 1f/0 1% © peer ora ee 4 rr fo - ofo tt @ Table: PLA Programmable Table structure of PLA fort! ‘The intern ial gate level ‘ons is as shown ing SPECTRUM €l Figure (2k: Internal Structure of PLA ___ The inputs, P, Qand R are applied to the buffer inverter combination to produce its complement. The respective values are given as input to the AND gates to produce the “product terms”. ‘The outputs from the ‘AND array are given as inputs to the ‘OR’ array. Thus, the output produced by the ‘OR’ gates is the “sum of product” terms. Applications 1. These are used to implement control over a data path. 2. Theregularstructure of PLA’s with programmable AND and OR array’s isused in complex systems involving many variables. 3. PLA’s are used to perform programmable logic sequencing and finite state machine operations with the registers at input and output 27. Explain detail about PAL and PLA. Ans: __ Novibee7 (R15), 010 Programmable Logic Array For answer refer Unit-5, Q26. Programmable Array Logit ‘The block diagram of programmable array logic i as shown in figure (1)- z Fixed OR amy "Figure (1k: Block Diagram ‘The Programmable Array Logic (PAL) is a programmable logic device which is constructed using programmable AND arty and fixed OR array. AND rey is provided to give product terms which are fopically summed using OR array. PAL- is easier for the programming Purpose. Inputs dm Ourputs agg ‘and four outputs Boolean expressi = ENTS LL-IN-ONE JOURN FOR ENG! EERING STUDI eSintr ex semen Seca 2p Eo Sm Pe dura seth Sanus Sx duwe pg ABE Ane PAL eur. tn emg. OR spas at ay SR DIGHTAL ELECTRONICS NINTUNYDERARAD) cack term mmet be Fagurs (2) : PAL mich Faur inguts, Frur Gutzuts and 2 Tiree Wide AND-O5 Sroctore Figure (2) represents 24 pus $ come open (say FF Fy md Fy. Each inp coe PAL is sed ta desien dizi 2 2 Wis widely used ie VLSI cious and yseems. G22. Compare PAL and PLA with respect to various performance features. 4.5. Cand D) ant ker The caper de of pFRal guesand a Grad OR exe, AND goss using fires Som caqpet seco ace also known as progmmmmad LO PALS imation. : ‘The compasison of PROM, PLA and PAL is mentioned below. f PLA PAL ] 1. | PLA is a programmable device which is used to] PAL is 2 programmable Gove WHR BETO implement combinational logic circuits. 2. | The design consists of programmable AND array and programmable OR. array. 3, | It is more expensive. 4, | PLA is difficult to program. 5. | In PLA, AND arrays are programmed to obtain desired minterms. 6, | It is more flexible to program AND array. 7. | It is used for implementing any Boolean functions, implement combinational logic circuits, ‘The design consists of programmable AND and fixed OR aay. Itis inexpensive. PAL is simple to progam. In PAL, AND arrays are programmed to obtain desired minterms. Itis less flexible to program. It is used for implementing any Boolean fictions. 8. | AND array are programmed to get desired minterms. | AND arrays are programmed to get desired WARNING: Xerox/Photacopying of this boak is a CRIMI minterms. ‘act, Anyone found guilty s LIABLE to face LEGAL preceediogs.memories and Asynchronous ge,

You might also like

• Unit V- PLD

  

  No ratings yet

  Unit V- PLD

  46 pages
• Memory Organization

  

  No ratings yet

  Memory Organization

  10 pages
• Semiconductor Memory Gate Notes 41

  

  No ratings yet

  Semiconductor Memory Gate Notes 41

  4 pages
• Unit-2

  

  No ratings yet

  Unit-2

  31 pages
• UNIT5 - PLDS, CPLDs & FPGA

  

  No ratings yet

  UNIT5 - PLDS, CPLDs & FPGA

  203 pages
• DF GTU Study Material Presentations Unit-5

  

  No ratings yet

  DF GTU Study Material Presentations Unit-5

  44 pages
• Basic Memory Operation: Static RAM, SRAM: An SRAM Is More Expensive and Less Dense Than DRAM. It Uses A

  

  No ratings yet

  Basic Memory Operation: Static RAM, SRAM: An SRAM Is More Expensive and Less Dense Than DRAM. It Uses A

  3 pages
• Memory and Programmable Logic

  

  No ratings yet

  Memory and Programmable Logic

  17 pages
• ECCE3206_chapter7

  

  No ratings yet

  ECCE3206_chapter7

  20 pages
• Lecture 09 - Ch No. 05 Internal Memory

  

  No ratings yet

  Lecture 09 - Ch No. 05 Internal Memory

  20 pages
• UNIT V Notes 1

  

  No ratings yet

  UNIT V Notes 1

  7 pages
• UNIT V Notes

  

  No ratings yet

  UNIT V Notes

  22 pages
• memory.pptx DLD ppt

  

  No ratings yet

  memory.pptx DLD ppt

  18 pages
• Feee 1st year

  

  No ratings yet

  Feee 1st year

  23 pages
• CF Pics 3

  

  No ratings yet

  CF Pics 3

  121 pages
• ece201ppt

  

  No ratings yet

  ece201ppt

  30 pages
• Memory Morgan Is at Ion

  

  No ratings yet

  Memory Morgan Is at Ion

  2 pages
• DLD Week-14

  

  No ratings yet

  DLD Week-14

  24 pages
• Components of Computer

  

  No ratings yet

  Components of Computer

  69 pages
• What Is Computer Memory and Storage

  

  No ratings yet

  What Is Computer Memory and Storage

  4 pages
• DE

  

  No ratings yet

  DE

  27 pages
• Microprocessor Lecture 5 Full

  

  No ratings yet

  Microprocessor Lecture 5 Full

  25 pages
• Microcontroller and Embeddes System - ARM Program Optimization 3

  

  No ratings yet

  Microcontroller and Embeddes System - ARM Program Optimization 3

  42 pages
• DSD Presentation

  

  No ratings yet

  DSD Presentation

  14 pages
• Materials for Memory and Display System

  

  No ratings yet

  Materials for Memory and Display System

  56 pages
• Unit 3 Notes

  

  No ratings yet

  Unit 3 Notes

  14 pages
• term paper

  

  No ratings yet

  term paper

  6 pages
• memory organization UNIT 3 - TOPIC 3.1 (PART 1)

  

  No ratings yet

  memory organization UNIT 3 - TOPIC 3.1 (PART 1)

  9 pages
• Different Types of Memories

  

  No ratings yet

  Different Types of Memories

  11 pages
• Chapter3 2 1

  

  No ratings yet

  Chapter3 2 1

  49 pages
• CC-1-UNIT-4

  

  No ratings yet

  CC-1-UNIT-4

  9 pages
• Semiconductor Memory and Programmable Logic Device

  

  No ratings yet

  Semiconductor Memory and Programmable Logic Device

  12 pages
• 14-Cache Memories-05-Sep-2018 - Reference Material I - Types of Main Memories

  

  No ratings yet

  14-Cache Memories-05-Sep-2018 - Reference Material I - Types of Main Memories

  18 pages
• Chapter 5 Memory and Memory Interface

  

  No ratings yet

  Chapter 5 Memory and Memory Interface

  56 pages
• Memory Devices

  

  No ratings yet

  Memory Devices

  29 pages
• Internal Memory (RAM + ROM) 2

  

  No ratings yet

  Internal Memory (RAM + ROM) 2

  32 pages
• Unit-4 Memory Ppts

  

  No ratings yet

  Unit-4 Memory Ppts

  31 pages
• CSE 1, IT 1 - DPSD

  

  No ratings yet

  CSE 1, IT 1 - DPSD

  50 pages
• Semiconductor and Programmable Logic Device

  

  No ratings yet

  Semiconductor and Programmable Logic Device

  35 pages
• Computer Lab 111

  

  No ratings yet

  Computer Lab 111

  21 pages
• Typesofmemory Updated

  

  No ratings yet

  Typesofmemory Updated

  8 pages
• 05 Internal Memory

  

  No ratings yet

  05 Internal Memory

  73 pages
• Memory

  

  No ratings yet

  Memory

  5 pages
• William Stallings Computer Organization and Architecture 8th Edition Internal Memory

  

  No ratings yet

  William Stallings Computer Organization and Architecture 8th Edition Internal Memory

  22 pages
• Chapter 22

  

  No ratings yet

  Chapter 22

  23 pages
• Unit V - Memories - V

  

  No ratings yet

  Unit V - Memories - V

  82 pages
• DPSD_UNIT_5

  

  No ratings yet

  DPSD_UNIT_5

  106 pages
• CO Unit 5

  

  No ratings yet

  CO Unit 5

  24 pages
• Ram & Rom: Random Access Memory

  

  No ratings yet

  Ram & Rom: Random Access Memory

  3 pages
• Computer Systems: Hardware (Book No. 1 Chapter 2)

  

  No ratings yet

  Computer Systems: Hardware (Book No. 1 Chapter 2)

  111 pages
• Computer Memory PDF

  

  No ratings yet

  Computer Memory PDF

  13 pages
• Memories - I: COMP541

  

  No ratings yet

  Memories - I: COMP541

  45 pages
• Unit 4-Memory System

  

  No ratings yet

  Unit 4-Memory System

  19 pages
• Primary Storage

  

  No ratings yet

  Primary Storage

  13 pages
• UNIT - 5_Part 1_Memory (1)

  

  No ratings yet

  UNIT - 5_Part 1_Memory (1)

  26 pages
• Chapter 7 Memory and Programmable Logic

  

  No ratings yet

  Chapter 7 Memory and Programmable Logic

  43 pages
• Unit - 3 Interfacing Semiconductor Memories and IO Devices

  

  No ratings yet

  Unit - 3 Interfacing Semiconductor Memories and IO Devices

  34 pages
• Data Structures

  

  No ratings yet

  Data Structures

  42 pages
• Data strucures

  

  No ratings yet

  Data strucures

  44 pages
• data structures

  

  No ratings yet

  data structures

  24 pages
• Data Structures

  

  No ratings yet

  Data Structures

  66 pages