Chapter 4: Digital Logic Design

:Combinational Logic

0 / 65
 Combinational Circuits
• Output is function of input only
i.e. no feedback

Combinational
n inputs • • m outputs
• change (after a delay) ••
• output mayCircuits
When input changes,


1 / 65
 Combinational Circuits
• Analysis
• Given a circuit, find out its function
• Function may be expressed as:
A
B
C
A
F1
?
B

• Boolean function
C
A
B

• Truth table
A
C

B
F2
?
C

• Design
• Given a desired function, determine its circuit
• Function may be expressed as:
• Boolean function
• Truth table

2 / 65
Analysis Procedure
• Boolean Expression Approach

A
B
F1
C T2=ABC
A T1=A+B+C
B T3=AB'C'+A'BC'+A'B'C
C
A
B F’2=(A’+B’)(A’+C’)(B’+C’)

A
F2
C
F2=AB+AC+BC
B
C
F1=AB'C'+A'BC'+A'B'C+ABC
F2=AB+AC+BC 3 / 65
Analysis Procedure
• Truth Table Approach
A B C F1 F2
A =0 0 0 0 0 0
0 0
B =0
F1
C =0
A =0 0
B =0 0
C =0
1
A =0 0
B =0

A =0 0 0
F2
C =0

B =0 0
C =0

4 / 65
Analysis Procedure
• Truth Table Approach
A B C F1 F2
A =0 0 0 0 0 0
0 1
B =0 0 0 1 1 0
F1
C =1
A =0 1
B =0 1
C =1
1
A =0 0
B =0

A =0 0 0
F2
C =1

B =0 0
C =1

5 / 65
Analysis Procedure
• Truth Table Approach
A B C F1 F2
A =0 0 0 0 0 0
0 1
B =1 0 0 1 1 0
F1
C =0
0 1 0 1 0
A =0 1
B =1 1
C =0
1
A =0 0
B =1

A =0 0 0
F2
C =0

B =1 0
C =0

6 / 65
Analysis Procedure
• Truth Table Approach
A B C F1 F2
A =0 0 0 0 0 0
0 0
B =1 0 0 1 1 0
F1
C =1
A =0
0 1 0 1 0
1
B =1 0 0 1 1 0 1
C =1
0
A =0 0
B =1

A =0 0 1
F2
C =1

B =1 1
C =1

7 / 65
Analysis Procedure
• Truth Table Approach
A B C F1 F2
A =1 0 0 0 0 0
0 1
B =0 0 0 1 1 0
F1
C =0
A =1
0 1 0 1 0
1 1
B =0 0 1 1 0 1
C =0 1 0 0 1 0
1
A =1 0
B =0

A =1 0 0
F2
C =0

B =0 0
C =0

8 / 65
Analysis Procedure
• Truth Table Approach
A B C F1 F2
A =1 0 0 0 0 0
0 0
B =0 0 0 1 1 0
F1
C =1
A =1
0 1 0 1 0
1 0
B =0 0 1 1 0 1
C =1 1 0 0 1 0
0
A =1 0 0 1
B =0
1 0 1

A =1 1 1
F2
C =1

B =0 0
C =1

9 / 65
Analysis Procedure
• Truth Table Approach
A B C F1 F2
A =1 0 0 0 0 0
0 0
B =1 0 0 1 1 0
F1
C =0
A =1
0 1 0 1 0
1 0
B =1 0 1 1 0 1
C =0 1 0 0 1 0
0
A =1 1
B =1
1 0 1 0 1
1 1 0 0 1
A =1 0 1
F2
C =0

B =1 0
C =0

10 / 65
Analysis Procedure
• Truth Table Approach
A B C F1 F2
A =1 0 0 0 0 0
1 1
B =1 0 0 1 1 0
F1
C =1
A =1
0 1 0 1 0
1 0
B =1 0 1 1 0 1
C =1 1 0 0 1 0
0
A =1 1
B =1
1 0 1 0 1
1 1 0 0 1
A =1 1 1
C =1
F2 1 1 1 1 1
B =1 1
C =1 B B
0 1 0 1 0 0 1 0
A 1 0 1 0 A 0 1 1 1
C C

F1=AB'C'+A'BC'+A'B'C+ABC F2=AB+AC+BC
11 / 65
 Design Procedure
• Given a problem statement:
• Determine the number of inputs and outputs
• Derive the truth table
• Simplify the Boolean expression for each output
• Produce the required circuit
Example:
Design a circuit to convert a “BCD” code to “Excess 3” code

➢ 4-bits ➢ 4-bits
➢ 0-9 values
? ➢ Value+3

12 / 65
Design Procedure
• BCD-to-Excess 3 Converter
C C
A B C D w x y z
1 1 1
0 0 0 0 0 0 1 1
1 1 1 1
0 0 0 1 0 1 0 0 B B
x x x x x x x x
0 0 1 0 0 1 0 1 A 1 1 x x
A 1 x x
0 0 1 1 0 1 1 0
D D
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0 w = A+BC+BD x = B’C+B’D+BC’D’
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0 C C
1 0 0 0 1 0 1 1 1 1 1 1
1 0 0 1 1 1 0 0 1 1 1 1
1 0 1 0 x x x x x x x x
B x x x x
B
A 1 x x
A 1 x x
1 0 1 1 x x x x
1 1 0 0 x x x x D D
1 1 0 1 x x x x
1 1 1 0 x x x x y = C’D’+CD z = D’
1 1 1 1 x x x x 13 / 65
Design Procedure
• BCD-to-Excess 3 Converter
A B C D w x y z A
0 0 0 0 0 0 1 1 w
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1 x
B
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1 C y
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
D z
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x w = A + B(C+D) y = (C+D)’ + CD
1 1 1 0 x x x x x = B’(C+D) + B(C+D)’ z = D’
1 1 1 1 x x x x 14 / 65
Seven-Segment Decoder a
w x y z abcdefg
w a
0 0 0 0 1111110 b
0 0 0 1 0110000 x c f b
? d g
0 0 1 0 1101101 y e
0 0 1 1 1111001 z f
0 1 0 0 0110011
g e c
0 1 0 1 1011011 BCD code
0 1 1 0 1011111
0 1 1 1 1110000 y d
1 0 0 0 1111111 1 1 1
1 0 0 1 1111011 1 1 1
1 0 1 0 xxxxxxx x x x x
x
1 0 1 1 xxxxxxx w 1 1 x x
1 1 0 0 xxxxxxx z
1 1 0 1 xxxxxxx
1 1 1 0 xxxxxxx a = w + y + xz + b=...
x’z’ c=...
1 1 1 1 xxxxxxx
d=... 15 / 65
Binary Adder
• Half Adder x S
• Adds 1-bit plus 1-bit HA
• Produces Sum and Carry
y C

x
+ y
───
x y C S C S
0 0 0 0
0 1 0 1 x
1 0 0 1
S
1 1 1 0
y C

16 / 65
Binary Adder
• Full Adder x S
• Adds 1-bit plus 1-bit plus 1-bit y FA
• Produces Sum and Carry z C

x
+ y
y + z
x y z C S ───
0 1 0 1
0 0 0 0 0 C S
0 0 1 0 1 x 1 0 1 0
z
0 1 0 0 1
S = xy'z'+x'yz'+x'y'z+xyz = x  y  z
0 1 1 1 0
y
1 0 0 0 1
0 0 1 0
1 0 1 1 0
x 0 1 1 1
1 1 0 1 0
z
1 1 1 1 1 C = xy + xz + yz
17 / 65
Binary Adder
• Full Adder
S = xy'z'+x'yz'+x'y'z+xyz = x  y  z
x C = xy + xz + yz
y
z
x
y x
x z y
x S z S
y
z
x
x
x y
y y y
z x
x z C
y z
y
z x C
z
z
y
z

18 / 65
Binary Adder
• Full Adder

x S
y HA HA

z C

x
S

y
C
z

19 / 65
Binaryx xAdder
xx yyyy
3 2 1 0 3 2 1 0
c 3 c2 c1 .
+ x3 x 2 x 1 x 0
Carry + y3 y2 y1 y0
Cy Binary Adder C0 Propagate ────────
Addition Cy S3 S2 S1 S0
S3S2S1S0

x3 x2 x1 x0
y3 y2 y1 y0
0

FA FA FA FA

C4 C3 C2 C1
S3 S2 S1 S0 20 / 65
Binary Adder
• Carry Propagate Adder

x7 x6 x5 x4 x3 x2 x1 x0
y7 y6 y5 y4 y3 y2 y1 y0

A3 A2 A1 A0 B3 B2 B1 B0 A3 A2 A1 A0 B3 B2 B1 B0

Cy CPA C0 Cy CPA C0 0

S3 S2 S1 S0 S3 S2 S1 S0

S7 S6 S5 S4 S3 S2 S1 S0

21 / 65
Binary Subtractor
• Use 2’s complement with binary adder
• x – y = x + (-y) = x + y’ + 1

x3 x2 x1 x0 y3 y2 y1 y0

A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci 1
S3 S2 S1 S0

F3 F2 F1 F0

22 / 65
Binary Adder/Subtractor
• M: Control Signal (Mode)
• M=0 ➔ F = x + y
• M=1 ➔ F = x – y x3 x2 x1 x0 y3 y2 y1 y0 M

A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci
S3 S2 S1 S0

F3 F2 F1 F0

23 / 65
Decoders
• Extract “Information” from the code
Only one
• Binary Decoder
• Example: 2-bit Binary Number
lamp will
turn on

0 1 2 3

0 1
x1 0
Binary
x0 0 Decoder 0
0

24 / 65
Decoders
• 2-to-4 Line Decoder
Y3

y3 Y2

Decoder
I1 Binary
y2
y1 Y1
I0 y0
Y0

I1 I0 Y3 Y2 Y1 Y0
I1
0 0 0 0 0 1 I0
0 1 0 0 1 0
Y3 = I1 I 0 Y2 = I1 I 0
1 0 0 1 0 0
1 1 1 0 0 0 Y1 = I1 I 0 Y0 = I1 I 0
25 / 65
Decoders
• 3-to-8 Line Decoder
Y7 = I 2 I1 I 0
Y6 = I 2 I1 I 0
Y7 Y5 = I 2 I1 I 0
Y6
Y4 = I 2 I1 I 0
Y5
Decoder
Binary

I2 Y4 Y3 = I 2 I1 I 0
I1 Y3
I0 Y2 = I 2 I1 I 0
Y2
Y1 Y1 = I 2 I1 I 0
Y0 Y0 = I 2 I1 I 0

I2
I1
I0
26 / 65
Decoders
• “Enable” Control
Y3

Y3

Decoder
I1 Y2
Binary Y2
I0 Y1
E Y1
Y0
Y0
E I1 I0 Y3 Y2 Y1 Y0
0 x x 0 0 0 0
I1
1 0 0 0 0 0 1 I0
E
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
27 / 65
Decoders
• Expansion I2 I1 I0
I2 I1 I0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0 Y3 Y7

Decoder
I0

Binary
0 1 0 0 0 0 0 0 1 0 0 Y2 Y6
I1 Y1
0 1 1 0 0 0 0 1 0 0 0 Y5
E Y0
1 0 0 0 0 0 1 0 0 0 0 Y4
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0 Y3 Y3

Decoder
I0

Binary
1 1 1 1 0 0 0 0 0 0 0 Y2 Y2
I1
Y1 Y1
E
Y0 Y0

28 / 65
 Implementation Using Decoders
• Each output is a minterm
• All minterms are produced Binary
Decoder
• Sum the required minterms
Y7
Example: Full Adder Y6
S(x, y, z) = ∑(1, 2, 4, 7) Y5
x I2 Y4
C(x, y, z) = ∑(3, 5, 6, 7)
y I1 Y3
z I0 Y2
Y1
Y0

S C 29 / 65
Encoders
• Put “Information” into code
• Binary Encoder
Only one
• Example: 4-to-2 Binary Encoder
switch
should be
activated
at a time

1
x1
x3 x2 x1 y1 y0
x2 y1 0 0 0 0 0
2 Binary
Encoder 0 0 1 0 1
y0 0 1 0 1 0
x3
3 1 0 0 1 1

31 / 65
Encoders
• Octal-to-Binary Encoder (8-to-3)
I7
I7 I6 I5 I4 I3 I2 I1 I0 Y2 Y1 Y0 I6
I5

Encoder
0 0 0 0 0 0 0 1 0 0 0 Y2

Binary
0 0 0 0 0 0 1 0 0 0 1 I4 Y1
0 0 0 0 0 1 0 0 0 1 0 I3 Y0
0 0 0 0 1 0 0 0 0 1 1 I2
0 0 0 1 0 0 0 0 1 0 0 I1
0 0 1 0 0 0 0 0 1 0 1 I0
0 1 0 0 0 0 0 0 1 1 0 I7
1 0 0 0 0 0 0 0 1 1 1 I6 Y2
I5
Y2 = I 7 + I 6 + I 5 + I 4 I4
I3 Y1
Y1 = I 7 + I 6 + I 3 + I 2 I2
I1
Y0 = I 7 + I 5 + I 3 + I1 I0 Y0
32 / 65
Multiplexers

S1 S0 Y I0
0 0 I0 I1
MUX Y
0 1 I1 I2
1 0 I2 I3
S1 S0
1 1 I3
33 / 65
Multiplexers
• 2-to-1 MUX
I0
I0 Y
MUX Y
I1 I1
• 4-to-1 MUX S
S
I0

I1
Y
I0 I2

I1 I3
MUX Y
I2
I3
S1 S0
S1 S0 34 / 65
Implementation Using Multiplexers
• Example
F(x, y) = ∑(0, 1, 3)

x y F I0
1
0 0 1 1 I1
MUX Y F
0 1 1 0 I2
1 0 0 1 I3
S1 S0
1 1 1
x y

35 / 65
Implementation Using Multiplexers
• Example
F(x, y, z) = ∑(1, 2, 6, 7)

0 I0
x y z F 1 I1
0 0 0 0 1 I2
0 0 1 1 0 I3
Y F
0 1 0 1 0 I4 MUX
0 1 1 0 0 I5
1 I6
1 0 0 0
1 I7
1 0 1 0 S2 S1 S0
1 1 0 1
1 1 1 1 x y z
36 / 65
Implementation Using Multiplexers
• Example
F(x, y, z) = ∑(1, 2, 6, 7)

x y z F
0 0 0 0 z I0
F=z z I1 F
0 0 1 1
MUX Y
0 1 0 1 0 I2
F=z 1 I3
0 1 1 0 S1 S0
1 0 0 0
F=0 x y
1 0 1 0
1 1 0 1
F=1
1 1 1 1
37 / 65
Implementation Using Multiplexers
• Example
F(A, B, C, D) = ∑(1, 3, 4, 11, 12, 13, 14, 15)

A B C D F
0 0 0 0 0
F=D
D I0
0 0 0 1 1
0 0 1 0 0
D I1
F=D
0 0 1 1 1 D I2
0 1 0 0 1
F=D 0 I3
0 1 0 1 0
0 MUX Y F
0 1 1 0 0
F=0 I4
0 1 1 1 0 D
1 0 0 0 0
I5
1 0 0 1 0 F=0 1 I6
1 0 1 0 0
1 0 1 1 1
F=D 1 I7
1 1 0 0 1 S2 S1 S0
F=1
1 1 0 1 1
1 1 1 0 1 F=1
1 1 1 1 1 A B C
38 / 65
Multiplexer Expansion
• 8-to-1 MUX using Dual 4-to-1 MUX

I0 I0
I1 I1
MUX Y
I2 I2
I3 I3
S1 S0 I0
MUX Y Y
I1
I0 S
I4
I5 I1
MUX Y
I6 I2
I7 I3
S1 S0

1 0 0
S2 S1 S0 39 / 65
DeMultiplexers
Y3
Y2
I DeMUX Y
1
S S Y0
1 0

Y3

Y2 S1 S0 Y3 Y2 Y1 Y0
I
Y1 0 0 0 0 0 I
Y0
0 1 0 0 I 0
1 0 0 I 0 0
S1 1 1 I 0 0 0
S0
40 / 65