12.water Level Monitoring System
12.water Level Monitoring System
1. INTRODUCTION
OBJECTIVE OF THE PROJECT
BLOCK DIAGRAM
2. HARDWARE DESCRIPTION
MICROCONTROLLER
Led PANNEL
POWER SUPPLY
PRINTED CIRCUIT BOARD
4. SOFTWARE DESCRIPTION
KEIL COMPILER
PROGRAM
INTRODUCTION
An embedded system is a combination of software and hardware to perform a dedicated
task.
An embedded system can be defined as a computing device that does a specific focused
job. Appliances such as the air-conditioner, VCD player, DVD player, printer, fax
machine, mobile phone etc. are examples of embedded systems. Each of these appliances
will have a processor and special hardware to meet the specific requirement of the
application along with the embedded software that is executed by the processor for
meeting that specific requirement. The embedded software is also called “firm ware”.
The desktop/laptop computer is a general purpose computer. You can use it for a variety
of applications such as playing games, word processing, accounting, software
development and so on. In contrast, the software in the embedded systems is always fixed
listed below:
Some of the main devices used in embedded products are Microprocessors and
Microcontrollers.
In contrast, a microcontroller not only accepts the data as inputs but also
manipulates it, interfaces the data with various devices, controls the data and thus
All these tasks are possible with the microcontroller because the microcontroller has
a CPU in addition to a fixed amount of RAM, ROM, I/O ports and timer all on a
single chip. This fixed amount of RAM, ROM and number of I/O ports in
microcontroller makes them ideal for many applications where cost and space are
critical.
ABSTRACT
In many houses water is stored in overhead tanks. Water is pumped from bores or wells
to the tanks by using an AC motor. The motor takes some time to fill the tank. An
operator has to pay attention to the tank to switch off the motor to avoid overflow of
water.
AUTOMATION:
If a system is developed for automation of pump for filling the tank, no operator is
required for supervising the system. Automatic water level controllers are already
available in the market. But these controllers are not suitable for this application, as the
electrodes are having direct contact with the content. Due to this the electrodes get filled
up with rust. To over come all these things we implemented a unique system for this
application by using magnetic sensors. The sensors are fixed at specified locations on the
container/tank. A floating magnet floats on the liquid and triggers the magnetic sensors
one-by-one based on the liquid level. Microcontroller monitors the liquid level and the
level displayed on LCD. If the maximum level is reached, the microcontroller switches
off the motor. If the liquid reaches the lower level, the controller drives the driver circuit
and operates the motor automatically. Siren driver circuit would be activated by
thermistor sensor.
As magnetic sensors / reed switches are used, the problem of oxidization of level probes
is completely eliminated. This is advanced, trouble-free, fit and forget system for
industrial applications.
This project uses regulated 5V, 500mA power supply. 7805 three terminal voltage
regulator is used for voltage regulation. Bridge type full wave rectifier is used to rectify
Level 1
Level 2
Magnetic Relay Driver
sensors for Level 3
level Motor
8
measurement
9
S
5
1
Crystal
Reset
circuit
MICROCONTROLLERS:
The Intel 8051 is a Harvard architecture, single chip microcontroller (µC) which
was developed by Intel in 1980 for use in embedded systems. It was popular in the 1980s
and early 1990s, but today it has largely been superseded by a vast range of enhanced
devices with 8051-compatible processor cores that are manufactured by more than 20
independent manufacturers including Atmel, Infineon Technologies and Maxim
Integrated Products.
8051 is an 8-bit processor, meaning that the CPU can work on only 8 bits of data
at a time. Data larger than 8 bits has to be broken into 8-bit pieces to be processed by the
CPU. 8051 is available in different memory types such as UV-EPROM, Flash and NV-
RAM.
The Intel 8051 is Harvard architecture, single chip microcontroller (µC) which
was developed by Intel in 1980 for use in embedded systems. It was popular in the 1980s
and early 1990s, but today it has largely been superseded by a vast range of enhanced
devices with 8051-compatible processor cores that are manufactured by more than 20
independent manufacturers including Atmel, Infineon Technologies and Maxim
Integrated Products.
8051 is an 8-bit processor, meaning that the CPU can work on only 8 bits of data
at a time. Data larger than 8 bits has to be broken into 8-bit pieces to be processed by the
CPU. 8051 is available in different memory types such as UV-EPROM, Flash and NV-
RAM.
The features, pin description of the microcontroller and the software tools used
are discussed in the following sections.
FEATURES OF AT89s52:
Description:
Vcc Pin 40 provides supply voltage to the chip. The voltage source is +5V.
Port 0
Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink
eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high
impedance inputs. Port 0 can also be configured to be the multiplexed low-order
address/data bus during accesses to external program and data memory. In this mode, P0
has internal pull-ups.
Port 0 also receives the code bytes during Flash programming and outputs the code bytes
during Program verification. External pull-ups are required during program verification.
Port 1
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers
can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high
by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are
externally being pulled low will source current (IIL) because of the internal pull-ups. In
addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input
(P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in
the following table.
Port 1 also receives the low-order address bytes during Flash programming and
verification.
Port 2
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers
can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high
by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are
externally being pulled low will source current (IIL) because of the internal pull-ups.
Port 2 emits the high-order address byte during fetches from external program memory
and during accesses to external data memory that uses 16-bit addresses (MOVX @
DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During
accesses to external data memory that uses 8-bit addresses (MOVX @ RI), Port 2 emits
the contents of the P2 Special Function Register. The port also receives the high-order
address bits and some control signals during Flash programming and verification.
Port 3
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers
can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high
by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are
externally being pulled low will source current (IIL) because of the pull-ups. Port 3
receives some control signals for Flash programming and verification.
Port 3 also serves the functions of various special features of the AT89S52, as shown in
the following table.
RST
Reset input. A high on this pin for two machine cycles while the oscillator is running
resets the device. This pin drives high for 98 oscillator periods after the Watchdog times
out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In
the default state of bit DISRTO, the RESET HIGH out feature is enabled.
ALE/PROG
Address Latch Enable (ALE) is an output pulse for latching the low byte of the address
during accesses to external memory. This pin is also the program pulse input (PROG)
during Flash programming.
In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and
may be used for external timing or clocking purposes. Note, however, that one ALE pulse
is skipped during each access to external data memory.
If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the
bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is
weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in
external execution mode.
PSEN
Program Store Enable (PSEN) is the read strobe to external program memory. When the
AT89S52 is executing code from external program memory, PSEN is activated twice
each machine cycle, except that two PSEN activations are skipped during each access to
external data memory.
EA/VPP
EA must be strapped to GND in order to enable the device to fetch code from external
program memory locations starting at 0000H up to FFFFH. Note, however, that if lock
bit 1 is programmed, EA will be internally latched on reset.
EA should be strapped to VCC for internal program executions. This pin also receives the
12-volt programming enable voltage (VPP) during Flash programming.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Oscillator Connections
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that
can be configured for use as an on-chip oscillator. Either a quartz crystal or ceramic
resonator may be used. To drive the device from an external clock source, XTAL2 should
be left unconnected while XTAL1 is driven. There are no requirements on the duty cycle
of the external clock signal, since the input to the internal clocking circuitry is through a
divide-by-two flip-flop, but minimum and maximum voltage high and low time
specifications must be observed.
Special Function Registers
A map of the on-chip memory area called the Special Function Register (SFR) space is
shown in the following table.
It should be noted that not all of the addresses are occupied and unoccupied addresses
may not be implemented on the chip. Read accesses to these addresses will in general
return random data, and write accesses will have an indeterminate effect.
User software should not write 1s to these unlisted locations, since they may be used in
future products to invoke new features. In that case, the reset or inactive values of the
new bits will always be 0.
Timer 2 Registers:
Control and status bits are contained in registers T2CON and T2MOD for Timer 2. The
register pair (RCAP2H, RCAP2L) is the Capture/Reload register for Timer 2 in 16-bit
capture mode or 16-bit auto-reload mode.
Interrupt Registers:
The individual interrupt enable bits are in the IE register. Two priorities can be set for
each of the six interrupt sources in the IP register.
Dual Data Pointer Registers:
To facilitate accessing both internal and external data memory, two banks of 16-bit Data
Pointer Registers are provided: DP0 at SFR address locations 82H-83H and DP1 at 84H
and 85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1. The user
should ALWAYS initialize the DPS bit to the appropriate value before accessing the
respective Data Pointer Register.
The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to
“1” during power up. It can be set and rest under software control and is not affected by
reset.
Memory Organization
MCS-51 devices have a separate address space for Program and Data Memory. Up to
64K bytes each of external Program and Data Memory can be addressed.
Program Memory
If the EA pin is connected to GND, all program fetches are directed to external memory.
On the AT89S52, if EA is connected to VCC, program fetches to addresses 0000H
through 1FFFH are directed to internal memory and fetches to addresses 2000H through
FFFFH are to external memory.
Data Memory
The AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a
parallel address space to the Special Function Registers. This means that the upper 128
bytes have the same addresses as the SFR space but are physically separate from SFR
space.
When an instruction accesses an internal location above address 7FH, the address mode
used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM
or the SFR space. Instructions which use direct addressing access the SFR space.
For example, the following direct addressing instruction accesses the SFR at location
0A0H (which is P2).
Instructions that use indirect addressing access the upper 128 bytes of RAM. For
example, the following indirect addressing instruction, where R0 contains 0A0H,
accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).
Note that stack operations are examples of indirect addressing, so the upper 128 bytes of
data RAM are available as stack space.
When the WDT is enabled, it will increment every machine cycle while the oscillator is
running. The WDT timeout period is dependent on the external clock frequency. There is
no way to disable the WDT except through reset (either hardware reset or WDT overflow
reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST pin.
Using the WDT
To enable the WDT, a user must write 01EH and 0E1H in sequence to the
WDTRST register (SFR location 0A6H). When the WDT is enabled, the user needs to
service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit
counter overflows when it reaches 16383 (3FFFH), and this will reset the device. When
the WDT is enabled, it will increment every machine cycle while the oscillator is
running. This means the user must reset the WDT at least every 16383 machine cycles.
To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is
a write-only register. The WDT counter cannot be read or written. When WDT
overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse
duration is 98xTOSC, where TOSC = 1/FOSC. To make the best use of the WDT, it
should be serviced in those sections of code that will periodically be executed within the
time required to prevent a WDT reset.
In Power-down mode the oscillator stops, which means the WDT also stops. While in
Power down mode, the user does not need to service the WDT. There are two methods of
exiting Power-down mode: by a hardware reset or via a level-activated external interrupt
which is enabled prior to entering Power-down mode. When Power-down is exited with
hardware reset, servicing the WDT should occur as it normally does whenever the
AT89S52 is reset. Exiting Power-down with an interrupt is significantly different.
The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is
brought high, the interrupt is serviced. To prevent the WDT from resetting the device
while the interrupt pin is held low, the WDT is not started until the interrupt is pulled
high. It is suggested that the WDT be reset during the interrupt service for the interrupt
used to exit Power-down mode.
To ensure that the WDT does not overflow within a few states of exiting Power-down, it
is best to reset the WDT just before entering Power-down mode.
Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine
whether the WDT continues to count if enabled. The WDT keeps counting during IDLE
(WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89S52
while in IDLE mode, the user should always set up a timer that will periodically exit
IDLE, service the WDT, and reenter IDLE mode. With WDIDLE bit enabled, the WDT
will stop to count in IDLE mode and resumes the count upon exit from IDLE.
UART
The Atmel 80C51 Microcontrollers implement three general purpose, 16-bit timers/
counters. They are identified as Timer 0, Timer 1 and Timer 2 and can be independently
configured to operate in a variety of modes as a timer or as an event counter. When
operating as a timer, the timer/counter runs for a programmed length of time and then
issues an interrupt request. When operating as a counter, the timer/counter counts
negative transitions on an external pin. After a preset number of counts, the counter
issues an interrupt request. The various operating modes of each timer/counter are
described in the following sections.
A basic operation consists of timer registers THx and TLx (x= 0, 1) connected in cascade
to form a 16-bit timer. Setting the run control bit (TRx) in TCON register turns the timer
on by allowing the selected input to increment TLx. When TLx overflows it increments
THx; when THx overflows it sets the timer overflow flag (TFx) in TCON register.
Setting the TRx does not clear the THx and TLx timer registers. Timer registers can be
accessed to obtain the current count or to enter preset values. They can be read at any
time but TRx bit must be cleared to preset their values, otherwise the behavior of the
timer/counter is unpredictable.
The C/Tx# control bit (in TCON register) selects timer operation, or counter operation,
by selecting the divided-down peripheral clock or external pin Tx as the source for the
counted signal. TRx bit must be cleared when changing the mode of operation, otherwise
the behavior of the timer/counter is unpredictable. For timer operation (C/Tx# = 0), the
timer register counts the divided-down peripheral clock. The timer register is incremented
once every peripheral cycle (6 peripheral clock periods). The timer clock rate is FPER /
6, i.e. FOSC / 12 in standard mode or FOSC / 6 in X2 mode. For counter operation
(C/Tx# = 1), the timer register counts the negative transitions on the Tx external input
pin. The external input is sampled every peripheral cycle. When the sample is high in one
cycle and low in the next one, the counter is incremented.
Since it takes 2 cycles (12 peripheral clock periods) to recognize a negative transition,
the maximum count rate is FPER / 12, i.e. FOSC / 24 in standard mode or FOSC / 12 in
X2 mode. There are no restrictions on the duty cycle of the external input signal, but to
ensure that a given level is sampled at least once before it changes, it should be held for
at least one full peripheral cycle. In addition to the “timer” or “counter” selection, Timer
0 and Timer 1 have four operating modes from which to select which are selected by bit-
pairs (M1, M0) in TMOD. Modes 0, 1and 2 are the same for both timer/counters. Mode 3
is different.
The four operating modes are described below. Timer 2, has three modes of operation:
‘capture’, ‘auto-reload’ and ‘baud rate generator’.
Timer 0
Timer 0 is controlled by the four lower bits of the TMOD register and bits 0, 1, 4 and 5 of
the TCON register. TMOD register selects the method of timer gating (GATE0), timer or
counter operation (T/C0#) and mode of operation (M10 and M00). The TCON register
provides timer 0 control functions: overflow flag (TF0), run control bit (TR0), interrupt
flag (IE0) and interrupt type control bit (IT0).
For normal timer operation (GATE0= 0), setting TR0 allows TL0 to be incremented by
the selected input. Setting GATE0 and TR0 allows external pin INT0# to control timer
operation.
Timer 0 overflow (count rolls over from all 1s to all 0s) sets TF0 flag, generating an
interrupt request. It is important to stop timer/counter before changing mode.
As the count rolls over from all 1’s to all 0’s, it sets the timer interrupt flag TF0. The
counted input is enabled to the Timer when TR0 = 1 and either GATE = 0 or INT0 = 1.
(Setting GATE = 1 allows the Timer to be controlled by external input INT0, to facilitate
pulse width measurements). TR0 is a control bit in the Special Function register TCON.
GATE is in TMOD.
The 13-bit register consists of all 8 bits of TH0 and the lower 5 bits of TL0. The upper 3
bits of TL0 are indeterminate and should be ignored. Setting the run flag (TR0) does not
clear the registers.
Mode 0 operation is the same for Timer 0 as for Timer 1. There are two different GATE
bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).
Timer/Counter x (x = 0 or 1) in Mode 0
Mode 1 (16-bit Timer)
Mode 1 is the same as Mode 0, except that the Timer register is being run with all 16 bits.
Mode 1 configures timer 0 as a 16-bit timer with the TH0 and TL0 registers connected in
cascade. The selected input increments the TL0 register.
Timer/Counter x (x = 0 or 1) in Mode 1
When the interrupt request is serviced, hardware clears TF0. The reload leaves TH0
unchanged. The next reload value may be changed at any time by writing it to the TH0
register. Mode 2 operation is the same for Timer/Counter 1.
Timer/Counter x (x = 0 or 1) in Mode 2
Mode 3 (Two 8-bit Timers)
Mode 3 configures timer 0 so that registers TL0 and TH0 operate as separate 8-bit timers.
This mode is provided for applications requiring an additional 8-bit timer or counter. TL0
uses the timer 0 control bits C/T0# and GATE0 in the TMOD register, and TR0 and TF0
in the TCON register in the normal manner. TH0 is locked into a timer function (counting
FPER /6) and takes over use of the timer 1 interrupt (TF1) and run control (TR1) bits.
Thus, operation of timer 1 is restricted when timer 0 is in mode 3.
Timer 1
Timer 1 is identical to timer 0, except for mode 3, which is a hold-count mode. The
following comments help to understand the differences:
• Timer 1 functions as either a timer or event counter in three modes of operation. Timer
1’s mode 3 is a hold-count mode.
• Timer 1 is controlled by the four high-order bits of the TMOD register and bits 2, 3, 6
and 7 of the TCON register. The TMOD register selects the method of timer gating
(GATE1), timer or counter operation (C/T1#) and mode of operation (M11 and M01).
The TCON register provides timer 1 control functions: overflow flag (TF1), run control
bit (TR1), interrupt flag (IE1) and interrupt type control bit (IT1).
• Timer 1 can serve as the baud rate generator for the serial port. Mode 2 is best suited for
this purpose.
• For normal timer operation (GATE1 = 0), setting TR1 allows TL1 to be incremented by
the selected input. Setting GATE1 and TR1 allows external pin INT1# to control timer
operation.
• Timer 1 overflow (count rolls over from all 1s to all 0s) sets the TF1 flag generating an
interrupt request.
• When timer 0 is in mode 3, it uses timer 1’s overflow flag (TF1) and run control bit
(TR1). For this situation, use timer 1 only for applications that do not require an interrupt
(such as a baud rate generator for the serial port) and switch timer 1 in and out of mode 3
to turn it off and on.
• It is important to stop timer/counter before changing modes.
Timer 2
Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter.
The type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 5-2).
Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud
rate generator. The modes are selected by bits in T2CON, as shown in Table 10-1. Timer
2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is
incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods,
the count rate is 1/12 of the oscillator frequency.
In the Counter function, the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin, T2. In this function, the external input is sampled
during S5P2 of every machine cycle. When the samples show a high in one cycle and a
low in the next cycle, the count is incremented. The new count value appears in the
register during S3P1 of the cycle following the one in which the transition was detected.
Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0
transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a
given level is sampled at least once before it changes, the level should be held for at least
one full machine cycle.
Capture Mode
In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0,
Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit
can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same
operation, but a 1-to-0 transition at external input T2EX also causes the current value in
TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the
transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can
generate an interrupt.
Timer in Capture Mode
Setting the DCEN bit enables Timer 2 to count up or down, as shown in Figure 10-2. In
this mode, the T2EX pin controls the direction of the count. A logic 1 at T2EX makes
Timer 2 count up. The timer will overflow at 0FFFFH and set the TF2 bit. This overflow
also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer
registers, TH2 and TL2, respectively.
A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2
equal the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and
causes 0FFFFH to be reloaded into the timer registers.
The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a
17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt.
Baud Rate Generator
Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON.
Note that the baud rates for transmit and receive can be different if Timer 2 is used for the
receiver or transmitter and Timer 1 is used for the other function. Setting RCLK and/or
TCLK puts Timer 2 into its baud rate generator mode.
The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2
causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H
and RCAP2L, which are preset by software.
The baud rates in Modes 1 and 3 are determined by Timer 2’s overflow rate according to
the following equation.
The Timer can be configured for either timer or counter operation. In most applications, it
is configured for timer operation (CP/T2 = 0). The timer operation is different for Timer
2 when it is used as a baud rate generator. Normally, as a timer, it increments every
machine cycle (at 1/12 the oscillator frequency). As a baud rate generator, however, it
increments every state time (at 1/2 the oscillator frequency). The baud rate formula is
given below.
Where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit
unsigned integer.
Timer 2 as a baud rate generator is shown in the below figure. This figure is valid only if
RCLK or TCLK = 1 in T2CON. Note that a rollover in TH2 does not set TF2 and will
not generate an interrupt. Note too, that if EXEN2 is set, a 1-to-0 transition in T2EX will
set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus,
when Timer 2 is in use as a baud rate generator, T2EX can be used as an extra external
interrupt.
Note that when Timer 2 is running (TR2 = 1) as a timer in the baud rate generator mode,
TH2 or TL2 should not be read from or written to. Under these conditions, the Timer is
incremented every state time, and the results of a read or write may not be accurate. The
RCAP2 registers may be read but should not be written to, because a write might overlap
a reload and cause write and/or reload errors. The timer should be turned off (clear TR2)
before accessing the Timer 2 or RCAP2 registers.
A 50% duty cycle clock can be programmed to come out on P1.0, as shown in the below
figure. This pin, besides being a regular I/O pin, has two alternate functions. It can be
programmed to input the external clock for Timer/Counter 2 or to output a 50% duty
cycle clock ranging from 61 Hz to 4 MHz (for a 16-MHz operating frequency).
Interrupts
The AT89S52 has a total of six interrupt vectors: two external interrupts (INT0 and
INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These
interrupts are all shown in Figure 13-1.
Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register
T2CON. Neither of these flags is cleared by hardware when the service routine is
vectored to. In fact, the service routine may have to determine whether it was TF2 or
EXF2 that generated the interrupt, and that bit will have to be cleared in software.
The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the
timers overflow. The values are then polled by the circuitry in the next cycle. However,
the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer
overflows.
Idle Mode
In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active.
The mode is invoked by software. The content of the on-chip RAM and all the special
functions registers remain unchanged during this mode. The idle mode can be terminated
by any enabled interrupt or by a hardware reset.
Note that when idle mode is terminated by a hardware reset, the device normally resumes
program execution from where it left off, up to two machine cycles before the internal
reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this
event, but access to the port pins is not inhibited. To eliminate the possibility of an
unexpected write to a port pin when idle mode is terminated by a reset, the instruction
following the one that invokes idle mode should not write to a port pin or to external
memory.
Power-down Mode
In the Power-down mode, the oscillator is stopped, and the instruction that invokes
Power-down is the last instruction executed. The on-chip RAM and Special Function
Registers retain their values until the Power-down mode is terminated. Exit from Power
down mode can be initiated either by a hardware reset or by an enabled external interrupt.
Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be
activated before VCC is restored to its normal operating level and must be held active
long enough to allow the oscillator to restart and stabilize.
When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched
during reset. If the device is powered up without a reset, the latch initializes to a random
value and holds that value until reset is activated. The latched value of EA must agree
with the current logic level at that pin in order for the device to function properly.
Programming the Flash – Parallel Mode
The AT89S52 is shipped with the on-chip Flash memory array ready to be programmed.
The programming interface needs a high-voltage (12-volt) program enable signal and is
compatible with conventional third-party Flash or EPROM programmers.
The AT89S52 code memory array is programmed byte-by-byte.
Programming Algorithm:
Before programming the AT89S52, the address, data, and control signals should be set up
according to the “Flash Programming Modes”. To program the AT89S52, take the
following steps:
1. Input the desired memory location on the address lines.
5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte
write cycle is self-timed and typically takes no more than 50 µs. Repeat steps 1 through
5, changing the address and data for the entire array or until the end of the object file is
reached.
Data Polling:
The AT89S52 features Data Polling to indicate the end of a byte write cycle. During a
write cycle, an attempted read of the last byte written will result in the complement of the
written data on P0.7. Once the write cycle has been completed, true data is valid on all
outputs, and the next cycle may begin. Data Polling may begin any time after a write
cycle has been initiated.
Ready/Busy:
The progress of byte programming can also be monitored by the RDY/BSY output signal.
P3.0 is pulled low after ALE goes high during programming to indicate BUSY. P3.0 is
pulled high again when programming is done to indicate READY.
Program Verify:
If lock bits LB1 and LB2 have not been programmed, the programmed code data can be
read back via the address and data lines for verification. The status of the individual lock
bits can be verified directly by reading them back.
The signature bytes are read by the same procedure as a normal verification of locations
000H, 100H, and 200H, except that P3.6 and P3.7 must be pulled to a logic low. The
values returned are as follows.
(200H) = 06H
Chip Erase:
In the parallel programming mode, a chip erase operation is initiated by using the proper
combination of control signals and by pulsing ALE/PROG low for a duration of 200 ns -
500 ns.
In the serial programming mode, a chip erase operation is initiated by issuing the Chip
Erase instruction. In this mode, chip erase is self-timed and takes about 500 ms. During
chip erase, a serial read from any address location will return 00H at the data output.
The Code memory array can be programmed using the serial ISP interface while RST is
pulled to VCC. The serial interface consists of pins SCK, MOSI (input) and MISO
(output). After RST is set high, the Programming Enable instruction needs to be executed
first before other operations can be executed. Before a reprogramming sequence can
occur, a Chip Erase operation is required.
The Chip Erase operation turns the content of every memory location in the Code array
into FFH. Either an external system clock can be supplied at pin XTAL1 or a crystal
needs to be connected across pins XTAL1 and XTAL2. The maximum serial clock
(SCK) frequency should be less than 1/16 of the crystal frequency. With a 33 MHz
oscillator clock, the maximum SCK frequency is 2 MHz.
To program and verify the AT89S52 in the serial programming mode, the following
sequence is recommended:
1. Power-up sequence:
If a crystal is not connected across pins XTAL1 and XTAL2, apply a 3 MHz to 33 MHz
clock to XTAL1 pin and wait for at least 10 milliseconds.
2. Enable serial programming by sending the Programming Enable serial
instruction to pin MOSI/P1.5. The frequency of the shift clock supplied at pin
SCK/P1.7 needs to be less than the CPU clock at XTAL1 divided by 16.
3. The Code array is programmed one byte at a time in either the Byte or Page mode. The
write cycle is self-timed and typically takes less than 0.5 ms at 5V.
4. Any memory location can be verified by using the Read instruction which returns the
content at the selected address at serial output MISO/P1.6.
5. At the end of a programming session, RST can be set low to commence normal device
operation.
Data Polling:
The Data Polling feature is also available in the serial mode. In this mode, during a write
cycle an attempted read of the last byte written will result in the complement of the MSB
of the serial output byte on MISO.
The Instruction Set for Serial Programming follows a 4-byte protocol and is shown in the
table given below.
Serial Programming Instruction Set
For Page Read/Write, the data always starts from byte 0 to 255. After the command byte
and upper address byte are latched, each byte thereafter is treated as data until all 256
bytes are shifted in/out. Then the next instruction will be ready to be decoded.
Function
Testing an LED
Colours of LEDs
LEDs are available in red, orange, amber, yellow, green, blue and white. Blue and white
LEDs are much more expensive than the other colours.
The colour of an LED is determined by
the semiconductor material, not by the
colouring of the 'package' (the plastic
body). LEDs of all colours are available
in uncoloured packages which may be
diffused (milky) or clear (often described
as 'water clear'). The coloured packages are also available as diffused (the standard type)
or transparent.
Tri-colour LEDs
The most popular type of tri-colour LED has a red and a green LED combined in
one package with three leads. They are called tri-colour because mixed red and green
light appears to be yellow and this is produced when both the red and green LEDs are on.
The diagram shows the construction of a tri-colour LED. Note the different
lengths of the three leads. The centre lead (k) is the common cathode for both LEDs, the
outer leads (a1 and a2) are the anodes to the LEDs allowing each one to be lit separately,
or both together to give the third colour.
Bi-colour LEDs
A bi-colour LED has two LEDs wired in 'inverse parallel' (one forwards, one backwards)
combined in one package with two leads. Only one of the LEDs can be lit at one time and
they are less useful than the tri-colour LEDs described above.
Sizes, Shapes and Viewing angles of LEDs
As well as a variety of colours, sizes and shapes, LEDs also vary in their viewing
angle. This tells you how much the beam of light spreads out. Standard LEDs have a
viewing angle of 60° but others have a narrow beam of 30° or less. Rapid Electronics
stock a wide selection of LEDs and their catalogue is a good guidetotherangeavailable.
An LED must have a resistor connected in series to limit the current through the LED,
otherwise it will burn out almost instantly.
:
The resistor value, R is given by
R = (VS - VL) / I
VS = supply voltage
VL = LED voltage (usually 2V, but 4V for blue and white LEDs)
I = LED current (e.g. 20mA), this must be less than the maximum permitted
If the calculated value is not available choose the nearest standard resistor value
which is greater, so that the current will be a little less than you chose. In fact you may
wish to choose a greater resistor value to reduce the current (to increase battery life for
example) but this will make the LED less bright.
where:
V = voltage across the resistor (= VS - VL in this case)
So R = (VS - VL) / I
If you wish to have several LEDs on at the same time it may be possible to
connect them in series. This prolongs battery life by lighting several LEDs with the same
current as just one LED.
All the LEDs connected in series pass the same current so it is best if they are all
the same type. The power supply must have sufficient voltage to provide about 2V for
each LED (4V for blue and white) plus at least another 2V for the resistor. To work out a
value for the resistor you must add up all the LED voltages and use this for VL.
If the LEDs require slightly different voltages only the lowest voltage LED will
light and it may be destroyed by the larger current flowing through it. Although identical
LEDs can be successfully connected in parallel with one resistor this rarely offers any
useful benefit because resistors are very cheap and the current used is the same as
connecting the LEDs individually.
POWER SUPPLY:
The input to the circuit is applied from the regulated power supply. The a.c. input i.e.,
230V from the mains supply is step down by the transformer to 12V and is fed to a
rectifier. The output obtained from the rectifier is a pulsating d.c voltage. So in order to
get a pure d.c voltage, the output voltage from the rectifier is fed to a filter to remove any
a.c components present even after rectification. Now, this voltage is given to a voltage
regulator to obtain a pure constant dc voltage.
230V AC
50Hz
D.C
Output
Transformer:
Rectifier:
The output from the transformer is fed to the rectifier. It converts A.C. into
pulsating D.C. The rectifier may be a half wave or a full wave rectifier. In this project, a
bridge rectifier is used because of its merits like good stability and full wave rectification.
Filter:
Capacitive filter is used in this project. It removes the ripples from the output of
rectifier and smoothens the D.C. Output received from this filter is constant until the
mains voltage and load is maintained constant. However, if either of the two is varied,
D.C. voltage received at this point changes. Therefore a regulator is applied at the output
stage.
Voltage regulator:
As the name itself implies, it regulates the input applied to it. A voltage regulator
is an electrical regulator designed to automatically maintain a constant voltage level. In
this project, power supply of 5V and 12V are required. In order to obtain these voltage
levels, 7805 and 7812 voltage regulators are to be used. The first number 78 represents
positive supply and the numbers 05, 12 represent the required output voltage levels.
DESCRIPTION
A variable regulated power supply, also called a variable bench power
supply, is one where you can continuously adjust the output voltage to your
requirements. Varying the output of the power supply is the recommended
way to test a project after having double checked parts placement against
circuit drawings and the parts placement guide.
This type of regulation is ideal for having a simple variable bench power
supply. Actually this is quite important because one of the first projects a
hobbyist should undertake is the construction of a variable regulated power
supply. While a dedicated supply is quite handy e.g. 5V or 12V, it's much
handier to have a variable supply on hand, especially for testing.
Most digital logic circuits and processors need a 5 volt power supply. To use
these parts we need to build a regulated 5 volt source. Usually you start with
an unregulated power supply ranging from 9 volts to 24 volts DC (A 12 volt
power supply is included with the Beginner Kit and the Microcontroller
Beginner Kit.). To make a 5 volt power supply, we use a LM7805 voltage
regulator IC (Integrated Circuit). The IC is shown below.
The LM7805 is simple to use. You simply connect the positive lead of your
unregulated DC power supply (anything from 9VDC to 24VDC) to the Input
pin, connect the negative lead to the Common pin and then when you turn
on the power, you get a 5 volt supply from the Output pin.
CIRCUIT FEATURES
Now the RMS secondary voltage (primary is whatever is consistent with your area) for
our power transformer T1 must be our desired output Vo PLUS the voltage drops across
D2 and D4 ( 2 * 0.7V) divided by 1.414.
This means that Vsec = [13V + 1.4V] / 1.414 which equals about 10.2V. Depending on
the VA rating of your transformer, the secondary voltage will vary considerably in
accordancewith the applied load. The secondary voltage on a transformer advertised as
say 20VA will be much greater if the secondary is only lightly loaded.
If we accept the 2.5% ripple as adequate for our purposes then at 13V this
becomes 13 * 0.025 = 0.325 Vrms. The peak to peak value is 2.828 times this value. Vrip
= 0.325V X 2.828 = 0.92 V and this value is required to calculate the value of C1. Also
required for this calculation is the time interval for charging pulses. If you are on a 60Hz
system it it 1/ (2 * 60 ) = 0.008333 which is 8.33 milliseconds. For a 50Hz system it is
0.01 sec or 10 milliseconds.
Remember the tolerance of the type of capacitor used here is very loose. The
important thing to be aware of is the voltage rating should be at least 13V X 1.414 or
18.33. Here you would use at least the standard 25V or higher (absolutely not 16V).With
our rectifier diodes or bridge they should have a PIV rating of 2.828 times the Vsec or at
least 29V. Don't search for this rating because it doesn't exist. Use the next highest
standard or even higher. The current rating should be at least twice the load current
maximum i.e. 2 X 0.5A or 1A. A good type to use would be 1N4004, 1N4006 or 1N4008
types.
These are rated 1 Amp at 400PIV, 600PIV and 1000PIV respectively. Always
be on the lookout for the higher voltage ones when they are on special.
TRANSFORMER RATING - In our example above we were taking 0.5A out of the
Vsec of 10V. The VA required is 10 X 0.5A = 5VA. This is a small PCB mount
transformer available in Australia and probably elsewhere.
This would be an absolute minimum and if you anticipated drawing the
maximum current all the time then go to a higher VA rating.
The two capacitors in the primary side are small value types and if you don't know
precisely and I mean precisely what you are doing then OMIT them. Their loss won't
cause you heartache or terrible problems.
THEY MUST BE HIGH VOLTAGE TYPES RATED FOR A.C USE
The fuse F1 must be able to carry the primary current but blow under
excessive current, in this case we use the formula from the diagram. Here N = 240V /
10V or perhaps 120V / 10V. The fuse calculates in the first instance to [ 2 X 0.5A ] / [240
/ 10] or .04A or 40 ma. In the second case .08A or 80 ma. The difficulty here is to find
suitable fuses of that low a current and voltage rating. In practice you use the closest you
can get (often 100 ma ). Don't take that too literal and use 1A or 5A fuses.
CONSTRUCTION
The whole project MUST be enclosed in a suitable box. The main switch
(preferably double pole) must be rated at 240V or 120V at the current rating. All exposed
parts within the box MUST be fully insulated, preferably with heat shrink tubing.
1) Technology
2) Design
Conductor materials available are silver, brass, aluminium and copper. Copper is most
widely used. The thickness of conducting material depends upon the current carrying
capacity of circuit. Thus a thicker copper layer will have more current carrying capacity.
The printed circuit boards usually serves three distinct functions.
Advantages of PCB
1) When a number of identical assemblies are required. PCB’s provide cost saving
because once a layout is approved there is no need to check the circuit every time.
2) For large equipments such as computers, the saving on checking connections or
wires is substantial.
3) PCB’s have controllable and predictable electrical and mechanical properties.
4) A more uniform product is produced because wiring errors are eliminated.
5) The distributed capacitances are constant from one production to another.
6) Soldering is done in one operation instead of connecting discrete components by
wires.
7) The PCB construction lands itself for automatic assembly.
8) Spiral type of inductors may be printed.
9) Weight is less.
10) It has miniaturization potential.
11) It has reproducible performance.
12) All the signals are accessible for testing at any point along conductor track.
Classifications of laminates :
Laminates
Glass base lamination Paper base lamination
There materials are built from several layers of paper or glass, which are bound
together under heat and pressure to form rigid sheets. The binder is usually a phenolic
resin in the case of glass base.
The copper layer is formed on either side or two sides of the laminate.
Because of the different filters and binding resins the characteristic properties of
copper clad laminates change.
The rigid sheets of filters which form reinforcement use paper in the form of
alpha cellulose, craft or rags. These are cheaper and have easy machinbillity. Glass
filter uses glass fibers which are woven to give cloth like appearance. This gives a
high mechanical strength, they are better moisture resistant than above type.
(1) Phenolic:
Phenol and formaldehyde produce phenolic paper base laminate has phenolic
resins with proper filter. The co lour of this base material is usually brown and it is
opaque. Certain additives and the grid is called FR grade.
Disadvantages:
They can be divided into (a) epoxy glass (b) epoxy paper
Epoxy paper: this is also paper base is impregnated with epoxy resin. The co lour is
yellowish white and it is translucent.
Epoxy glass: this base material is more expensive but is combines relative strength and
good is mainly because of glass fiber. The co lour of this material is usually green and it
is semitransparent.
They are mostly used with glass fiber. Their water resistance is good.
These are mostly used with glass fiber. Their maximum temperature limit is 165C.
Advantages:
(a)It has low dissipation factor over wide rang of temperature, humidity and
frequency rang.
They have good heat resistance and good electrical properties .However their
mechanical properties are not good.
There are a number of specifications that are applicable to copper clad laminated e.g.
CIRCUIT DESCRIPTION
SCHEMATIC DIAGRAM:
SCHEMATIC DIAGRAM OF CONROLLER
5v
D7
D6 5v 5v R1 R2
D5
D4 10k 10k 1k 1k
D3
D2 5v
D1 SC L
D0 C1 0 .1 u F SD A
R 3R 4R 5R 6R 7R 8R 9R 1 0 R 1R1 1R2 1R3 1R4 1R5 1R6 1R7 1 8
U1
40
JP1 JP2
VC C
39 8
8 38 P 0.0/AD 0 P 1.7 7 1
7 37 P 0.1/AD 1 P 1.6 6 2
6 36 P 0.2/AD 2 P 1.5 5 3
5v 5 P 0.3/AD 3 P 1.4 4
35 4
4 34 P 0.4/AD 4 P 1.3 3 5
3 33 P 0.5/AD 5 P 1.2 2 6
C2 2 32 P 0.6/AD 6 P 1.1 1 7
C 1 P 0.7/AD 7 P 1.0 8
CON1 9 CON2
R ST
C3 33pF 18 JP3
R 19 XTA L 2 21
8.2k Y1 P 2.0/A8 22 1
P 2.1/A9 23 2
C4 19 P 2.2/A10 24 3
33pF XTA L 1 P 2.3/A11 4
1 1 .5 9 MH z 25
JP4 P 2.4/A12 26 5
17 P 2.5/A13 27 6
8 16 P 3.7/R D P 2.6/A14 28 7
7 15 P 3.6/W R P 2.7/A15 8
6 14 P 3 . 5 / T1
CON4
5 13 P 3 . 4 / TO 29 R 2R0 2R1 2R2 2R3 2R4 2R5 2R6 2 7
CON3 4 12 P 3 . 3 / I N T1 PSEN 30
3 P 3 . 2 / I N TO ALE/PR O G RS
11 31 EN
2 P 3 . 1 / TXD EA/VPP
GND
10 R TC _ D ATA
1 P 3 . 0 / R XD
R TC _ C L K
A T8 9 C 5 1 R TC _ R S T
R XD R 2R9 3R0 3R1 3R2 3R3 3R4 3R5 3 6
20
TXD R 28
1k
5v
5v
5v
2
R 40
1 3
10K POT J4
10K POT 1
2
3
RS 4
5
EN 6
D0 7
D1 8
D2 9
D3 10
D4 11
D5 12
D6 13
D7 14
15
16
5V LC D _C O N
C 13 0 .1 u F
U4
8
SD A 5 1
SD A A0
VC C
2
6 A1 3
SC L SC L A2
VSS
7
WP
2 4 A TC 1 6
4
SCHEMATIC DIAGRAM OF PERIPHARAL
5V
5V
C5 0.1uF
R 3R8 3 9 P1
R R 5
9
16
U2 4
RX 12
R 1O U T R 1IN
13 8
VC C
TX 11
T1 I N
3
8 14 7
10 R 2IN T1 O U T 7 2
T2 I N T2 O U T 9 6
1 R 2O U T 5 1
C6
C+ C 2-
0.1uF C7 C O N N E C TO R D B 9
3 4 C
C 1- C 2+
M A X2 3 2
5V
6 C8
V- 2
V+
GND
C9
0.1uF
C
15
5V
C 10 0 .1 u F
C 11 6uF U3
1
Y2 2
X1
VC C
3 6 R TC _ D ATA
C 12 X2 I/O
6 u F 3 2 .7 6 8 K H z
7 R TC _ C L K
SC LK
8 5 R TC _ R S T
VC C R ST
GND
B T1
3 .3 V D S1302
4
CIRCUIT DESCRIPTION
The main parts of this schematic diagram are:
1. POWER SUPPLY.
2. (AT89S52) MICROCONTROLLER.
3. RELAY 1 LAMP
4. RELAY 2 FAN
5. RELAY 3 TV
KEIL COMPILER:
Keil compiler is software used where the machine language code is written and compiled.
After compilation, the machine source code is converted into hex code which is to be
dumped into the microcontroller for further processing. Keil compiler also supports C
language code.
PRELOAD:
Preload is software which accepts only hex files. Once the machine code is converted
into hex code, that hex code has to be dumped into the microcontroller and this is done by
the Preload. Preload is a programmer which itself contains a microcontroller in it other
than the one which is to be programmed. This microcontroller has a program in it written
in such a way that it accepts the hex file from the Keil compiler and dumps this hex file
into the microcontroller which is to be programmed. As the Preload programmer kit
requires power supply to be operated, this power supply is given from the power supply
circuit designed above. It should be noted that this programmer kit contains a power
supply section in the board itself but in order to switch on that power supply, a source is
required. Thus this is accomplished from the power supply board with an output of
12volts.
After you have tested your application, it is required to create an Intel HEX file to
download the software into an EPROM programmer or simulator. µVision2 creates HEX
files with each build process when Create HEX file under Options for Target – Output is
enabled. You may start your PROM programming utility after the make process when
you specify the program under the option Run User Program #1.
CPU Simulation
µVision2 simulates up to 16 Mbytes of memory from which areas can be
mapped for read, write, or code execution access. The µVision2 simulator traps
and reports illegal memory accesses.
In addition to memory mapping, the simulator also provides support for the
integrated peripherals of the various 8051 derivatives. The on-chip peripherals
of the CPU you have selected are configured from the Device
Database selection
you have made when you create your project target. Refer to page 58 for more
information about selecting a device .You may select and display the on-chip peripheral
components using the Debug menu. You can also change the aspects of each peripheral
using the controls in the dialog boxes.
Start Debugging
You start the debug mode of µVision2 with the Debug – Start/Stop Debug
Session command. Depending on the Options for Target – Debug
configuration, µVision2 will load the application program and run the startup
code µVision2 saves the editor screen layout and restores the screen lay out of the last
debug session. If the program execution stops, µVision2 opens an
editor window with the source text or shows CPU instructions in the disassembly
window. The next executable statement is marked with a yellow arrow. During
debugging, most editor features are still available.
For example, you can use the find command or correct program errors. Program source
text of your application is shown in the same windows. The µVision2 debug mode differs
from the edit mode in the following aspects:
_ The “Debug Menu and Debug Commands” described on page 28 are
available. The additional debug windows are discussed in the following.
_ The project structure or tool parameters cannot be modified. All build
commands are disabled.
Disassembly Window
The Disassembly window shows your target program as mixed source and assembly
program or just assembly code. A trace history of previously executed instructions may
be displayed with Debug – View Trace Records. To enable the trace history, set Debug –
Enable/Disable Trace Recording.
If you select the Disassembly Window as the active window all program step commands
work on CPU instruction level rather than program source lines. You can select a text line
and set or modify code breakpoints using toolbar buttons or the context menu commands.
You may use the dialog Debug – Inline Assembly… to modify the CPU
instructions. That allows you to correct mistakes or to make temporary changes to the
target program you are debugging.
15. Click on the file option from menu bar and select “new”
16. The next screen will be as shown in next page, and just maximize
it by double clicking on its blue boarder.
20. Now you will get another window, on which by default “C” files
will appear.
21. Now select as per your file extension given while saving the file
22. Click only one time on option “ADD”
23. Now Press function key F7 to compile. Any error will appear if so
happen.
27. Now Click on the Peripherals from menu bar, and check your
required port as shown in fig below
28. Drag the port a side and click in the program file.
29. Now keep Pressing function key “F11” slowly and observe.
30. You are running your program successfully
SOURCE CODE:
#include<reg51.h>
#define ON 1
#define OFF 0
void main(void)
{
unsigned char i=0;
serialtx_str(str1);
for(i=0;i<200;i++);
serialtx_str(str2);
for(i=0;i<200;i++);
while(1)
{
delay_ms(100);
}
}