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Processors
Scalar and superscalar
A scalar processor acts on one piece of data at a time. MIPS pipelined processor is a scalar processor. A vector processor acts on several pieces of data with a single instruction. A superscalar processor issues several instructions at a time, each of which operates on one piece of data. ARM pipelined processor is a scalar processor. Scalar processors Scalar processors are the most basic type of processor. These usually process just one item at a time, typically integers or floating point numbers. Floating point numbers are numbers that are either too large or small to be represented by integers. According to the scalar system of ordering information, each instruction is handled sequentially. As a result, scalar processing can take up some time. Vector Processors Vector processors typically operate on an array of data points. This means that rather than handling each item individually, multiple items that all have the same instruction can be completed at once. This can save time over scalar processing, but also adds complexity to a system; this can and often does slow other functions. Vector processing usually works best when there is a large amount of data to be processed. In these instances, groups of data and individual data sets can be handled by one instruction. Superscalar processor A superscalar processor can independently execute multiple instructions at once during a single clock cycle. It includes redundant execution resources, such as multiple floating-point units, arithmetic logic units and integer shifters. This type of processor is designed for parallel computing and speculative execution without the need for special software. It can improve the execution speed of many processor- intensive applications by manipulating and rearranging code. It is frequently used in several classes of computers, including servers, desktops and even laptops. Although some aspects of the architecture have been used in processors since the 1960s, true superscalar processors were not released until much later. Some Reduced Instruction Set Computing (RISC) processors sold in the late 1980s and early 1990s were superscalar. Their simple cores and fixed-length instructions made dispatching and scheduling of parallel instructions relatively easy. Many non-RISC processors manufactured since the late 1990s have superscalar architectures as well. Embedded, low-power and other specialty processors are often exceptions, optimizing other aspects of their designs instead of parallel execution. A key feature of a superscalar processor is its ability to execute program code out of order for efficiency reasons. To do this, it must be aware of any instruction's dependencies upon another. If an instruction affects the results of or uses the resources of another, it is highly likely that the two must not be executed in parallel. Techniques exist to eliminate some types of dependencies, but others must delay processing until resources are available. Out-of-order execution must also be able to guarantee proper contents of registers, flags and other resources if a system interrupt occurs. In this case, the system state must look the same, as if the code had been executed sequentially as designed. Another consideration is how many instructions the processor should examine to find opportunities for parallel execution. The greater the number, the more efficient the execution can be. This also includes speculative execution of instructions on the other side of each branch in the examined code. From Scalar to Super Scalar Pipelines Diversified Pipelines Dynamic Pipelines SuperScalar Processor A more aggressive approach is to equip the processor with multiple processing units to handle several instructions in parallel in each processing stage. With this arrangement, several instructions start execution in the same clock cycle and the process is said to use multiple issue. Such processors are capable of achieving an instruction execution throughput of more than one instruction per cycle. They are known as ‘Superscalar Processors’.