Code des sources des TP VHDL

TP N°4: Design of logic circuit with Quartus II –

CPLD/FPGA

Activité pratique 4 : Feux de carrefour ( Traffic Light Controller)

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Use ieee.std_logic_unsigned.all;

entity traffic_light is
PORT ( CLOCK : in std_logic;
LED_COM : out std_logic;
Lout : out std_logic_vector ( 11 downto 0 ) );
end traffic_light;

architecture DESCRIPTION of traffic_light is

signal CMP10 : std_logic_vector ( 3 downto 0 ) ;
signal CMP2 : std_logic_vector ( 1 downto 0 ) ;
signal C10 : std_logic;
signal C2 : std_logic;
signal OutTmp : std_logic_vector ( 11 downto 0 ):="100100001001";

signal e:std_logic_vector(24 downto 0);

signal c:bit;

begin
LED_COM <= '1';

process( CLOCK )
begin
if CLOCK'event and CLOCK='1' then
if e>10000000 then
e<=(others=>'0');
else e<=e+1;
end if;

if e<5000000 then
c<='0';
else c<='1';
end if;
end if;
end process;

process ( c, OutTmp )
begin
if ( c = '1' and c'event) then
if (OutTmp = "100100001001" or OutTmp = "001001100100")
then
CMP10 <= CMP10 + 1;
if (CMP10 = "1001") then
C10 <= '1';
CMP10 <= "0000";

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 Code des sources des TP VHDL

end if;
else C10 <= '0';
end if;
end if;
end process;

process ( c )
begin
if ( c = '1' and c'event) then
if (OutTmp = "100100010010" or OutTmp = "010010100100")
then
CMP2 <= CMP2 + 1;
if (CMP2 = "01") then
C2 <= '1';
CMP2 <= "00";
end if;
else C2 <= '0';
end if;
end if;
end process;

process ( c, C2, C10 )

begin
if ( c = '1' and c'event) then
if (C10 = '1' and OutTmp = "100100001001") then
OutTmp <= "100100010010"; end if;
if (C2 = '1' and OutTmp = "100100010010") then
OutTmp <= "001001100100"; end if;
if (C10 = '1' and OutTmp = "001001100100") then
OutTmp <= "010010100100"; end if;
if (C2 = '1' and OutTmp = "010010100100") then
OutTmp <= "100100001001"; end if;

end if;
end process;
Lout <= OutTmp;
end DESCRIPTION;

Par M. JAROU 2|Page

 Code des sources des TP VHDL

Activité pratique 5 : Matrice de LED

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity matrix is
port(CLOCK:in std_logic;
R,CR,CG: out std_logic_vector(7 downto 0));
end matrix;
architecture description_matrix of matrix is
type Vect is Array(0 to 7) of std_logic_vector(7 downto 0);
type Names is Array (0 to 4) of Vect;--Two dimensions array it contains the 7 sequences to
display a specific letter
signal n:integer:=0;
signal Rows:Vect; -- sequence des lignes
signal CRH,CRT,CRZ,CRU,CRIN:Vect;--sequence des colones , lettre de nom
signal Na:Names;
signal m,cpt:integer:=0;
signal c: bit ;
signal e:std_logic_vector(24 downto 0);

begin
Rows(0)<="00000001";
Rows(1)<="00000010";
Rows(2)<="00000100";
Rows(3)<="00001000";
Rows(4)<="00010000";
Rows(5)<="00100000";
Rows(6)<="01000000";
Rows(7)<="10000000";

--Letter H

CRH(0)<="11000011";
CRH(1)<="11000011";
CRH(2)<="11000011";
CRH(3)<="11111111";
CRH(4)<="11111111";
CRH(5)<="11000011";
CRH(6)<="11000011";
CRH(7)<="11000011";

--Letter T
CRT(0)<="11111111";
CRT(1)<="11111111";
CRT(2)<="00011000";
CRT(3)<="00011000";
CRT(4)<="00011000";
CRT(5)<="00011000";
CRT(6)<="00011000";
CRT(7)<="00011000";

--letter Z
CRZ(0)<="11111111";
CRZ(1)<="11111111";
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CRZ(2)<="11000000";
CRZ(3)<="00110000";
CRZ(4)<="00001100";
CRZ(5)<="00000011";
CRZ(6)<="11111111";
CRZ(7)<="11111111";

--signe "up"
CRU(0)<="00011000";
CRU(1)<="00111100";
CRU(2)<="01111110";
CRU(3)<="11111111";
CRU(4)<="00011000";
CRU(5)<="00011000";
CRU(6)<="00011000";
CRU(7)<="00011000";

--sign interdit
CRIN(0)<="00011000";
CRIN(1)<="00111100";
CRIN(2)<="01111110";
CRIN(3)<="10000001";
CRIN(4)<="01111110";
CRIN(5)<="00111100";
CRIN(6)<="00011000";
CRIN(7)<="00000000";

--Storing of letter's sequences in the two dimensional array

Na(0)<=CRH;
Na(1)<=CRT;
Na(2)<=CRZ;
Na(3)<=CRU;
Na(4)<=CRIN;
-------------------------------------------
process(CLOCK)
begin
if CLOCK'event and CLOCK='1' then
if e>10000 then
e<=(others=>'0');
else e<=e+1;
end if;

if e<5000 then
c<='0';
else c<='1';
end if;
--if add>6 then
--add<=(others=>'0');
--else add<=add+1;
--end if;
end if;
end process;

process(c)
begin
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 Code des sources des TP VHDL

if ( c = '1' and c'event) then

cpt<=cpt+1;
R<=Rows(n);
if (m = 5) then
m<=0;
end if;
if (m = 4) then
CR<=(Na(m)(n));
CG<="00000000";
n<=n+1;

else if (m = 3) then
CG<=(Na(m)(n));
CR<="00000000";
n<=n+1;
else
CR<=Na(m)(n);
CG<=(Na(m)(n));
n<=n+1;
end if;
end if;
if (n=8)then
n<=0;
end if;
if(cpt=400) then
m<=m+1;
cpt<=0;
end if;
end if;

end process;

end description_matrix;

Par M. JAROU 5|Page

 Code des sources des TP VHDL

Activité pratique 7 : LCD (LCD displayer)

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ensa_lcd is
port( clk,rst:in std_logic;
com:out std_logic_vector(2 downto 0);
fct:out std_logic_vector(7 downto 0));
end entity;
architecture cmp of ensa_lcd is
signal clk_int,e:std_logic_vector(25 downto 0);
signal c,button:std_logic;
signal button1,button2,button_pressed:std_logic;
type etat is (etat_rien, etat_efface, etat_efface2, etat_retour, etat_retour2, etat_conf, etat_conf2,
etat_allume, etat_allume2, etat_mode, etat_mode2, etat_ecrit);
signal etat_actuel:etat;
signal etat_futur:etat;
type tab is array(12 downto 0) of std_logic_vector(7 downto 0);
signal tab_a:tab;
shared variable i:integer:=0;
begin
----------------------------------
process(clk)
begin
if clk'event and clk='1'then
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 Code des sources des TP VHDL

if e>10000000 then e<=(others=>'0');

else e<=e+1;
end if;
button<=e(15);
if clk_int>1000 then clk_int<=(others=>'0');
else clk_int<=clk_int+1;
end if;
if clk_int<500 then c<='0';
else c<='1';
end if;
end if;
end process;
-------------------------------
process(c)
begin
if c'event and c='1' then
button1<=button;
button2<=button1;
end if;
end process;
button_pressed<=button1 and not button2;
process(c)
begin
if c'event and c='1'then
etat_actuel<=etat_futur;
end if;
end process;
----------------------------------------
process(button_pressed,rst)
begin
if button_pressed'event and button_pressed='1'then i:=i+1;
end if;
if rst='1'then i:=0;
end if;
end process;
process(rst,c,etat_actuel,tab_a,button_pressed)
variable e,esp,k,i_1,t,r:std_logic_vector(7 downto 0);
variable n:std_logic_vector(7 downto 0);
variable s:std_logic_vector(7 downto 0);
variable a:std_logic_vector(7 downto 0);
begin
e:="01000101";
n:="01001110";
s:="01010011";
a:="01000001";
esp:="00010000";
k:="01001011";
i_1:="01001001";
t:="01010100";
r:="01010010";
tab_a<=(a,r,t,i_1,n,e,k,esp,a,s,n,e,esp);
case etat_actuel is
when etat_rien=>
if button_pressed='1' and i<=12 then etat_futur<=etat_conf;
elsif rst='1'then etat_futur<=etat_efface;
elsif i>12 then etat_futur<=etat_rien;
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else etat_futur<=etat_rien;
end if;
com<="000";
fct<="00000000";
when etat_efface=>
com<="100";
fct<="00000001";
etat_futur<=etat_efface2;
when etat_efface2 =>
com<="000";
fct<="00000001";
etat_futur<=etat_retour;
when etat_retour=>
com<="100";
fct<="00000010";
etat_futur<=etat_retour2;
when etat_retour2=>
com<="000";
fct<="00000001";
etat_futur<=etat_rien;
when etat_conf=>
com<="100";
fct<="00111000";
etat_futur<=etat_conf2;
when etat_conf2=>
com<="000";
fct<="00001100";
etat_futur<=etat_allume;
when etat_allume=>
com<="100";
fct<="00001110";
etat_futur<=etat_allume2;
when etat_allume2=>
com<="000";
fct<="00001110";
etat_futur<=etat_mode;
when etat_mode=>
com<="100";
fct<="00000110";
etat_futur<=etat_mode2;
when etat_mode2=>
com<="000";
fct<="00000110";
etat_futur<=etat_ecrit;
when etat_ecrit=>
com<="110";
fct<=tab_a(i);
etat_futur<=etat_rien;
end case;
end process;
end cmp;

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 Code des sources des TP VHDL

Activité pratique 8 : Générateur/diviseur de fréquence (Frequency Generator)

--freq_div_10.vhdl
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Use ieee.std_logic_unsigned.all;

entity freq_div_10 is
PORT ( s_in : in std_logic;
s_out : out std_logic );
end freq_div_10;

architecture description of freq_div_10 is

signal CMP : std_logic_vector ( 3 downto 0 ) ;
signal e:std_logic_vector(24 downto 0);
signal c:bit;

begin
process( s_in )
begin
if (s_in'event and s_in='1') then
if e>=9 then
e<=(others=>'0');
else e<=e+1;
end if;

if e<=4 then
s_out<='0';
else s_out<='1';
end if;
end if;
end process;
end description;

--Multiplexeur_vhdl.vhdl
library ieee;
use ieee.std_logic_1164.all;
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 Code des sources des TP VHDL

entity Multiplexeur_vhdl is
port (a, b, c, d, e, f, g, h: in std_logic;
Sel: in std_logic_vector(2 downto 0);
ledOut : out std_logic_vector (7 downto 0);
Output: out std_logic);
end Multiplexeur_vhdl;

architecture Comportement of Multiplexeur_vhdl is

begin
process (a, b, c, d, e, f, g, h, Sel) is
begin
case Sel is
when "111" => Output <= h; ledOut <= "00000001";
when "110" => Output <= g; ledOut <= "00000010";
when "101" => Output <= f; ledOut <= "00000100";
when "100" => Output <= e; ledOut <= "00001000";
when "011" => Output <= d; ledOut <= "00010000";
when "010" => Output <= c; ledOut <= "00100000";
when "001" => Output <= b; ledOut <= "01000000";
when "000" => Output <= a; ledOut <= "10000000";
end case;
end process;
end Comportement;

-- frequency_generator.vhd
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Use ieee.std_logic_unsigned.all;

entity frequency_generator is
PORT ( OSC : in std_logic;
c_10M,c_1M,c_100K,c_10K,c_1K,c_100,c_10,c_1 : out std_logic );
end frequency_generator;

architecture description of frequency_generator is

component freq_div_10
PORT(s_in : in std_logic;
s_out : out std_logic
);
end component;

signal wire_1 : std_logic;

signal wire_2 : std_logic;
signal wire_3 : std_logic;
signal wire_4 : std_logic;
signal wire_5 : std_logic;
signal wire_6 : std_logic;

begin
c_10M <= OSC;
c_1M <= wire_1;
c_100K <= wire_2;

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 Code des sources des TP VHDL

c_10K <= wire_3;

c_1K <= wire_4;
c_100 <= wire_5;
c_10 <= wire_6;

U1 : freq_div_10
PORT MAP(s_in => OSC,
s_out => wire_1);

U2 : freq_div_10
PORT MAP(s_in => wire_1,
s_out => wire_2);

U3 : freq_div_10
PORT MAP(s_in => wire_2,
s_out => wire_3);

U4 : freq_div_10
PORT MAP(s_in => wire_3,
s_out => wire_4);

U5 : freq_div_10
PORT MAP(s_in => wire_4,
s_out => wire_5);

U6 : freq_div_10
PORT MAP(s_in => wire_5,
s_out => wire_6);

U7 : freq_div_10
PORT MAP(s_in => wire_6,
s_out => c_1);

end description;

--Freq_gen_mux.vhd
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Use ieee.std_logic_unsigned.all;

entity Freq_gen_mux is
PORT ( OSCIL, up, down : in std_logic;
LED : out std_logic_vector (7 downto 0);
DE : out std_logic_vector (2 downto 0);
Csel : out std_logic;
LEDCOM : out std_logic );
end Freq_gen_mux;

architecture description of Freq_gen_mux is

component frequency_generator
PORT ( OSC : in std_logic;
c_10M,c_1M,c_100K,c_10K,c_1K,c_100,c_10,c_1 : out
std_logic );
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 Code des sources des TP VHDL

end component;

component Multiplexeur_vhdl
PORT (a, b, c, d, e, f, g, h: in std_logic;
Sel: in std_logic_vector(2 downto 0);
ledOut : out std_logic_vector (7 downto 0);
Output: out std_logic);
end component;

signal cmp_wire : std_logic_vector ( 2 downto 0 ):= "000";

signal out_wire : std_logic;

signal wire_1 : std_logic;

signal wire_2 : std_logic;
signal wire_3 : std_logic;
signal wire_4 : std_logic;
signal wire_5 : std_logic;
signal wire_6 : std_logic;
signal wire_7 : std_logic;
signal wire_8 : std_logic;

signal upDown : std_logic;

signal CupDown : std_logic;

begin
upDown <= up xor down;
CupDown <= wire_7 and upDown;
LEDCOM <= '1';
DE <= "110";

process (CupDown)
begin
if (CupDown'event and CupDown='0') then
if (cmp_wire < "111" and down = '0') then cmp_wire <= cmp_wire + 1;
else if (cmp_wire > "000" and up = '0') then cmp_wire <= cmp_wire - 1; end
if;
end if;
end if;
end process;

U1 : frequency_generator
PORT MAP( OSC => OSCIL,
c_10M => wire_1,
c_1M => wire_2,
c_100K => wire_3,
c_10K => wire_4,
c_1K => wire_5,
c_100 => wire_6,
c_10 => wire_7,
c_1 => wire_8);

U2 : Multiplexeur_vhdl
PORT MAP(a => wire_1,
b => wire_2,
c => wire_3,
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 Code des sources des TP VHDL

d => wire_4,
e => wire_5,
f => wire_6,
g => wire_7,
h => wire_8,
ledOut => LED,
Sel => cmp_wire,
Output => Csel);

end description;

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 Code des sources des TP VHDL

Chronomètre

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