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Verilog Full Adder

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5 views9 pages

Verilog Full Adder

Uploaded by

mursaleenkhan0127489
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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12/15/2024 Application of ICT

LEARNING THE BASICS OF


PYTHON LANGUAGE

Submitted by:
• Muhammad Mohsin Khan
(CMS ID: 505636)
• Shahab Khan
(CMS ID: 508429)
• Eyesha tur radia
(CMS ID: 519787)

CE-46B
Submitted to:
• Dr. Asad Mansoor Khan
Application of ICT lab report #11

OBJECTIVES:
The purpose of this lab was to learn the basics of varilog by designing full-adder and
comparator

TASK #01

CODE:
module full_adder(a,b,c_in,sum,c_out);

input a,b,c_in;

output sum,c_out;
01
Application of ICT lab report #11

wire s1,s2,c1;

assign s1 = (~a & b) | (a & ~b);

assign c1 = a & b;

assign s2 = s1 & c_in;

assign sum = (~s1 & c_in) | (s1 & ~c_in);

assign c_out = (~s2 & c1) | (s2 & ~c1);

endmodule

TEST BENCH:
MODULE TB _ FULL _ ADDER ;

// I NPUTS

REG A ;

REG B ;

REG C_ IN ;

// O UTPUTS

WIRE SUM ;

WIRE C _ OUT;

02
Application of ICT lab report #11

// I NSTANTIATE THE U NIT U NDER T EST (UUT)

FULL _ ADDER UUT (

. A( A),

. B( B),

. C_ IN( C_ IN),

. SUM( SUM),

. C_ OUT( C_OUT)

);

INITIAL BEGIN

// I NITIALIZE I NPUTS

A = 0;
B = 0;

C _ IN = 0;

// W AIT 100 NS FOR GLOBAL RESET TO FINISH

#100;

// A DD STIMULUS HERE

A = 1;

B = 1;

C _ IN = 1;

#30;

A = 0;

B = 1;

C _ IN = 0;

#30;
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Application of ICT lab report #11

A = 1;

B = 0;

C _ IN = 1;

#30;

END

ENDMODULE

OUTPUT:

04
Application of ICT lab report #11

TASK #02:

CODE:
module q2(a,b,o1,o2,o3); //getting module

input a,b; //assigning input

output o1,o2,o3; //assigning output

wire w1,w2,w3,w4; //assigning wires

assign w1=~a; //A not

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Application of ICT lab report #11

assign w2=~b; //B not

assign w3=w1 & b; //A not And B

assign w4=w2 & a; //B not And a

assign o1= w1 & b; //a<b

assign o2= ~(w3 | w4); //a=b

assign o3= w2 & a; //a>b

endmodule

TEST BENCH:
module tb_q2;

// Inputs

reg a;

reg b;

// Outputs

wire o1;

wire o2;

wire o3;

// Instantiate the Unit Under Test (UUT)

q2 uut (

.a(a),

.b(b),

.o1(o1),

.o2(o2),
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Application of ICT lab report #11

.o3(o3)

);

initial begin

// Initialize Inputs

a = 0;

b = 0;

// Wait 100 ns for global reset to finish

#100;

// Initialize Inputs

a = 1;

b = 0;

// Wait 100 ns for global reset to finish

#100;

// Initialize Inputs

a = 0;

b = 1;

// Wait 100 ns for global reset to finish

#100;

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Application of ICT lab report #11

// Add stimulus here

end

endmodule

OUTPUT:

CONCLUSION:

we understand the basics use of varilog

08

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