12/22/2024 Application of ICT

LEARNING THE BASICS OF

Submitted by:
• Muhammad Mohsin Khan
(CMS ID: 505636)
• Shahab Khan
(CMS ID: 508429)
• Eyesha tur radia
(CMS ID: 519787)

CE-46B
Submitted to:
• Dr. Asad Mansoor Khan
Application of ICT lab report #12

OBJECTIVES:
The purpose of this lab was to learn Behavioral Modeling to design complex Logic.

TASK #01

Verilog script:
module aludesign(A,B,C,OPCODE);

input [3:0] A,B;

input [1:0] OPCODE;

output reg [3:0] C;

always @ (*)

begin

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Application of ICT lab report #12

if (OPCODE==0)

C = A + B;

else if (OPCODE==1)

C = A - B;

else if (OPCODE==2)

C = A | B;

else if (OPCODE==3)

C = A & B;

else if (OPCODE==4)

C = A >> B;

else if (OPCODE==5)

C = A << B;

else

C = 0 ;
end

endmodule

TEST BENCH:
MODULE TB_ ALUDESIGN;

// I NPUTS

REG [3:0] A;

REG [3:0] B;

REG [1:0] OPCODE;

// O UTPUTS

WIRE [3:0] C;

// I NSTANTIATE THE UNIT UNDER T EST (UUT)

ALUDESIGN UUT (

.A(A),

.B(B),

.C(C),
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Application of ICT lab report #12

.OPCODE(OPCODE)

);

INITIAL BEGIN

// I NITIALIZE INPUTS

A = 3;

B = 2;

OPCODE = 0;

// W AIT 100 NS FOR GLOBAL RESET TO FINISH

#100;

A = 3;

B = 2;

OPCODE = 1;

// W AIT 100 NS FOR GLOBAL RESET TO FINISH

#100;

A = 3;

B = 2;

OPCODE = 2;

// W AIT 100 NS FOR GLOBAL RESET TO FINISH

#100;

A = 3;

B = 2;

OPCODE = 3;

// W AIT 100 NS FOR GLOBAL RESET TO FINISH

#100;

A = 3;
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Application of ICT lab report #12

B = 2;

OPCODE = 4;

// W AIT 100 NS FOR GLOBAL RESET TO FINISH

#100;

A = 3;
B = 2;

OPCODE = 5;

// W AIT 100 NS FOR GLOBAL RESET TO FINISH

#100;

// A DD STIMULUS HERE

END

ENDMODULE

OUTPUT:

04
Application of ICT lab report #12

TASK #02:

Verilog script:
MUX:
module MUX_4_x_1(in1,in2,in3,in4,sel,out);

input [7:0]in1,in2,in3,in4;

output reg [7:0] out;

input [1:0] sel;

always@(*)

begin

if (sel == 0)

out = in1;

else if (sel == 1)

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Application of ICT lab report #12

out = in2;

else if (sel == 2)

out = in3;

else

out = in4;

end

endmodule

ALU:
module ALU(A, B, OPCODE,C);

input [7:0] A, B;

input [2:0] OPCODE;

output reg [7:0] C;

always @(*) begin

case (OPCODE)

3'b000: C = A + B;

3'b001: C = A - B;

3'b010: C = A | B;

3'b011: C = A & B;

3'b100: C = A >> B;

3'b101: C = A << B;

default: C = 4'b0000;

endcase

end

endmodule

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Application of ICT lab report #12

Calling modules:
module rom_alu(opCode,out);

input [2:0]opCode;

output [7:0] out;

wire [1:0]sel1,sel2;

assign sel1 = opCode[1:0];

assign sel2 = opCode[2:1];

wire [7:0] res1,res2;

reg [7:0] ROM [0:3];

initial begin

ROM[0] = 8'b00000010; // 2

ROM[1] = 8'b00000100; // 4

ROM[2] = 8'b00000011; // 3

ROM[3] = 8'b00000111; // 7

end

MUX_4_x_1 mux1(ROM[0],ROM[1],ROM[2],ROM[3],sel1,res1);

MUX_4_x_1 mux2(ROM[0],ROM[1],ROM[2],ROM[3],sel2,res2);

ALU uut1(res1,res2,opCode,out);

endmodule

TEST BENCH:
module tb_ROM_ALU;

// Inputs

reg [2:0] opCode;

// Outputs

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Application of ICT lab report #12

wire [7:0] out;

// Instantiate the Unit Under Test (UUT)

rom_alu uut (

.opCode(opCode),

.out(out)

);

initial begin

// Initialize Inputs

opCode = 0;

// Wait 100 ns for global reset to finish

#100;

opCode = 1;

// Wait 100 ns for global reset to finish

#100;

opCode = 2;

// Wait 100 ns for global reset to finish

#100;

opCode = 3;

// Wait 100 ns for global reset to finish

#100;

opCode = 2;

// Wait 100 ns for global reset to finish

#100;opCode = 1;

// Wait 100 ns for global reset to finish

#100;opCode = 0;
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Application of ICT lab report #12

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

end

endmodule

OUTPUT:

09
Application of ICT lab report #12

TASK #03

Verilog script:
ALU:
module alu(A,B,opCode,C);

input [7:0] A, B;

input [2:0] opCode;

output reg [7:0] C;

always @(*) begin

case (opCode)

3'b000: C = A + B;

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Application of ICT lab report #12

3'b001: C = A - B;

3'b010: C = A | B;

3'b011: C = A & B;

3'b100: C = A >> B;

3'b101: C = A << B;

default: C = 4'b0000;

endcase

end

endmodule

Splitter:
module splitter(instruction,opCode,A,B);

input [18:0] instruction;

output reg [2:0] opCode;

output reg [7:0] A;

output reg [7:0] B;

always @ (*) begin

opCode = instruction[18:16];

A = instruction[15:8];

B = instruction[7:0];

end

endmodule

Calling Module:
module pc_alu(pc,C);

input [2:0] pc;

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Application of ICT lab report #12

output [7:0] C;

wire [18:0] instruction;

wire [7:0] A,B;

wire [2:0] opCode;

ROM rom1(pc,instruction);

splitter split1(instruction,opCode,A,B);

alu alu1(A,B,opCode,C);

endmodule

CONCLUSION:

we understand Behavioral Modeling to design complex Logic.

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