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Signal Integrity Characterization Techniques 2nd Edition
Mike Resso Digital Instant Download
Author(s): Mike Resso, Eric Bogatin [edited by]
ISBN(s): 9781931695930, 1931695938
Edition: 2
File Details: PDF, 9.11 MB
Year: 2009
Language: english
 Signal Integrity
Characterization Techniques

Executive Editors

IEC
Chicago, Illinois
© 2009 by Professional Education International, Inc. All rights of
reproduction, including that of translation into foreign languages, are
reserved. Requests for republication privileges should be addressed to
Publications Department, International Engineering Consortium, 300
West Adams Street, Suite 1210, Chicago, Illinois 60606-5114, USA.

All opinions expressed in Signal Integrity Characterization Techniques

are those of the authors and are not binding on Professional Education
International or the International Engineering Consortium.

ISBN: 978-1-931695-93-0

International Engineering Consortium

300 West Adams Street, Suite 1210
Chicago, Illinois 60606-5114, USA
+1-312-559-4100 voice • +1-312-559-4111
fax [email protected] • www.iec.org

ii
 About the Executive Editors

Mike Resso is the signal integrity application scientist in the component

test division at Keysight Technologies and has over twenty-five years
of experience in the test and measurement industry. His professional
background includes the design and development of electro-optic test
instrumentation for aerospace and commercial applications. His most
recent activity has focused on the complete multiport characterization
of high-speed digital interconnects using time domain reflectometry
and vector network analysis. Mike has authored over 30 professional
publications in such diverse fields as infrared detector probe systems,
linearly variable optical filters and electrically conductive antireflection
coatings. He has been awarded one U.S. patent and has twice received the
Keysight “Spark of Insight” Award for his contribution to the company.
Mike received a B.S. degree in electrical and computer engineering from
University of California in 1983.

Eric Bogatin is signal integrity evangelist at Bogatin Enterprises, which

specializes in training for signal integrity and interconnect design. His
company offers a complete curriculum in short courses and training
materials to help accelerate engineers and managers up the learning
curve to be more effective in fields related to signal integrity. He has
held senior engineering and management positions at such companies as
AT&T Bell Labs, Raychem Corporation, Advanced Packaging Systems,
and Sun Microsystems. For 20 years, he has been involved in various
aspects of signal integrity and inter-connect design, from the materials
side, manufacturing, product design, measurements and, most recently,
education and consulting. Eric has written four books on signal integrity
and inter-connect design, over 200 papers, and most recently wrote a
book entitled Signal Integrity-Simplified published in 2004. Eric received
his Ph.D. in physics from the University of Arizona in Tucson in 1980
and his B.S. in physics from the Massachusetts Institute of Technology
in 1976.

iii
 About the Publisher

The International Engineering Consortium (IEC) is a non-profit

organization dedicated to catalyzing technology and business progress
worldwide in a range of high technology industries and their university
communities. Since 1944, the IEC has provided high-quality educational
opportunities for industry professionals, academics, and students. In
conjunction with industry-leading companies, the IEC has developed
an extensive, free on-line educational program. The IEC conducts
industry-university programs that have substantial impact on curricula.
It also conducts research and develops publications, conferences, and
technological exhibits that address major opportunities and challenges of
the information age. More than 70 leading high-technology universities
are IEC affiliates, and the IEC handles the affairs of the Electrical and
Computer Engineering Department Heads Association and Eta Kappa
Nu, the honor society for electrical and computer engineers. The IEC also
manages the activities of the Enterprise Communications Consortium.

iv
 IEC Corporate Members / University Program Sponsors
The IEC’s University Program, which provides grants for full-time faculty members and
their students to attend IEC Forums, is made possible through the generous contributions
of its Corporate Members. For more information on Corporate Membership or the
University Program, please call +1-312-559-3309 or send an e-mail to [email protected].

IEC Corporate Members

These are some of the universities that participate in the University Grant Program:

The University of Arizona University of Glasgow University of Massachusetts The Pennsylvania State University
Arizona State University Howard University McGill University University of Pennsylvania
Auburn University Illinois Institute of Technology Michigan State University University of Pittsburgh Polytechnic
University of California at Berkeley University of Illinois at Chicago The University of Michigan University
University of California, Davis University of Illinois at University of Minnesota Purdue University
University of California, Santa Urbana/Champaign Mississippi State University The Queen’s University of Belfast
Barbara Imperial College of Science, The University of Mississippi Rensselaer Polytechnic Institute
Carnegie Mellon University Technology and Medicine University of Missouri-Columbia University of Southampton
Case Western Reserve University Institut National Polytechnique University of Missouri-Rolla University of Southern California
Clemson University de Grenoble Technische Universität München Stanford University
University of Colorado at Boulder Instituto Tecnológico y de Estudios Universidad Nacional Autónoma Syracuse University
Columbia University Superiores de Monterrey de México University of Tennessee, Knoxville
Cornell University Iowa State University North Carolina State University Texas A&M University
Drexel University KAIST at Raleigh The University of Texas at Austin
École Nationale Supérieure des The University of Kansas Northwestern University University University of Toronto
Télécommunications de Bretagne University of Kentucky of Notre Dame VA Polytechnic Institute and
École Nationale Supérieure des Lehigh University The Ohio State State University
Télécommunications de Paris University College London University Oklahoma State University of Virginia
École Supérieure d’Électricité Marquette University University University of Washington
University of Edinburgh University of Maryland at College The University of Oklahoma University of Wisconsin-Madison
University of Florida Park Massachusetts Institute of Oregon State University Worcester Polytechnic Institute
Georgia Institute of Technology Technology Université d’Ottawa

v
 Preface

Today’s emerging high-speed digital applications require a special kind

of design engineer who understands the subtle signal integrity issues at
hand. Although a classical electrical and computer engineering education
is helpful, it is the high-frequency microwave effects that normally cause
the most problems within telecommunications and computer systems,
channels, and components. Reflections from impedance discontinuities,
crosstalk, intra-line skew, and a multitude of other problems can
immediately stop a system from working properly.

Clearly, there is a gap in the college electrical engineering courses

between the traditional digital and microwave curricula. This is why
learning never stops for signal integrity engineers. This book addresses
this gap with a focus on a practical and intuitive understanding of signal
integrity effects within the data transmission channel. High-speed
interconnects such as connectors, printed circuit boards (PCBs), cables,
integrated circuit (IC) packages, and backplanes are critical elements of
differential channels that must be designed using today’s most powerful
analysis and characterization tools. Both measurements and simulation
must be done on the device under test, and both activities must yield data
that correlates with each other. Most of this book focuses on real-world
applications of signal integrity measurements.

Since the most intuitive measurements for digital engineers are usually
done in the time domain, this book starts with a fundamental understanding
of single-ended and differential time domain reflectometry (TDR)
measurements in chapters 1 and 2. Chapters 3, 4, and 5 complete the
first major section of this book by describing vector network analyzers
(VNAs) and S-parameters (including 12-port S-parameters).

Section 2 of this book delves into the longest, densest, and highest-
bandwidth application for interconnects: the backplane. While many
high-speed PCBs exhibit difficult signal integrity problems, none can
compare with the typical backplane for design challenges.

The sheer number of layers and signal channels in a backplane create

a design challenge most microwave engineers would find daunting. In
section 2, we describe a methodology for characterizing even the most
complex backplanes.

vii
Signal Integrity Characterization Techniques

Section 3 of this book advances the discussion of linear passive

device characterization with the implementation of sophisticated error
correction techniques. One of the main advantages of using a VNA is
the ultra-precise calibration and de-embedding capabilities. Hence, we
cover this information in great detail in this section of the book.

Section 4 covers various jitter measurements, including such diverse

topics as laser transmitter driver circuitry jitter and a novel statistical
jitter measurement methodology called STATEYE.

New measurement technologies co-evolve with design and technology

innovation within the engineering communities, so the authors wanted to
inspire some new thinking in sections 5 and 6. Analyzing some of these
new technologies can provide valuable insight into the future direction
that our fast-paced world takes us. Solving today’s problems can teach us
valuable lessons indeed, but investigating the future trends is sometimes
akin to viewing a crystal ball. Our hope is to trigger inspiration to learn
more about signal integrity and the high-speed technology around us.

Second Edition Additions

An additional section at the end of the book entitled, “Future Technology
Trends” has been added. This includes such interesting topics as
microprobing, new calibration methods and de-mystifying PCB
channel design. Some new authors are introduced that should enhance
the education value of the book by bringing new insights into the
characterization of signal integrity phenomena.

New graphics were added to reflect newer test equipment brought to

market after the publishing of the first edition. Examples of this are the
N1930B Physical Layer Test System 2015, the M9375A 32-port 26.5
GHz PXI Vector Network Analyzer and the N1055A 9 picosecond Time
Domain Reflectometry module. These novel test systems have industry-
leading performance and therefore merit the addition of their capabilities
into today’s signal integrity reference books.

A few chapters have become outdated due to the previously mentioned

advancements of technology, so these were deleted from the second
edition printing. They have been replaced with appropriate technology
topics that should stimulate the thinking process of the reader even
further than the first edition chapters. At least, that is the hope and desire
of the authors.

viii
 Acknowledgements

We would like to acknowledge the professional help from colleagues

who have assisted in the creation of this signal integrity book. The list of
authors reads like a “who’s who” of signal integrity, so it is with much
thanks that we publish these individuals’ names:

Heidi Barnes Crescencio Gutierrez

Michael Baxter Abraham Islas
Shelley Begley Haw-Jyh Liaw
Orlando Bell Jim Maynard
Osvaldo Buccafusca Tom McCarthy
William Burns Will Miller
Jack Carrel Roland Modinger
Jinhua Chen José Moreira
Antonio Ciccomancini Gary Otonari
Michael Comai Gautam Patel
Steven Corey Stephen Reddy
John D’Ambrosia Jason Roe
Bill Dempsey Anthony Sanders
Jay Diepenbrock Edward Sayre
Dave Dunham Hong Shi
Vince Duperron Dina Smolyansky
John Goldie Laurie Taira-Griffin
Thomas Gneiting Francisco Tamayo-Broes
Kevin Grundy Ming Tsai

A special thanks to Bob Schaefer for his extensive work on chapter

5 that entailed many months of experiments for comparing detailed
measurement data of TDRs and VNAs.

Mike Resso
Keysight Technologies

Eric Bogatin
Bogatin Enterprises

July 2015

ix
Signal Integrity Characterization Techniques

Special Acknowledgement

And finally, a post-humus acknowledgement to my late wife Vivian who

passed after the publication of the first edition. She continues to inspire
me in every aspect of my daily life. Her strong work ethic and pursuit
of intellectual excellence has forever motivated me to continue writing
and giving back to the signal integrity community with knowledge laden
books and papers such as this publication.

Mike Resso
Keysight Technologies

July 2015

x
 Table of Contents

About the Executive Editor.................................................................. iii

About the Publisher................................................................................ iv
Acronym Guide....................................................................................759

Preface............................................................................................... xvii
Acknowledgements........................................................................... xxix

Part I: Getting Started: Introducing TDR and VNA

Techniques and the Power of S-Parameters

Chapter 1: Single-Port TDR, TDR/TDT,.............................................. 3

and 2-Port TDR Measurements
Interconnect Analysis is Simplified with Physical Layer Tools Eric
Bogatin, Signal Integrity Evangelist, Bogatin Enterprises
Mike Resso, Signal Integrity Application Scientist, Component Test
Division, Keysight Technologies
1.1: Introduction ......................................................................... 3
1.2: Single-Port TDR................................................................... 4
1.3: Two-Port TDR/TDT........................................................... 39
1.4: Two-Port TDR/Crosstalk ................................................. 52
1.5: Two-Port Differential TDR (DTDR).................................. 69

Chapter 2: 4-Port TDR/VNA/PLTS Measurements........................91

Eric Bogatin, Signal Integrity Evangelist, Bogatin Enterprises
Mike Resso, Signal Integrity Application Scientist, Component Test
Division, Keysight Technologies
2.1: Introduction ....................................................................... 91
2.2: Four-Port Techniques.......................................................... 92
2.3: Summary ...........................................................................151

Chapter 3: Differential Impedance Design and Verification................153

with a TDR
Eric Bogatin, Signal Integrity Evangelist, Bogatin Enterprises
Mike Resso, Product Manager, Lightwave Division, Keysight
Technologies
3.1: Abstract..............................................................................153
3.2: Overview............................................................................153

xi
Chapter 4: Accuracies and Limitations of Time and...........................209
Frequency Domain Analyses of Physical-Layer Devices
Robert Schaefer, Technical Leader and R&D Project Manager, Signal
Integrity Group, Keysight Technologies
4.1: Introduction.......................................................................185
4.2: Equipment Setup................................................................186
4.3: Fundamental Differences between TDR and VNA..............187
Instruments
4.4: TDR and VNA Sources......................................................189
4.5: Architectures and Sources of Error......................................191
4.6: Calibration and Normalization...........................................194
4.7: Measurement Accuracies: Reciprocity, Repeatability,.......199
and Drift
4.8: Measurement Comparisons................................................206
4.9: Summary...........................................................................213

Chapter 5: Data Mining 12-port s-Parameters...................................215

Eric Bogatin, Signal Integrity Evangelist, Bogatin Enterprises
Mike Resso, Signal Integrity Application Scientist, Component Test
Division, Keysight Technologies
5.1: Abstract.......................................................................215
5.2: High-Speed Serial Links and the Bandwidth of............215
Interconnects
5.3: Four-Port S-Parameters.....................................................216
5.4: Twelve-Port S-Parameters and Information Overload.....221
5.5: Serial-Link Performance Analysis.....................................222
5.6: Losses.........................................................................225
5.7: Impedance Continuities.....................................................226
5.8: Mode Conversion..............................................................228
5.9: Channel-to-Channel Crosstalk..........................................231
5.10: Conclusion.........................................................234

Part II: Backplane Measurements and Analysis

Chapter 6: A Design of Experiments for Gigabit Serial.......................239

Backplane Channels
Jack Carrel, System IO Specialist, Xilinx
Bill Dempsey, Owner and President, Redwire Enterprises
Mike Resso, Signal Integrity Application Scientist, Component Test
Division, Keysight Technologies

xii
 6.1: Abstract..........................................................................239
6.2: Introduction..................................................................239
6.3: Serial Backplane Channels...............................................241
6.4: Backplane Platform Description.....................................242
6.5: Daughtercard Description.................................................247
6.6: Backplane Characterization..............................................249
6.7: eHSD Connection Channels............................................251
6.8: HM-Zd Channels..............................................................253
6.9: HM-2mm Channels..........................................................255
6.10: Crosstalk Measurements...................................................257
6.11: Eye Diagram Analysis......................................................263
6.12: Reference Channels...........................................................267
6.13: Summary......................................................................273

Chapter 7: Gigabit Backplane Design, Simulation and ......................275

Measurement – The Unabridged Story
Edward Sayre, Owner and Director, NESA
Jinhua Chen, Signal Integrity and EMI Engineer, NESA
Michael Baxter, Signal Integrity Engineer, NESA
Gautam Patel, Signal Integrity Engineer, New Product Development,
Teradyne
John Goldie, Member of the Technical Staff, National Semiconductor
Mike Resso, Product Manager, Lightwave Division, Keysight
Technologies
7.1: Introduction.....................................................................275
7.2: Gigabit Backplane Design Case Study.............................275
7.3: Simulations.......................................................................281
7.4: Measurements...................................................................288
7.5: Recommendations.............................................................298
7.6: Summary...........................................................................299

Part III: Assuring Quality Measurements: Probing and

De-Embedding

Chapter 8: The ABCs of De-embedding............................................303

Eric Bogatin, Signal Integrity Evangelist, Bogatin Enterprises Mike
Resso, Signal Integrity Applications Scientist, Component Test Division,
Keysight Technologies

xiii
 8.1: Introduction...........................................................................303
8.2: Why De-Embedding?............................................................303
8.3: Principles of De-Embedding................................................310
8.4: Obtaining the S-Parameter of the Future.............................323
8.5: Direct Measurement of Fixture S-Parameters....................324
8.6: Building the Fixture S-Parameter by Fitting a.......................335
Model to Measurement Data
8.7: Simulating the Fixture S-Parameter with a 3D......................346
Field Solver
8.8: Summary...............................................................................355

Chapter 9: Differential PCB Structures Using Measured....................357

TRL Calibration and Simulated Structure De-embedding
Heidi Barnes, High-Frequency Device Interface Board Designer,
Verigy, Inc.
Antonio Ciccomancini, Application Engineer, CST of America, Inc.
Mike Resso, Signal Integrity Applications Scientist, Component Test
Division, Keysight Technologies
Ming Tsai, Staff Hardware Development Engineer, Production
Technology Division, Xilinx
9.1: Abstract...........................................................................357
9.2: Introduction.....................................................................357
9.3: Combined TRL Calibration and Simulated Structure......360
De-Embedding for Multi-Mode N-Port Systems
9.4: TRL Calibration Structures and Measurement..................365
Technique
9.5: Simulated Four-Port and 12-Port De-Embedding.................367
Structure
9.6: Device Structure under Test: Coupled and..........................369
Un-Coupled via Pairs
9.7: Verification Using Four-Port Multimode TRL....................371
Calibration
9.8: Demonstration of the Combined TRL Calibration...............374
and Simulated Structure De-Embedding Technique for
Multi-Mode N-Port System
9.9: Summary and Conclusion..................................................377

xiv
Chapter 10: Performance at the DUT: Techniques for.........................381
Evaluating the Performance of an ATE System
Heidi Barnes, Senior Application Consultant, Verigy
José Moreira, Senior Application Consultant, Verigy
Michael Comai, Senior Product Engineer, AMD
Abraham Islas, Senior Product Engineer, AMD
Francisco Tamayo-Broes, Product Development Engineer, AMD
Mike Resso, Signal Integrity Measurement Specialist, Component Test
Division, Keysight Technologies
Antonio Ciccomancini, Application Engineer, CST
Orlando Bell, Vice President, Engineering, GigaTest Labs
Ming Tsai, Principal Engineer, RF Design Group, Amalfi
Semiconductor
10.1: Abstract....................................................................381
10.2: Introduction..............................................................381
10.3: Probing Technology, Interposer Design, and........................383
Mechanical Challenges
10.4: Calibration Techniques......................................................387
10.5: Measuring the Probe and Probe Interposer Adapter.............393
10.6: Test Fixture Performance Measurement.............................397
10.7: Focus Calibration on an ATE System: Measuring.............400
“at the DUT”
10.8: Conclusion..................................................................407

Chapter 11: Frequency Domain Calibration:....................................411

A Practical Approach for the Serial Data Designer
Steven Corey, Principal Engineer, Electro-Optical Product Line,
Tektronix
Eric Bogatin, Signal Integrity Evangelist, Bogatin Enterprises
Dima Smolyansky, Product Marketing Manager, Tektronix
11.1: Abstract...........................................................................411
11.2: Characterization of Serial Channels.................................411
11.3: Calibration Methods..........................................................413
11.4: Frequency Limits from Time Domain Measurements.....416
11.5: Intrinsic Performance Limits.............................................419
11.6: Variation in Typical Fixtures............................................422
11.7: Conclusion................................................................426

xv
Chapter 12: Practical Design and Implementation of Stripline...........427
TRL Calibration Fixtures for 10-Gigabit Interconnect Analysis
Vince Duperron, Design Engineer, Molex
Dave Dunham, Electrical Engineer Manager, Molex
Mike Resso, Product Manager, Signal Integrity Applications, Keysight
Technologies
12.1: Abstract.........................................................................427
12.2: Introduction...................................................................427
12.3: Why Calibrate?..................................................................428
12.4: Linear Two-Port Network Analyzer Measurements........429
12.5: VNA Measurement Errors................................................431
12.6: Vector Network Analyzer with Four Ports......................432
12.7: A Real-World VNA Block Diagram Example:...............433
The Keysight N5230A-245
12.8: TRL Calibration Types.....................................................435
12.9: A Stripline TRL Fixture—A Design Case Study...........436
12.10: The Macro Element View................................................441
12.11: Putting It Together.............................................................444
12.12: The Micro-Half of a TRL Design....................................446
12.13: Validation of TRL Fixtures..............................................450
12.14: Using the Corrected Material Properties..........................451
12.15: Conclusion....................................................................455

Part IV: Jitter and Active Signal Analysis

Chapter 13: Channel Compliance Testing Utilizing Novel..................459

Statistical Eye Methodology
Anthony Sanders, Principal Engineer, Infineon
Mike Resso, Signal Integrity Applications Scientist, Keysight
Technologies
John D’Ambrosia, Manager, Semiconductor Relations, Tyco Electronics
13.1: Abstract.........................................................................459
13.2: Introduction...................................................................460
13.3: StatEye Methodology........................................................464
13.4: Cascading of Channel with Transmitter and Receiver.......471
Return Loss Model
13.5: Design Example Results...................................................483
13.6: Conclusion....................................................................491

xvi
Chapter 14: Characterizing Jitter Performance on High Speed...........493
Digital Devices Using Innovative Sampling Technology
Osvaldo Buccafusca, Development Scientist, Lightwave Division,
Keysight Technologies
Mike Resso, Signal Integrity Applications Scientist, Keysight
Technologies
14.1: Abstract.........................................................................493
14.2: Introduction...................................................................493
14.3: Jitter Measurement............................................................494
14.4: Random Sampling and Precision Time Base....................497
14.5: Future Trends: Optical Sampling......................................504
14.6: Summary.......................................................................505

Chapter 15: Signal Integrity Concerns When Modulating...................507

Laser Transmitters at Gigabit Rates
Stephen Reddy, Senior Design Engineer, Transmission Subsystems
Group, JDS Uniphase
Laurie Taira, Senior Product Engineer, Research and Development,
Delphi Connection Systems
Mike Resso, Signal Integrity Application Scientist, Lightwave Division,
Keysight Technologies

Part V: Analysis of New Technologies

Chapter 16: The Role of Dielectric Constant and Dissipation.............549

Factor Measurements in Multi Gigabit Systems
Eric Bogatin, Signal Integrity Evangelist, Bogatin Enterprises
Shelley Begley, Team Leader, Keysight Technologies
Mike Resso, Signal Integrity Application Scientist, Component Test
Division, Keysight Technologies
16.1: Abstract.........................................................................549
16.2: Introduction...................................................................550
16.3: Dielectric Properties of Laminates....................................551
16.4: Impact of Dielectic Materials in Signal Integration...........552
16.5: Measurement Methods......................................................555
16.6: Split-Post Dielectic Resonator Method..............................559
16.7: Conclusion.....................................................................566

xvii
Chapter 17: Designing Scalable 10G Backplane Interconnect............569
Systems Utilizing Advanced Verification Methodologies
Kevin Grundy, Chief Executive Officer, SiliconPipe
Haw-Jyh Liaw, Director, Systems Engineering, Aeluros
Gary Otonari, Engineering Project Manager, GigaTest Labs
Mike Resso, Signal Integrity Applications Scientist, Keysight
Technologies
17.1: Abstract.........................................................................569
17.2: Approach.......................................................................569
17.3: Current Design Impediments and Approaches..................571
17.4: AE1002 Equalization........................................................575
17.5: Improving the Channel .....................................................576
17.6: Initial Functional Testing..................................................581
17.7: Full System Analysis.........................................................582
17.8: Summary.......................................................................589

Chapter 18: Investigating Microvia Technology for............................593

10 Gbps and Higher Telecommunications Systems
Mike Resso, Signal Integrity Applications Scientist, Keysight
Technologies Thomas Gneiting, Founder, AdMOS Advanced Modeling
Roland Mödinger, Senior Engineer, ERNI Electroapparate GmbH Jason
Roe, Application Engineer, ERNI Electroapparate GmbH
18.1: Abstract...........................................................................593
18.2: Introduction.....................................................................593
18.3: Telecom System Physical Layer Overview......................594
18.4: Signal Integrity and Differential Signaling.....................600
Backplane Data
18.5: Four Port Microvia Measurements....................................605
18.6: Microvia Construction......................................................608
18.7: Modeling and Simulation Case Study...............................613
18.8: Summary and Conclusions................................................618

Chapter 19: ATE Interconnect Performance to 43 Gbps.....................621

Using Advanced PCB Materials
Heidi Barnes, Senior Application Consultant, Verigy
José Moreira, Senior Application Consultant, Verigy
Tom McCarthy, Vice President, Taconic
William Burns, Senior Applications Engineer, Altanova Corporation
Crescencio Gutierrez, Engineering and Research and Development
Manager, Harbor Electronics
Mike Resso, Signal Integrity Applications Scientist, Keysight
Technologies

xviii
 19.1: Abstract............................................................................621
19.2: Introduction......................................................................621
19.3: Dielectic Materials for ATE Test Fixtures.......................624
19.4: The Taconic Fast-Rise Dielectic Materials.......................632
19.5: Experimental Results........................................................633
19.6: Equalization to the Rescue................................................639
19.7: NEXT/FEXT Crosstalk Variations with............................642
PCB Materials
19.8: Dielectric Influence on Complex ATE Test-Fixture..........643
Stack-Up Decisions
19.9: Conclusion........................................................................646

Part VI: Future Technology Trends

Chapter 20: De-Mystifying the 28 Gb/s PCB Channel:...................651

Design to Measurement
Mike Resso, Signal Integrity Applications Scientist, Keysight Technolo-
gies Thomas Gneiting, Founder, AdMOS Advanced Modeling
Roland Mödinger, Senior Engineer, ERNI Electroapparate GmbH Jason
Roe, Application Engineer, ERNI Electroapparate GmbH
20.1: Abstract............................................................................651
20.2: Approach..........................................................................651
20.3: Current Design Impediments and Approaches...................653
20.4: AE 1002 Equalization........................................................655
20.5: Improving the Channel......................................................662
20.6: Initial Functional Testing...................................................669
20.7: Conclusion..........................................................682

Chapter 21: Analysis of Test Coupon Structures for the..............687

Extraction of High Frequency PCB Material Properties
Mike Resso, Signal Integrity Applications Scientist, Keysight Technolo-
gies
Thomas Gneiting, Founder, AdMOS Advanced Modeling
Roland Mödinger, Senior Engineer, ERNI Electroapparate GmbH Jason
Roe, Application Engineer, ERNI Electroapparate GmbH
21.1: Abstract............................................................................687
21.2: Introduction......................................................................687
21.3: Description of the Methodology....................................... 688
21.4: Simulation of the Methodology........................................ 694
21.5: Measurement vs. Simulation............................................. 697
21.6: Conclusion..................................................................698

xix
Chapter 22: Using Microprobing, Modeling and Error Correction......701
Techniques to Optimize Channel Design
Chief Executive Officer, SiliconPipe
Haw-Jyh Liaw, Director, Systems Engineering, Aeluros
Gary Otonari, Engineering Project Manager, GigaTest Labs
Mike Resso, Signal Integrity Applications Scientist, Keysight
Technologies
22.1: Abstract.........................................................................701
22.2: Introduction...................................................................701
22.3: Design Case Study.............................................................714
22.4: Conclusion.....................................................................723

Chapter 23: Characterization of PCB Insertion Loss with a................725

New Calibration Method
Chief Executive Officer, SiliconPipe
Haw-Jyh Liaw, Director, Systems Engineering, Aeluros
Gary Otonari, Engineering Project Manager, GigaTest Labs
Mike Resso, Signal Integrity Applications Scientist, Keysight
Technologies
23.1: Abstract.........................................................................725
23.2: Introduction...................................................................725
23.3: Characterization of PCB insertion loss with new..............729
1xAFR
23.4: Comparisons of different methods in characterizing..........730
PCB insertion loss with simulations
23.5: Comparisons of different methods with measurements.......737
23.6: Considerations on the gating range of 1xAFR method......742
22.7: Conclusion....................................................................745

Author Biographies....................................................................... 749

xx
 Part I

Getting Started:
Introducing TDR and VNA
Techniques and the Power of
S-Parameters
Signal Integrity Characterization Techniques

2
 Chapter 1: Single-Port TDR, TDR/TDT, and Two-Port TDR

Chapter 1

Single-Port TDR, TDR/TDT, and Two-Port TDR:

Interconnect Analysis Is Simplified with
Physical Layer Tools

1.1 Introduction

The time domain reflectometer (TDR) has come a long way since the
early days when it was used to locate faults in cables. Time domain
reflectometry can be used for more than 40 characterization, modeling,
and emulation applications, many of which are illustrated in this
application note series.

If your applications involve signals with rise times shorter than

one nanosecond, transmission line properties of the interconnects
are important. TDR is a versatile tool to provide a window into the
performance of your interconnects to quickly and routinely answer the
three important questions: does my interconnect meet specifications,
will it work in my application, and where do I look to improve its
performance?

The TDR is not just a simple radar station for transmission lines, sending
pulses down the line and looking at the reflections from impedance
discontinuities. It is also an instrument that can directly provide first-order
topology models, S-parameter behavioral models, and with up to four
channels, characterize rise time degradation, interconnect bandwidth,
near- and far-end crosstalk, odd mode, even mode, differential and
common impedance, mode conversion, and the complete differential
channel characterization.

To provide a little order to the wide variety of applications explored in

this signal integrity book, the series is divided into the following three
parts covering four general areas:

• Part 1 (Chapter 1)—Those that use a single-port TDR, those that

3
Signal Integrity Characterization Techniques

use TDR/time domain transmission (TDT), and those that use two-
port TDR.
• Part 2 (Chapter 2)—Those that use four-port TDR or four-port
vector network analyzer (VNA) with physical layer test system
(PLTS).
• Part 3 (Chapter 10)—Those that use advanced signal integrity
measurements and calibration.

The principles of TDR and VNA operation are detailed in other chapters
in this book and references listed in the bibliography. This application
note series concentrates on the valuable information that can be quickly
obtained with simple techniques that can be used to help get the design
right the first time.

1.2 Single-Port TDR

Overview
This section will look at the seven most important applications of one-
port TDR. The first two refer to the complete characterization of a
uniform transmission line, extracting the characteristic impedance and
time delay.

But we can get more than this with specially designed test structures.
We can also get a fundamental, intrinsic property of the transmission
line, the velocity of a signal, and from this, the intrinsic bulk dielectric
constant of the laminate.

When the line is not uniform and has discontinuities, we can build
first-order, topology-based models right from the front screen. If this
is not high-bandwidth enough, we can bring the measured data into a
simulation tool such as Keysight’s Advanced Design System (ADS)
and build very–high-bandwidth models, which can then be used in
simulations to evaluate whether this interconnect might be acceptable in
a specific application.

Finally, we can emulate the final application system’s rise time with
the TDR to directly measure the reflection noise generated by physical
structures in the interconnect and whether they might pose a potential
problem or, equally of value, might be ignored.

4
 Chapter 1: Single-Port TDR, TDR/TDT, and Two-Port TDR

Measuring Characteristic Impedance and Uniformity of

Transmission Lines
Historically, the most common use of the TDR has been to characterize
the electrical properties of a transmission line. For an ideal, lossless
transmission line, there are only two parameters that fully characterize
the interconnect: its characteristic impedance and its time delay. This is
the easiest and most common application for TDR.

The TDR sends a calibrated step edge of roughly 200 mV into the device
under test (DUT). Any changes in the instantaneous impedance the edge
encounters along its path will cause some of this signal to reflect back,
depending on the change in impedance it sees. The constant incident
voltage of 200 mV, plus any reflected voltage, is what is displayed on the
screen of the TDR.

Figure 1.1: Measured TDR Response from a Microstrip Transmission

Line. Top Trace Is the Reflection from the End of the Cable; Bottom Trace
Is the Reflected Signal from the DUT

In Figure 1.1, the bottom line is the measured TDR response when
the DUT is the microstrip trace shown. The first two inches of the

5
Signal Integrity Characterization Techniques

transmission line has a characteristic impedance of roughly 50 Ohms,

while the next four inches of the transmission line has a characteristic
impedance of roughly 40 Ohms. The far end of the line is open.

The voltage displayed on the screen is the total voltage: the incident,
constant 200 mV, plus the reflected voltage. Note on the bottom of the
screen, the vertical voltage scale is 100 mV/div. The top line is the TDR
response for the cable not connected to the transmission line. This defines
the beginning of the cable, which is an open. On the bottom line, at this
instant of time, is the small reflected voltage from the surface-mounted
assembly (SMA) launch, followed by the roughly 50 Ohm section of
the line, and about one division later, the small drop in voltage from the
lower-impedance second half of the transmission line.

Contained in this reflected signal is the information about the impedance

profile of the transmission line. We could read the voltages off the front
screen and use pencil and paper to back out the impedance of the line,
or we can take advantage of some of the built-in features of this TDR.

We can use the two markers, which will automatically perform the
calculations to back out the instantaneous impedance from the measured
data. There are clearly two regions of relatively uniform impedance on
this transmission line. We move the markers so that one is in each region,
as shown in Figure 1.2, and then we can read the impedance of each
region from the screen.

6
 Chapter 1: Single-Port TDR, TDR/TDT, and Two-Port TDR

Figure 1.2: Using Markers to Measure the Characteristic Impedance of a

Transmission Line

The impedance of the first region, read from the solid-line marker, is
48.3 Ohms. The impedance in the second region, read from the dotted-
line marker, is 37.7 Ohms. The nominal design impedances were 50
Ohms and 40 Ohms, so we see that actual and fabricated impedances are
off by about 3.5 and 6 percent, respectively.

The one caveat when using markers is to watch out for masking
effects. The impedance read by the marker can be interpreted as the
instantaneous impedance of the transmission line at the location of the
marker, as long as it is the first interface, or there have been only small
impedance discontinuities up to the location of the marker. This feature
makes extracting the instantaneous impedance of a uniform transmission
line almost trivial. In addition, we can see that the impedance in each
region is relatively uniform, as there is little deviation in the reflected
voltage up and down the line segments.

In addition to using the marker to identify the specific instantaneous

impedance of the transmission line, we can also convert the vertical
voltage scale into an impedance scale.

7
Signal Integrity Characterization Techniques

Figure 1.3: The Advanced Settings Function Can Adjust the Vertical Scale
to Display the Impedance Directly

By selecting Time Domain Displays, then Ohms, then new chart, we can
choose to display T11 in ohms to see the impedance profile as shown in
Figure 1.3. When we select the Ohms scale, the TDR will convert every
point of the reflected voltage into an equivalent instantaneous impedance.

Effectively, the TDR takes each measured voltage point, subtracts 200
mV to get the reflected voltage, then takes the ratio of this voltage to the
200 mV of incident voltage to get the reflection coefficient, and from the
reflection coefficient, uses the simple relationship: Z = 50 Ω x (1 + rho)/
(1 - rho) to calculate the instantaneous impedance of each point. Finally,
this extracted instantaneous impedance is plotted on the screen.

The offset and scale settings, now calibrated in Ohms, can be used to
adjust the scale for our application.

8
 Chapter 1: Single-Port TDR, TDR/TDT, and Two-Port TDR

Figure 1.4 is the same TDR data for this two-segment transmission
line but now with the instantaneous impedance displayed directly on
the vertical scale. In this case, the scale is 10 Ohms/div with the center
location set to 50 Ohms. On this scale we can literally read off the screen
the impedance of the first section as about 48 Ohms and the impedance
of the second section as about 38 Ohms.

Figure 1.4: The Same Transmission Line Displayed on the Impedance

Scale at 10 Ohms/div, with 50 Ohms in the Center

This scale setting allows a direct and effortless graphical display of the
impedance profile of a transmission line, with the one caveat that we are
assuming all the measured voltage coming back to the TDR is due to
reflections from impedance discontinuities. This is a good assumption as
long as the impedance changes up to each point are small.

It looks like, for this transmission line, the impedance of the first section
is decreasing slightly down the line, while the impedance profile of the
second section is mostly constant. We can use this technique to evaluate
how uniform the impedance of a transmission line is.

9
Signal Integrity Characterization Techniques

Figure 1.5: High-Resolution TDR Profile of a Nominally Uniform

Transmission Line, at 2 Ohms/div and 50 Ohms in the Center of the Screen

Figure 1.5 shows the measured TDR response of a nominally uniform

transmission line on an expanded scale of 2 Ohms/div. The impedance at
the center of the screen is set at 50 Ohms. This scale information can be
read next to the channel 1 button of the screen.

The large peak at the beginning of the line is the inductive discontinuity
of the SMA launch that, on this high-resolution scale, looks huge. At 2
Ohms/div on the vertical scale, it looks like this uniform transmission
line is not so uniform. It appears to have a variation of as much as 1 Ohm
from the beginning to the end of the line. This is roughly 2 percent.

Is this variation real, or could it be some sort of artifact? There are two
important artifacts that might give rise to this sort of behavior. It could
be there is rise-time degradation in the incident signal. It may not be
perfectly flat, like an ideal Gaussian step edge. After all, the reflected
signal displayed on the TDR is really the reflection of the incident signal.
If the incident signal has a long tail, we will see this long tail in the
TDR response and may mistakenly interpret this as an impedance profile
variation.

10
 Chapter 1: Single-Port TDR, TDR/TDT, and Two-Port TDR

One way around this problem is to use the calibrated response feature of
the DCA 86100C TDR, which is being done in this case.

Other sources of artifact can be either distributed series resistance in

the trace or distributed shunt conductance in the trace due to the lossy
nature of the line. The series resistance will cause the reflected voltage
to increase down the line, while the shunt conductance will cause the
reflected TDR response to decrease down the line, as in this case.

One way to evaluate whether an impedance profile is really showing a

variation in the instantaneous impedance of the transmission line or an
artifact is to measure the TDR response of the line from both ends. If it
is real, we should see the slope of the response change, depending on
which end of the line we launch from. If it is one of the two artifacts, the
response will look the same on the screen, independent of which end we
launch from.

Figure 1.6: High-Resolution TDR Response from Each End of the Same
Uniform Transmission Line, Verifying the Impedance Variation Is Real

11
Signal Integrity Characterization Techniques

Figure 1.6 shows the measured TDR response launching from each end
of the line where the scale is 2 Ohms/div in both cases.

The TDR from left end launch line shows the left side of the line is
the higher impedance. While the TDR from right end launch line also
confirms that the impedance of the trace is higher on the left side. This
variation in the instantaneous impedance is confirmed to be real and is
not due to the series resistance, shunt conductance, or non-ideal step
edge. Using the technique of comparing the launches from both ends,
we can unambiguously identify real, nonuniform impedance effects in a
transmission line.

In this example, the microstrip is showing a variation of about half a

division, or 1 Ohm out of 50 Ohms, or 2 percent, from one end to the
other. This could be due to a variation in the laminate thickness, the
slight drift in the alignment of the trace width over a fiber bundle in the
glass weave, or a variation in the etching of the line due to photo resist
developer variation across the board.

By measuring the variation in other lines across the board or inspecting

the dimensions of the board, the root cause might be identified and the
process stabilized.

Measuring Time Delay of a Transmission Line

The second important property of a transmission line is the time delay
from one end to the other. This can also be measured directly from the
screen of the TDR using markers. However, to get an accurate measure
of the time delay, we need to know the starting point of the transmission
line.

By removing the DUT and recording the TDR response from the open
end of the cable, we can use this as a reference to define the beginning of
the line. This is the top line in Figure 1.7. When we reconnect the DUT
and record the TDR response, we see the reflection from the open at the
far end of the transmission line, just visible at the far right edge of the
screen.

12
 Chapter 1: Single-Port TDR, TDR/TDT, and Two-Port TDR

Figure 1.7: TDR Response of a Uniform Six-Inch Transmission Line

Open at the Far End

The total round-trip time delay is the time interval from the beginning
of the reflection from the open end of the cable to the reflection from the
open far end of the DUT. To increase the accuracy, we use the time from
the midpoint of the two open responses. This can be measured simply
and easily using the vertical markers directly from the screen.

13
Signal Integrity Characterization Techniques

Figure 1.8: TDR Response of the Reference Open and Uniform Six-Inch
Transmission Line, with Markers Showing the Beginning and End of the
Traces

Using the marker buttons below the screen, we can position the markers
in Figure 1.8 so that they define the midpoint-to-midpoint distances. We
can read off the screen that the total time delay is 1.87 ns. This is the
round-trip time delay. The one-way time delay is half of this, or .935 ns.
This is the time delay (TD) of the transmission line.

From the physical length of the transmission line, six inches, and the
time delay, 0.935 ns, we can also calculate the speed of the signal down
this transmission line. The speed is 6 in/0.935 ns = 6.42 in/ns. This is
an intrinsic property of the transmission line and would be true for any
transmission line of the same width built on this layer of the board,
independent of the length of the line.

One of the artifacts in this measurement is the uncertainty of how much

of the total TD is due to the connector at the front of the line. Is the open
reference really the beginning of the line, or is there some contribution
to the launch into the transmission line of the circuit board? We can take

14
 Chapter 1: Single-Port TDR, TDR/TDT, and Two-Port TDR

advantage of a simple test feature to get around this artifact and extract a
more accurate value for the speed of a signal on the trace.

This trick is useful only if we have the option of designing the test line to
aid in the characterization of the circuit board and each particular layer.
The secret is to add small imperfections to the line such as reference pads
at two locations with a known separation.

Figure 1.9: TDR Response of a Uniform Transmission Line with

Two Small Reference Pads Located on Four-Inch Centers

Figure 1.9 shows an example of a six-inch-long transmission line with two

reference pads (in close-up), located with a center spacing of four inches.
These pads can be easily detected with the TDR. The TDR response is
displayed on a scale with 2 Ohms/div. This is a high-sensitivity scale.
On the far left, it shows the beginning of the line with a few ripples from
the SMA launch. About two divisions from the beginning is the dip from
the first pad, which acts as a small capacitive load, a lower impedance.
Some time later, the TDR signal shows the response from the second
reference pad.

15
Signal Integrity Characterization Techniques

Accurate Measurement of Signal Speed in a Transmission Line

The time difference between these two negative dips is the round-trip
time difference between the pads separated by four inches. By measuring
this time delay from the screen, we can get an accurate measure of the
speed of the signal, independent of the nature of the launch into the
transmission line.

We can measure the time delay between the dips using the onscreen
markers. By aligning each marker with the center of the dip, we can
measure this location within a few picoseconds’ accuracy. We can see
from the screen in Figure 1.10 that the round-trip time delay is 1.238 ns.
From this round-trip delay, we can calculate the one-way time delay as
half this, or 0.619 ns.

Figure 1.10: TDR Response from a Microstrip with Two Reference Pads
Using Markers to Measure the Round-Trip Time Delay

Given the physical distance between the two reference pads as four
inches, the speed of the signal down the microstrip can be calculated as
4 in/0.619 ns = 6.46 in/ns. This is very close to the 6.42 in/ns calculated
as the speed of the signal using the end-toned method.

16
 Chapter 1: Single-Port TDR, TDR/TDT, and Two-Port TDR

Using this value of the speed of the signal, we can extract the laminate’s
dielectric properties.

Extracting the Bulk Dielectric Constant of the Laminate

The speed of the signal down a transmission line is directly related to the
dielectric constant the signal sees. In a stripline structure, such as shown
in Figure 1.11, the signal sees a uniform, homogeneous material with
a composite dielectric constant that is made up of a combination of the
resin dielectric constant and the glass weave dielectric constant. Small
variations in the local relative combination can affect the local dielectric
constant, which is an important source of skew between adjacent lines in
a differential pair.

Figure 1.11: A Stripline Construction and Extracting the Bulk

Dielectric Constant

From a measurement of the speed of a signal down a stripline transmission

line, the effective dielectric constant the signal sees, Dk, can be extracted
using the simple relationship shown. The 11.803 number is the speed of
light in air, in the units of inches/ns.

However, in a microstrip, the effective dielectric constant the signal sees

is not the bulk value of the laminate.

17
Signal Integrity Characterization Techniques

In a microstrip, some of the electric field lines are in the bulk laminate,
and see the laminate composite dielectric constant, but some of the field
lines, as shown in Figure 1.12, are in the air, with a dielectric constant of
one. The signal sees a composite of these two materials, which creates an
effective dielectric constant, Dkeff. It is this value that affects the signal
speed and can be extracted from the measured speed of the signal.

Figure 1.12: Effective Dielectric Constant in Microstrip

In this example, the speed is 6.46 in/ns. The extracted effective dielectric
constant would be 3.34. This is unfortunately not a very useful number.
It is not the bulk dielectric constant of the laminate. We cannot use this
value of the effective dielectric constant in a field solver or approximation
to help us calculate the impedance of any other geometries, for example.
We really need to convert the effective dielectric constant into the actual
bulk dielectric constant.

This conversion is related to the precise nature of the electric field lines,
and what fraction is in the air and the bulk laminate. It also depends very
much on the cross-section geometry of the microstrip. The only way to
convert the extracted, effective dielectric constant into the bulk laminate
dielectric constant is to use a 2D field solver.

18
 Chapter 1: Single-Port TDR, TDR/TDT, and Two-Port TDR

Figure 1.13: Using a Field Solver to Back out the Bulk Dielectric
Constant from the Effective Dielectric Constant

In Figure 1.13, a 2D field solver is used to calculate the effective

dielectric constant for different bulk values, using the same geometry
as the trace that is measured. We set up the field solver with the cross-
section information about the specific microstrip that was measured
and use the field solver to calculate the effective dielectric constant for
different bulk dielectric constant values.

When we plot up the bulk dielectric constant versus the effective

dielectric constant, we get a relatively straight line, as shown in Figure
1.13. We use this curve to back out the bulk dielectric constant, given
the effective value of 3.34 that was measured. This analysis gives a bulk
dielectric constant for this laminate of 4.48.

The TDR enables the measurement of the effective dielectric constant,

while the 2D field solver enables the conversion of the effective dielectric
constant into the bulk dielectric constant.

19
Signal Integrity Characterization Techniques

Building a Model of a Discontinuity Such as a Corner, Test Pad, Gap

in the Return Path, SMA Launch, or Terminating Resistor
Extracting a Model for Capacitive Discontinuities
Not all interconnect structures are uniform transmission lines. As much
as we might try to eliminate them, there will often be discontinuities that
are unavoidable. For example, test pads, component leads, 90-degree
corners, gaps in the return path, or even engineering change wires will
all create discontinuities. These structures, by their nature, are non-
uniform and often difficult to calculate other than with a 3D field solver.
Sometimes, the quickest way to evaluate their impedance is to build a
structure and measure it.

From the measured response, we can empirically evaluate the impact

on the signal if we match the TDR’s rise time to the rise time of the
application. We could then directly measure off the screen of the TDR
the amount of reflected voltage noise we might see in the system.
Alternatively, we could use the TDR to extract a simple, first-order
model for the structure and use this model in a system-level simulation
to evaluate the impact of the discontinuity. Finally, if we need more
accuracy or a higher-bandwidth model than what we can get directly
from the screen, we can take the measured data from the TDR and bring
it into a modeling and simulation tool such as SPICE or ADS to fit a
more accurate model. These processes are illustrated in this section.

20
 Chapter 1: Single-Port TDR, TDR/TDT, and Two-Port TDR

Figure 1.14: TDR Response from a Uniform Transmission Line

Having a Small Test Pad

Let us start with a simple test pad on an otherwise uniform line, as show
in Figure 1.14. The TDR response is shown as the yellow line on the
screen, displayed in an Ohms scale, with 2 Ohms/div. The small dip near
the beginning of the line is due to the SMA launch. The large dip about
three divisions from the left edge is from the test pad.

On this scale, the reflected signal from the small test pad looks huge, but
is a discontinuity of only 4.5 divisions or about nine Ohms. This can be
interpreted as the instantaneous impedance a signal would see, if it had
the rise time of the TDR, in this case, about 40 ps. Since this test pad
is not a uniform transmission line, the instantaneous impedance is not
related to a characteristic impedance, and the impedance a signal would
see is going to depend on the rise time of the signal. We can use the TDR
to directly emulate any rise time from as fast as 20 ps up to longer than
one nanosecond, to directly evaluate the impact of the discontinuity on
the system rise time.

21
Signal Integrity Characterization Techniques

Using the built in calibration feature of the DCA 86100C, we can change
the effective rise time of the stimulus and directly display the response
from this small discontinuity. The structure is the same, and the scale is
the same for each of the four rise times of 40, 100, 200, and 500 ps.

Figure 1.15: TDR Response for a Uniform Transmission Line with a

Small Test Pad, at Four Rise Times of 40, 100, 200, and 500 ps

Figure 1.15 clearly shows that the instantaneous impedance a signal

would see encountering this test pad is strongly dependent on the rise
time of the signal. If the rise time were 40 ps, the signal would see an
impedance discontinuity of about nine Ohms. At 100 ps, this is only
about five Ohms; at 200 ps, it is 2.5 Ohms; and at 500 ps, it is less than
one Ohm, hardly noticeable to the signal. Based on the noise budget
allocated for discontinuities, we could determine the shortest rise time
at which this discontinuity would begin to cause problems or could be
ignored.

22
 Chapter 1: Single-Port TDR, TDR/TDT, and Two-Port TDR

For example, if three Ohm discontinuities were allowable, this particular

test pad could be used for rise times as short as 250 ps. Much below this,
and the impact might be felt. The way to know for sure would be to build
a model for the discontinuity and use it in a simulation.

By inspection, the simplest model for this discontinuity is a single lumped

capacitor. At 40 ps rise time, the TDR response is close to that from
an ideal lumped capacitor. We can use the built-in “excess reactance”
feature to build a model and extract the parameter values directly from
the screen using markers.

The excess reactance feature built into the DCA 86100C will model
the DUT as a uniform transmission line having a single discontinuity—
either a lumped inductor or lumped capacitor. The software will use the
position of the two vertical markers to define the region of the response
where the capacitance or inductance will be extracted.

To use this feature, position the markers on either side of the discontinuity
and read the amount of capacitance or inductance from the “excess
reactance” value on the screen. One hint in using this feature is to
position the markers so that they have roughly the same impedance value
on either side of the discontinuity. It does not matter what the vertical
scale is when the excess reactance function is used.

23
Signal Integrity Characterization Techniques

Figure 1.16: Using the Excess Resistance Feature to Extract the

Capacitance of a Test Pad

In Figure 1.16, the markers are used to extract the capacitance of the test
pad. The model we are assuming is a single lumped capacitor. The value
of this capacitance is read off the screen as 236 fF. This capacitance,
plus the impedance of the uniform part of the line, 49 Ohms, provides a
complete model for this transmission line structure.

24
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