Computer

ADITYA COLLEGE OF ENGINEERING

(AUTONOMOUS)
Valasapalle (P), Punganur Road – 517325, Madanapalle

DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING

COMPUTER
ORGANIZATI
ON

Prepared by : Mr. Amareswara Kumar Archakam, M. Tech

Assistant Professor, Dept., of ECE

Mr. Amareswara Kumar Archakam Page 1

Computer
Unit – V (10 Lectures)

Mr. Amareswara Kumar Archakam Page 2

Computer

UNIT - V SYLLUBUS
BASIC STRUCTURE OF COMPUTERS: Accessing I/O devices, Programmed Input/output,
Interrupts, Direct Memory Access, Buses, Standard I/O Interfaces (PCI, SCSI and USB),

Book: Carl Hamacher, Zvonks Vranesic, SafeaZaky (2002), Computer Organization, 5th
edition, McGraw Hill: Chapter-4 Pages: 203 - 290

Mr. Amareswara Kumar Archakam Page 3

Computer

Introduction :

One of the basic features of a computer is its ability to exchange data with other devices.
Human - Computer communication :
This communication capability enables a human operator to use a keyboard and a
display screen to process text and graphics.
Compute - Computer communication :
We make extensive use of computers to communicate with other computers over the
Internet and access information around the globe.
Compute - Devices communication :
In other applications, computers are less visible but equally important. They are
an integral part of home appliances, manufacturing equipment, transportation systems,
banking, and point-of- sale terminals. In such applications, input to a computer may come
from a sensor switch, a digital camera, a microphone, or a fire alarm. Output may be a
sound signal sent to a speaker, or a digitally coded command that changes the speed of a
motor, opens a valve, or causes a robot to move in a specified manner.

Topic - 1 : ACCESSING I/O DEVICES & PROGRAMMED INPUT/OUTPUT

A simple arrangement to connect I/O devices to a computer is to use a single bus

arrangement shown in figure 1 . The bus enables all the devices connected to it to
exchange information. Typically, it consists of three sets of lines used to carry address,
data, and control signals . Each I/O device is assigned a unique set of addresses. When the
processor places a particular address on the address line, the device that recognizes this
address responds to the commands issued on the control lines . The processor requests
either a read or a write operation, and the requested data are transferred over the data
lines, when I/O devices and the memory share the same address space, the arrangement
is called memory-mapped I/O.

Figure - 1 : A single Bus structure

Mr. Amareswara Kumar Archakam Page 4

Computer
With memory-mapped I/O, any machine instruction that can access memory can
be used to transfer data to or from an I/O device . For example, if DATAIN is the address
of the input buffer associated with the keyboard, the instruction

Move DATAIN, R0
Reads the data from DATAIN and stores them into processor register R0.
Similarly, the instruction
Move R0, DATAOUT
Sends the contents of register R0 to location DATAOUT, which may be the output
data buffer of a display unit or a printer.
Most computer systems use memory-mapped I/O . some processors have special
In and Out instructions to perform I/O transfers.
Figure 2 illustrates the hardware required to connect an I/O device to the bus. The
address decoder enables the device to recognize its address when this address appears
on the address lines. The data register holds the data being transferred to or from the
processor. The status register contains information relevant to the operation of the I/O
device. Both the data and status registers are connected to the data bus and assigned
unique addresses. The address decoder, the data and status registers, and the control
circuitry required to coordinate I/O transfers constitute the device’s interface circuit.

Figure - 2 : I/O interface for an input device

program-controlled I/O, in which the processor repeatedly checks a status flag to

achieve the required synchronization between the processor and an input or output device .
We say that the processor polls the device .
There are two other commonly used mechanisms for implementing I/O operations:
(a) interrupts
In the case of interrupts, synchronization is achieved by having the I/O device send a
special signal over the bus whenever it is ready for a data transfer operation.
(b)direct memory access.

Mr. Amareswara Kumar Archakam Page 5

Computer

Direct memory access is a technique used for high-speed I/O devices. It involves
having the device interface transfer data directly to or from the memory, without continuous
involvement by the processor.

Topic - 2 : INTERRUPTS

In the programmed I/O transfer, the program enters a wait loop in which it
repeatedly tests the device status. During this period, the processor is not performing
any useful computation. There are many situations where other tasks can be performed
while waiting for an I/O device to become ready. To allow this to happen, we can arrange
for the I/O device to alert the processor when it becomes ready. It can do so by sending a
hardware signal called an interrupt request to the processor.
Since the processor is no longer required to continuously poll the status of I/O
devices, it can use the waiting period to perform other useful tasks. Indeed, by using
interrupts, such waiting periods can ideally be eliminated. The routine executed in
response to an interrupt request is called the interrupt-service routine, which is the
PRINT routine in our example.

Figure - 3 : Transfer of control through the use interrupts

Assume that an interrupt request arrives during execution of instruction i in

Figure. The processor first completes execution of instruction i. Then, it loads the
program counter with the address of the first instruction of the interrupt-service routine.
For the time being, let us assume that this address is hardwired in the processor.
After execution of the interrupt-service routine, the processor returns to instruction i + 1.
Therefore, when an interrupt occurs, the current contents of the PC, which point to
instruction i + 1, must be put in temporary storage in a known location.

Mr. Amareswara Kumar Archakam Page 6

Computer

A Return-from-interrupt instruction at the end of the interrupt-service routine

reloads the PC from that temporary storage location, causing execution to resume at
instruction i + 1. The return address must be saved either in a designated general-
purpose register or on the processor stack.
It should note that as part of handling interrupts, the processor must inform the
device that its request has been recognized so that it may remove its interrupt-request
signal. This may be accomplished by means of a special control signal on the bus.
Before starting execution of the interrupt-service routine, any information that
may be altered during the execution of that routine must be saved. This information must
be restored before execution of the interrupt program is resumed. In this way, the
original program can continue execution without being affected in any way by the
interruption, except for the time delay.
An interrupt is more than a simple mechanism for coordinating I/O transfers. In a
general sense, interrupts enable transfer of control from one program to another to be
initiated by an event external to the computer. Execution of the interrupted program
resumes after the execution of the interrupt-service routine has been completed. The
concept of interrupts is used in operating systems.

Enabling and Disabling Interrupts

In a computer, the programmer have facilities to get control over the events that
take place during program execution. The arrival of an interrupt request from an external
device causes the processor to suspend the execution of one program and start the
execution of another. Because interrupts can arrive at any time, they may alter the
sequence of events from that envisaged by the programmer. Hence, the interruption of
program execution must be carefully controlled. A fundamental facility found in all
computers is the ability to enable and disable such interruptions as desired.

let us summarize the sequence of events involved in handling an interrupt request

from a single device. Assuming that interrupts are enabled in both the processor and the
device, the following is a typical scenario:
1. The device raises an interrupt request.
2. The processor interrupts the program currently being executed and saves the contents of
the PC and PS registers.
3. Interrupts are disabled by clearing the IE bit in the PS to 0.
4. The action requested by the interrupt is performed by the interrupt-service routine,
during which time the device is informed that its request has been recognized, and in
response, it deactivates the interrupt-request signal.

Mr. Amareswara Kumar Archakam Page 7

Computer
5. Upon completion of the interrupt-service routine, the saved contents of the PC and
PS registers are restored (enabling interrupts by setting the IE bit to 1), and execution
of the interrupted program is resumed.

Topic - 3 : DIRECT MEMORY ACCESS

An instruction to transfer input or output data is executed only after the processor
determines that the I/O device is ready, either by polling its status register or by waiting for
an interrupt request. Due to this considerable overhead is incurred, because several
program instructions must be executed involving many memory accesses for each data word
transferred. When transferring a block of data, instructions are needed to increment the
memory address and keep track of the word count. The use of interrupts involves
operating system routines causes additional overhead to save and restore processor
registers, the program counter, and other state information.
An alternative approach is used to transfer blocks of data directly between the
main memory and I/O devices, such as disks. A special control unit is provided to manage
the transfer, without continuous intervention by the processor. This approach is called
direct memory access, or DMA.
The unit that controls DMA transfers is referred to as a DMA controller. It may be
part of the I/O device interface, or it may be a separate unit shared by a number of I/O
devices. The DMA controller performs the functions that would normally be carried out
by the processor when accessing the main memory. For each word transferred, it
provides the memory address and generates all the control signals needed. It increments
the memory address for successive words and keeps track of the number of transfers.
Although a DMA controller transfers data without intervention by the processor,
its operation must be under the control of a program executed by the processor, usually
an operating system routine. To initiate the transfer of a block of words, the processor sends
to the DMA controller the starting address, the number of words in the block, and the
direction of the transfer. The DMA controller then proceeds to perform the requested
operation. When the entire block has been transferred, it informs the processor by raising
an interrupt.
To start a DMA transfer of a block of data from the main memory to one of the
disks, an OS routine writes the address and word count information into the registers of the
disk controller. The DMA controller proceeds independently to implement the specified
operation. When the transfer is completed, this fact is recorded in the status and control
register of the DMA channel by setting the Done bit. At the same time, if the IE bit is set, the
controller sends an interrupt request to the processor and sets the IRQ bit. The status

Mr. Amareswara Kumar Archakam Page 8

Computer
register may also be used to record other information, such as whether the transfer took
place correctly or errors occurred.

Figure 4 : Use of a DMA controller in a computer system

Cycle Stealing
 Requests by DMA devices for using the bus are having higher priority than
processor requests
 Top priority is given to high speed peripherals such as ,
□ Disk
□ High speed Network Interface and Graphics display device.
 Since the processor originates most memory access cycles, the DMA controller can
be said to steal the memory cycles from the processor.
 This interviewing technique is called Cycle stealing.
Burst Mode
The DMA controller may be given exclusive access to the main memory to transfer a
block of data without interruption. This is known as Burst/Block Mode
Bus Master
The device that is allowed to initiate data transfers on the bus at any given time is called the
bus master.
Bus Arbitration :
It is the process by which the next device to become the bus master is selected and
the bus mastership is transferred to it.

Mr. Amareswara Kumar Archakam Page 9

Computer
Types:
There are 2 approaches to bus arbitration. They are,

□ Centralized arbitration ( A single bus arbiter performs arbitration)

□ Distributed arbitration (all devices participate in the selection of next bus master).
Centralized Arbitration:

Here the processor is the bus master and it may grants bus mastership to one of its
DMA controller. A DMA controller indicates that it needs to become the bus master by
activating the Bus Request line (BR) which is an open drain line. The signal on BR is the
logical OR of the bus request from all devices connected to it. When BR is activated the
processor activates the Bus Grant Signal (BGI) and indicated the DMA controller that they
may use the bus when it becomes free. This signal is connected to all devices using a daisy
chain arrangement. If DMA requests the bus, it blocks the propagation of Grant Signal to
other devices and it indicates to all devices that it is using the bus by activating open
collector line, Bus Busy (BBSY).

Figure 5 : A simple arrangement for bus arbitration using daisy chain

The timing diagram shows the sequence of events for the devices connected to the
processor is shown. DMA controller 2 requests and acquires bus mastership and later
releases the bus. During its tenure as bus master, it may perform one or more data transfer.
After it releases the bus, the processor resources bus mastership.

Figure 6 : Sequence of signals during transfer of bus mastership

Mr. Amareswara Kumar Archakam Page

 Computer
Distributed Arbitration:
It means that all devices waiting to use the bus have equal responsibility in carrying
out the arbitration process. Each device on the bus is assigned a 4 bit id. When one or more
devices request the bus, they assert the Start-Arbitration signal & place their 4 bit ID
number on four open collector lines, ARB0 to ARB3. A winner is selected as a result of the
interaction among the signals transmitted over these lines. The net outcome is that the
code on the four lines represents the request that has the highest ID number. The drivers
are of open collector type. Hence, if the i/p to one driver is equal to 1, the i/p to another
driver connected to the same bus line is equal to 0 (i.e., bus the is in low-voltage state).

Figure 7 : A distributed arbitration scheme

Topic - 4 : BUSES
The bus shown in Figure (a) is a simple structure that implements the
interconnection network. Only one source/destination pair of units can use this bus to
transfer data at any one time. The bus consists of three sets of lines used to carry address,
data, and control signals. I/O device interfaces are connected to these lines, as shown in
Figure (b) for an input device. Each I/O device is assigned a unique set of addresses for the
registers in its interface.

Mr. Amareswara Kumar Archakam Page

Computer
When the processor places a particular address on the address lines, it is examined
by the address decoders of all devices on the bus. The device that recognizes this address
responds to the commands issued on the control lines.

Synchronous Bus :

Mr. Amareswara Kumar Archakam Page

 Computer
Asynchronous Bus :

Topic - 5 : INTERFACE CIRCUITS

The I/O interface of a device consists of the circuitry needed to connect that device
to the bus. On one side of the interface are the bus lines for address, data, and control. On
the other side are the connections needed to transfer data between the interface and the
I/O device. This side is called a port, and it can be either a parallel or a serial port. A parallel
port transfers multiple bits of data simultaneously to or from the device. A serial port sends
and receives data one bit at a time. Communication with the processor is the same for both
formats; the conversion from a parallel to a serial format and vice versa takes place inside
the interface circuit.
Before we present specific circuit examples, let us recall the functions of an I/O
interface. An I/O interface does the following:
1. Provides a register for temporary storage of data
2. Includes a status register containing status information that can be accessed by
the processor
Mr. Amareswara Kumar Archakam Page
 Computer
3. Includes a control register that holds the information governing the behaviour of
the interface
4. Contains address-decoding circuitry to determine when it is being addressed by
the processor
5. Generates the required timing signals
6. Performs any format conversion that may be necessary to transfer data between
the processor and the I/O device, such as parallel-to-serial conversion in the
case of a serial port
Parallel Interface :
We describe an interface circuit for an 8-bit input port that can be used for
connecting a simple input device, such as a keyboard. Then, we describe an interface circuit
for an 8-bit output port, which can be used with an output device such as a display. We
assume that these interface circuits are connected to a 32-bit processor that uses memory-
mapped I/O and the asynchronous bus protocol depicted.

Input Interface
Figure shows a circuit that can be used to connect a keyboard to a processor. The
registers in this circuit correspond to those given in Figure. Assume that interrupts are not
used, so there is no need for a control register. There are only two registers: a data register,
KBD_DATA, and a status register, KBD_STATUS. The latter contains the keyboard status flag,
KIN.

Encoder :

A typical keyboard consists of mechanical switches that are normally open. When a
key is pressed, its switch closes and establishes a path for an electrical signal. This signal is
detected by an encoder circuit that generates the ASCII code for the corresponding character.

Debouncing Circuit :
Mr. Amareswara Kumar Archakam Page
Computer
A difficulty with such mechanical push button switches is that the contacts bounce
when a key is pressed, resulting in the electrical connection being made then broken several
times before the switch settles in the closed position. Although bouncing may last only one
or two milliseconds, this is long enough for the computer to erroneously interpret a single
pressing of a key as the key being pressed and released several times. The effect of bouncing
can be eliminated using a simple debouncing circuit, which could be part of the keyboard
hardware or may be incorporated in the encoder circuit.
The output of the encoder in Figure consists of one byte of data representing the
encoded character and one control signal called Valid. When a key is pressed, the Valid
signal changes from 0 to 1, causing the ASCII code of the corresponding character to be
loaded into the KBD_DATA register and the status flag KIN to be set to 1. The status flag is
cleared to 0 when the processor reads the contents of the KBD_DATA register. The interface
circuit is shown connected to an asynchronous bus on which transfers are controlled by the
handshake signals Master-ready and Slave-ready, as in Figure. The bus has one other
control line, R/W, which indicates a Read operation when equal to 1.

Output Interface

Let us now consider the output interface shown in Figure, which can be used to
connect an output device such as a display. We have assumed that the display uses two
handshake signals, New-data and Ready, in a manner similar to the handshake between the
bus signals Master-ready and Slave-ready. When the display is ready to accept a character,
it asserts its Ready signal, which causes the DOUT flag in the DISP_STATUS register to be set
to 1. When the I/O routine checks DOUT and finds it equal to 1, it sends a character to
DISP_DATA. This clears the DOUT flag to 0 and sets the New-data signal to 1. In response,
the display returns Ready to 0 and accepts and displays the character in DISP_DATA. When
it is ready to receive another character, it asserts Ready again, and the cycle repeats.
Figure shows an implementation of this interface. Its operation is similar to that of
the input interface of Figure 7.11, except that it responds to both Read and Write
operations. A Write operation in which A2 = 0 loads a byte of data into register DISP_DATA.
A Read operation in which A2 = 1 reads the contents of the status register DISP_STATUS. In
this case, only the DOUT flag, which is bit b2 of the status register, is sent by the interface.
The remaining bits of DISP_STATUS are not used. The state of the status flag is determined
by the handshake control circuit.

Mr. Amareswara Kumar Archakam Page

Computer

Serial Interface :

A serial interface is used to connect the processor to I/O devices that transmit data
one bit at a time. Data are transferred in a bit-serial fashion on the device side and in a bit-
parallel fashion on the processor side. The transformation between the parallel and serial
formats is achieved with shift registers that have parallel access capability. A block diagram
of a typical serial interface is shown in Figure. The input shift register accepts bit-serial
input from the I/O device.

When all 8 bits of data have been received, the contents of this shift register are
loaded in parallel into the DATAIN register. Similarly, output data in the DATAOUT register
are transferred to the output shift register, from which the bits are shifted out and sent to
the I/O device.

Mr. Amareswara Kumar Archakam Page

Computer
The part of the interface that deals with the bus is the same as in the parallel
interface described earlier. Two status flags, which we will refer to as SIN and SOUT, are
maintained by the Status and control block. The SIN flag is set to 1 when new data are
loaded into DATAIN from the shift register, and cleared to 0 when these data are read by the
processor. The SOUT flag indicates whether the DATAOUT register is available. It is cleared
to 0 when the processor writes new data into DATAOUT and set to 1 when data are
transferred from DATAOUT to the output shift register. The double buffering used in the
input and output paths in Figure is important.
It is possible to implement DATAIN and DATAOUT themselves as shift registers, thus
obviating the need for separate shift registers. However, this would impose awkward
restrictions on the operation of the I/O device. After receiving one character from the serial
line, the interface would not be able to start receiving the next character until the processor
reads the contents of DATAIN. Thus, a pause would be needed between two characters to
give the processor time to read the input data.

Topic - 6 : STANDARD I/O INTERFACES

A typical desktop or notebook computer has several ports that can be used to
connect I/O devices, such as a mouse, a memory key, or a disk drive. Standard interfaces
have been developed to enable I/O devices to use interfaces that are independent of any
particular processor. For example, a memory key that has a USB connector can be used with
any computer that has a USB port.
PCI Bus :
The PCI (Peripheral Component Interconnect) bus was developed as a low-cost,
processor-independent bus. It is housed on the motherboard of a computer and used to
connect I/O interfaces for a wide variety of devices. A device connected to the PCI bus
appears to the processor as if it is connected directly to the processor bus.
Bus Structure
The use of the PCI bus in a computer system is illustrated in Figure. The PCI bus is
connected to the processor bus via a controller called a bridge. The bridge has a special port
for connecting the computer’s main memory. It may also have another special highspeed
port for connecting graphics devices. The bridge translates and relays commands and
responses from one bus to the other and transfers data between them. For example, when
the processor sends a Read request to an I/O device, the bridge forwards the command and
address to the PCI bus. When the bridge receives the device’s response, it forwards the data
to the processor using the processor bus. I/O devices are connected to the PCI bus, possibly
through ports that use standards such as Ethernet, USB, SATA, SCSI, or SAS. The PCI bus

Mr. Amareswara Kumar Archakam Page

Computer
supports three independent address spaces: memory, I/O, and configuration.

Data transfers on a computer bus often involve bursts of data rather than individual
words. Words stored in successive memory locations are transferred directly between the
memory and an I/O device such as a disk or an Ethernet connection. Data transfers are
initiated by the interface of the I/O device, which acts as a bus master. The PCI bus is
designed primarily to support multiple-word transfers. A Read or a Write operation
involving a single word is simply treated as a burst of length one. The PCI bus uses the same
lines to transfer both address and data. In Figure, we assumed that the master maintains the
address information on the bus until the data transfer is completed. But, this is not
necessary. The address is needed only long enough for the slave to be selected, freeing the
lines for sending data in subsequent clock cycles.

SCSI BUS :
The acronym SCSI stands for Small Computer System Interface. It refers to a
standard bus defined by the American National Standards Institute (ANSI). The SCSI bus
may be used to connect a variety of devices to a computer. It is particularly well-suited for
use with disk drives. It is often found in installations such as institutional databases or
email systems where many disks drives are used.
In the original specifications of the SCSI standard, devices are connected to a
computer via a 50-wire cable, which can be up to 25 meters in length and can transfer data
at rates of up to 5 Megabytes/s.

The bus may use single- ended transmission, where each signal uses one wire, with a

Mr. Amareswara Kumar Archakam Page

Computer
common ground return for all signals.
Data Transfer

Devices connected to the SCSI bus are not part of the address space of the processor
in the same way as devices connected to the processor bus or to the PCI bus. A SCSI bus may
be connected directly to the processor bus, or more likely to another standard I/O bus such
as PCI, through a SCSI controller. Data and commands are transferred in the form of multi-
byte messages called packets. To send commands or data to a device, the processor
assembles the information in the memory then instructs the SCSI controller to transfer it to
the device. Similarly, when data are read from a device, the controller transfers the data to
the memory and then informs the processor by raising an interrupt.
The processor sends a command to the SCSI controller, which causes the following
sequence of events to take place:
1. The SCSI controller contends for control of the SCSI bus.
2. When it wins the arbitration process, the SCSI controller sends a command to the
disk controller, specifying the required Read operation.
3. The disk controller cannot start to transfer data immediately. It must first move the read
head of the disk to the required sector. Hence, it sends a message to the SCSI controller
indicating that it will temporarily suspend the connection between them. The SCSI bus
is now free to be used by other devices.
4. The disk controller sends a command to the disk drive to move the read head to the
first sector involved in the requested Read operation. It reads the data stored in that sector
and stores them in a data buffer. When it is ready to begin transferring data, it requests
control of the bus. After it wins arbitration, it re-establishes the connection with the
SCSI controller, sends the contents of the data buffer, then suspends the connection
again.
5. The process is repeated to read and transfer the contents of the second disk sector.
6. The SCSI controller transfers the requested data to the main memory and sends an
interrupt to the processor indicating that the data are now available.

Universal Serial Bus (USB) :

The Universal Serial Bus (USB) is the most widely used interconnection standard. A
large variety of devices are available with a USB connector, including mice, memory keys,
disk drives, printers, cameras, and many more. The commercial success of the USB is due to
its simplicity and low cost. The original USB specification supports two speeds of operation,
called low-speed (1.5 Megabits/s) and full-speed (12 Megabits/s). Later, USB 2, called High-
Speed USB, was introduced. It enables data transfers at speeds up to 480 Megabits/s. As I/O
devices continued to evolve with even higher speed requirements, USB 3 (called
Mr. Amareswara Kumar Archakam Page
Computer
Superspeed) was developed. It supports data transfer rates up to 5 Gigabits/s. The USB has
been designed to meet several key objectives:
• Provide a simple, low-cost, and easy to use interconnection system
• Accommodate a wide range of I/O devices and bit rates, including Internet
connections, and audio and video applications

• Enhance user convenience through a “plug-and-play” mode of operation We will

elaborate on some of these objectives before discussing the technical details of the
USB.
USB Architecture
The USB uses point-to-point connections and a serial transmission format. When
multiple devices are connected, they are arranged in a tree structure as shown in Figure.
Each node of the tree has a device called a hub, which acts as an intermediate transfer point
between the host computer and the I/O devices. At the root of the tree, a root hub connects
the entire tree to the host computer. The leaves of the tree are the I/O devices: a mouse, a
keyboard, a printer, an Internet connection, a camera, or a speaker.

The tree structure makes it possible to connect many devices using simple point-to-
point serial links. If I/O devices are allowed to send messages at any time, two messages
may reach the hub at the same time and interfere with each other. For this reason, the USB
operates strictly on the basis of polling. A device may send a message only in response to a
poll message from the host processor. Hence, no two devices can send messages at the same
time. This restriction allows hubs to be simple, low- cost devices.

Isochronous Traffic on USB

An important feature of the USB is its ability to support the transfer of isochronous
data in a simple manner. As mentioned earlier, isochronous data need to be transferred at
precisely timed regular intervals. To accommodate this type of traffic, the root hub
transmits a uniquely recognizable sequence of bits over the USB tree every millisecond.
This sequence of bits, called a Start of Frame character, acts as a marker indicating the
beginning of isochronous data, which are transmitted after this character. Thus, digitized
audio and video signals can be transferred in a regular and precisely timed manner.

Mr. Amareswara Kumar Archakam Page

Computer

Mr. Amareswara Kumar Archakam Page