2.

Digital Logic and

Microprocessor
Er. Pralhad Chapagain
Syllabus
MICROPROCESSOR SYSTEM
➢ A microcomputer consists of a set of components or modules of three basic types
CPU memory and I/O units which communicate with each other.

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PIN CONFIGURATION OF 8085

Fig (a) - Pin Diagram of 8085 & Fig(b) - logical schematic of Pin diagram

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PIN CONFIGURATION OF 8085
➢ The microprocessor is a clock-driven semiconductor device consisting of electronic
logic circuits manufactured by using either a large-scale integration (LSI) or very-
large-scale integration (VLSI) technique.

➢ The microprocessor is capable of performing various computing functions and

making decisions to change the sequence of program execution.

➢ In large computers, a CPU implemented on one or more circuit boards performs

these computing functions.

➢ The microprocessor is in many ways similar to the CPU, but includes the logic
circuitry, including the control unit, on one chip.
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PIN CONFIGURATION OF 8085
➢ The microprocessor can be divided into three segments for the sake clarity,
arithmetic/logic unit (ALU), register array, and control unit.

➢ 8085 is a 40 pin IC, DIP package. The signals from the pins can be grouped as follows
➢ 1. Power supply and clock signals

➢ 2. Address bus

➢ 3. Data bus

➢ 4. Control and status signals

➢ 5. Interrupts and externally initiated signals

➢ 6. Serial I/O ports

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PIN CONFIGURATION OF 8085
Power supply and Clock frequency signals:

➢ Vcc : + 5 volt power supply

➢ Vss : Ground

➢ X1, X2 : Crystal or R/C network or LC network connections to set the frequency of

internal clock generator.

➢ The frequency is internally divided by two. Since the basic operating timing
frequency is 3 MHz, a 6 MHz crystal is connected externally.

➢ CLK (output) :Clock Output is used as the system clock for peripheral and devices
interfaced with the microprocessor.
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PIN CONFIGURATION OF 8085
2. Address Bus:

➢ A8 - A15

➢ It carries the most significant 8 bits of the memory address or the 8 bits of the I/O address.

3. Multiplexed Address / Data Bus:

➢ AD0 - AD7

➢ These multiplexed set of lines used to carry the lower order 8 bit address as well as data bus.

➢ During the opcode fetch operation, in the first clock cycle, the lines deliver the lower order address
A0 - A7.

➢ In the subsequent IO / memory, read / write clock cycle the lines are used as data bus.

➢ The CPU may read or write out data through these lines.
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PIN CONFIGURATION OF 8085

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PIN CONFIGURATION OF 8085
Control and Status signals:

➢ These signals include two control signals (RD & WR) three status signals (IO/M, S1 and So)
to identify the nature of the operation and one special signal (ALE) ti indicate the beginning
of the operations.

➢ ALE (output) - Address Latch Enable.

➢ This signal helps to capture the lower order address presented on the multiplexed address /
data bus. When it is the pulse, 8085 begins an operation. It generates AD0 - AD7 as the separate
set of address lines A0 –A7.

➢ RD (active low) - Read memory or IO device.

➢ This indicates that the selected memory location or I/O device is to be read and that the data
bus is ready for accepting data from the memory or I/O device.
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PIN CONFIGURATION OF 8085
➢ WR (active low) - Write memory or IO device.
➢ This indicates that the data on the data bus is to be written into the selected memory location or
I/O device.

➢ IO/M’ (output) - Select memory or an IO device.

➢ This status signal indicates that the read / write operation relates to whether the memory or I/O
device.

➢ It goes high to indicate an I/O operation.

➢ It goes low for memory operations.

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PIN CONFIGURATION OF 8085
Status Signals:
➢ It is used to know the type of current operation of the microprocessor.

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PIN CONFIGURATION OF 8085
Interrupts and Externally initiated operations:

➢ They are the signals initiated by an external device to request the microprocessor to do a
particular task or work.

➢ There are five hardware interrupts called,

➢ On receipt of an interrupt, the microprocessor acknowledges the interrupt by the active low
INTA (Interrupt Acknowledge) signal.

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PIN CONFIGURATION OF 8085
➢ Hold (Input)
➢ This indicates peripheral controller requesting the bus.

➢ HLDA (Output)
➢ This indicates the acknowledgement for the Hold request.

➢ READY (Input)
➢ It is used to delay the microprocessor read and write cycles until a slow responding peripheral is
ready to send or accept data.
➢ Memory and I/O devices will have slower response compared to microprocessors.
➢ Before completing the present job such a slow peripheral may not be able to handle further data or
control signal from CPU.
➢ The processor sets the READY signal after completing the present job to access the data.
➢ The microprocessor enters into WAIT state while the READY pin is disabled. 15
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PIN CONFIGURATION OF 8085
➢ Reset In (input, active low)
➢ This signal is used to reset the microprocessor.
➢ The program counter inside the microprocessor is set to zero.
➢ The buses are tri-stated.

➢ Reset Out (Output)

➢ It indicates CPU is being reset.
➢ Used to reset all the connected devices when the microprocessor is reset.

Single Bit Serial I/O ports:

➢ SID (input) - Serial input data line
➢ SOD (output) - Serial output data line
➢ These signals are used for serial communication.
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Bus structure
➢ A microcomputer consists of a set of components or modules of three basic types CPU
memory and I/O units which communicate with each other.

➢ A bus is a communication pathway between two or more such components.

➢ A bus actually consists of multiple communication pathway or lines. Each line is capable of
transmitting signals representing binary 1 and 0.

➢ Several lines of the bus can be used to transmit binary data simultaneously.

➢ The bus that connects major microcomputer components such as CPU, memory or I/O is
called the system bus.

➢ System bus consists of number of separate lines. Each line assigned a particular function.

➢ Fundamentally in any system bus the lines can be classified into three group buses.
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Bus structure
Data Bus:
➢ Data bus provides the path for monitoring data between the system modules. The bus has various
numbers of separate lines like 8, 16, 32, or 64. Which referred as the width of data bus .These number
represents the no. of bits they can carry because each carry 1 bit.

Address Bus:

➢ Each Lines of address bus are used to designate the source or destination of the
data on data bus.
➢ For example, if the CPU requires reading a word (8, 16, 32) bits of data from
memory, it puts the address of desired word on address bus. The address bus is also
used to address I/O ports. Bus width determines the total memory the up can
handle.
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Bus structure
Control Bus:

➢ The control bus is a group of lines used to control the access to control signals and the use of the
data and address bus. The control signals transmit both command and timing information between
the system modules. The timing signals indicate the validity of data and address information, where
as command signals specify operations to be performed. Some of the control signals are:

➢ Memory Write (MEMW): It causes data on the bus to be loaded in to the address location.

➢ Memory Read (MEMR): It causes data from the addressed location to be placed on the data bus.

➢ I/O Write (IOW): It causes the data on the bus to be output to the addressed I/O port.

➢ I/O Read (IOR): It causes the data from the addressed I/O port to be placed on the bus.

➢ Transfer Acknowledge: This signal indicates that data have been accepted from or placed on the bus.

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Bus structure
➢ Bus Request: It is used to indicate that a module wants to gain control of the bus.

➢ Bus Grant: It indicates that a requesting module has been granted for the control of
bus.

➢ Interrupt Request: It indicates that an interrupt has been pending.

➢ Interrupt Acknowledge: it indicates that the pending interrupt has been recognized.

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Bus types
Synchronous Bus:

➢ In a synchronous bus, The Occurrence of the events on the bus is determined by a

clock .

➢ The clock transmits a regular sequence of 0’s & 1’s of equal duration. All the events
start at beginning of the clock cycle.

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Bus types
➢ Here the CPU issues a START signal to indicate the presence of address and control
information on the bus.

➢ Then it issues the memory read signal and places the memory address on the
address bus.

➢ The addressed memory module recognizes the address and after a delay of one
clock cycle it places the data and acknowledgment signal on the buses.

➢ In synchronous bus, all devices are tied to a fixed rate, and hence the system can
not take advantage of device performance but it is easy to implement.

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Bus types
Asynchronous Bus:

➢ In an asynchronous bus, the timing is maintained in such way that occurrence of

one event on the bus follows and depends on the occurrence of previous event.

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Bus types
➢ Here the CPU places Memory Read (Control) and address signals on the bus.

➢ Then it issues master synchronous signal (MSYNC) to indicate the presence of valid
address and control signals on the bus.

➢ The addressed memory module responds with the data and the slave synchronous
signal (SSYNC)

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Timing diagram
➢ It is a graphical representation. It represents the execution time taken by each
instruction in a graphical format. The execution time is represented in T-state.

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Instruction cycle
➢ It is defined as the time required to complete the execution of an instruction.

➢ The necessary steps that the CPU carries out to fetch an instruction and necessary data
from the memory and to execute it constitute an instruction cycle.

➢ An instruction cycle consists of fetch cycle and execute cycle.

➢ In fetch cycle CPU fetches op-code from the memory.

➢ The necessary steps which are carried out to get data if any from the memory and to
perform the specific operation specified in instruction constitute an execute cycle.

➢ The total time required to execute an instruction is given by IC=FC+EC

➢ The 8085 consists of 1-5 machine cycle or operation.

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fetch cycle
➢ The first byte of an instruction is its op-code.

➢ The content of the program counter, which is the address of the memory location
where op-code is available, is send to the memory.

➢ The memory places the op-code on the data bus so as to transfer it to CPU.

➢ The entire process takes 3 clock cycle and then the instruction is decoded in next
one clock cycle.

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Execute cycle
➢ The op-code from the memory goes to the IR, from the IR it goes to the decoder
which decodes instruction. After the instruction is decoded execution begins.

➢ If the operand is in general purpose register, execution is performed immediately.

➢ If an instruction contains data or operand address, then CPU has to perform some
read operations to get the desired data.

➢ In some instruction write operation is performed. In write cycle data are sent from
the CPU to the memory of an o/p device.

➢ In some cases execute cycle may involve one or more read or write cycle or both.

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machine cycle
➢ It is defined as the time required to complete one operation of accessing memory i/p, o/p or acknowledging the
external request. This cycle may consists of 3 to 6 T states.

➢ Op-code Fetch Cycle

➢ Memory Read Cycle (3T)

➢ Memory Write Cycle (3T)

➢ I/O Read Cycle (3T)

➢ I/O Write Cycle (3T)

➢ Interrupt acknowledge

➢ Bus idle

T-state:

➢ It is defined as one sub-division of the operation performed in one clock period. These sub-division are internal states
synchronized with system clock and each T state precisely equal to one clock period.

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Opcode fetch machine cycle
➢ The first machine cycle of every instruction is opcode fetch cycle in which the 8085 finds the
nature of the instruction to be executed.

➢ In this machine cycle, the microprocessor places the contents of PC on the address bus then
by reading operation it reads the op-cod of an instruction from determined memory
location. The length of this cycle is not fixed.

Step1: (T1 state)

➢ The 8085 processor places the contents of program counter on the address bus, activate the ALE
and send the status signals IO/M’, S1, and S0 with logical status (0 1 1) respectively.

Step 2: (T2 state)

➢ The low order address disappears from AD0-AD7 lines. Also, 8085 processor activates the RD
signals to enable the addressed memory location which places its contents on the data bus
(AD0-AD7).
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Opcode fetch machine cycle
Step 3: (T3 state)

➢ The processor loads the contents of data bus on its Instruction Register and deactivates the
RD signal to disables the memory devices.

Step4: (T4 state)

➢ Microprocessor decodes the instruction and performed the task specified into instruction.

Step5: (T5 & T6 states)

➢ The processor performs stack write, internal 16 bits, or conditional return operations
depending upon the type of instruction.

➢ One byte instructions those operate on 16 bit data are executed in T5 & T6. For example
DCX H, PCHL, SPHL, INX H, etc.
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 Opcode fetch machine cycle

Instruction that takes 6-

T for opcode fetch

CRISP

C- CALL, Conditional
RET.

R- RST

I- INX ,DCX

S- SPHL, PCHL

P- PUSH

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MEMORY READ machine cycle
➢ The microprocessor executes the memory read cycle to read the data from RAM or ROM memory.
8085 processor executes this machine cycle in 3 T-states. Steps below show the details of this
machine cycle:

➢ Step1 (T1 state):

➢ processor places the address on the address lines from SP, Rp, or PC and activates ALE in order to
latch low-order of address. Also, it sends the status signals IO/M’, S1, and S0 with logical status (0 1 0)
for memory read machine cycle.

➢ Step2 (T2 state):

➢ 8085 processor activates the RD’ signals to enable the addressed memory location which places its
contents on the data bus (AD0-AD7).

➢ Step 3: (T3 state)

➢ The processor loads the contents of data bus on specified register (F, A, B, C, D, E, H, and L) and
deactivates the RD’ signal to disables the memory devices.
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MEMORY READ machine cycle

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MEMORY WRITE machine cycle
➢ The microprocessor executes the memory write cycle to store the data into RAM or stack memory.
8085 processor executes this machine cycle in 3 T-states. Steps below show the details of this
machine cycle:

➢ Step1 (T1 state):

➢ processor places the address on the address lines from SP or Rp and activates ALE in order to latch
low-order of address. Also, it sends the status signals IO/M’, S1, and S0 with logical status (0 0 1) for
memory write machine cycle.

➢ Step2 (T2 state):

➢ 8085 processor places the data on data bus and activates the WR’ signal to writing data into
addressed memory location.

➢ Step 3: (T3 state)

➢ The processor deactivates the WR’ signal which disables the memory device and terminates the write
operation.
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MEMORY WRITE machine cycle

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IO READ machine cycle
➢ The microprocessor executes the IO read cycle to read the data from input device. 8085 processor
executes this machine cycle in 3 T-states. Steps below show the details of this machine cycle:

➢ Step1 (T1 state):

➢ processor places the address on the address lines from SP, Rp, or PC and activates ALE in order to
latch low-order of address. Also, it sends the status signals IO/M’, S1, and S0 with logical status (1 1 0)
for IO read machine cycle.

➢ Step2 (T2 state):

➢ 8085 processor activates the RD’ signals to enable the addressed input device which places its
contents on the data bus (AD0-AD7).

➢ Step 3: (T3 state)

➢ The processor loads the contents of data bus on specified register (F, A, B, C, D, E, H, and L) and
deactivates the RD’ signal to disables the input device.
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IO READ machine cycle

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IO write machine cycle
➢ The microprocessor executes the IO write cycle to store the data into output device. 8085 processor
executes this machine cycle in 3 T-states. Steps below show the details of this machine cycle:

➢ Step1 (T1 state):

➢ processor places the address on the address lines from SP or Rp and activates ALE in order to latch low-order of
address. Also, it sends the status signals with logical status (1 0 1) for IO write machine cycle.

➢ Step2 (T2 state):

➢ 8085 processor places the data on data bus and activates the WR’ signal to writing data into addressed output
device.

➢ Step 3: (T3 state)

➢ The processor deactivates the WR’ signal which disables the output device and terminates the writing operation.

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IO write machine cycle

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memory

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memory
➢ Memory is an essential component of the microcomputer system.

➢ It is used to store both instructions and data.

➢ Memory is made up of registers and the number of bits stored in a register is called
memory word .

➢ Memory word is identified by an address .

➢ If microprocessor uses 16 bit address , then there will be maximum of 216= 65536
memory addresses ranging from 0000H to FFFFH.

➢ There are various types of memory which can be classified in to two main groups
i.e. Primary memory and Secondary memory.
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memory
Processor Memory

➢ Processor memory refers to a set of microprocessor registers.

➢ They are used to hold temporary results when a computation is in progress Although use of such registers enhances
the execution speed

➢ The cost involved in the approach forces a microcomputer designer to include only a few registers include the
processor.

➢ In 8085 we have registers like A, B, C, D, E, H, L, SP, PC etc. to store data temporarily

Primary Memory

➢ It is the storage area where all programs are executed. The microprocessor can directly access only those items that
are stored in the primary memory

➢ Hence, all programs and data must be within the primary memory prior to execution.

➢ Usually, the size of the primary memory is much larger than that of processor memory and its operating speed is much
slower than processor's registers.
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memory
➢ Primary memories can be divided into two main groups
➢ Read only memory (ROM)

➢ Random Access memory .(RAM)

RAM

➢ It is used primarily for information that is likely to be altered, such as writing

programs or receiving data.

➢ This memory is volatile Two types of RAM are available

➢ Static RAM
➢ This memory is made up of flip flops and stores the bits as voltage.
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memory
➢ Each memory cell requires six transistors.

➢ This memory is more expensive and power consuming than dynamic memory.

➢ It is called ' because the information doesn't need a constant update.

➢ These memories are commonly used for cache memory.

➢ This types of memory is very fast with access time is 15 to 30 nanoseconds but is
physically bulky.

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memory
Dynamic RAM (DRAM)
➢ Dynamic random access memory is an improvement over the expensive and bulky SRAM.
➢ DRAM uses a different approach to store data Information is stored as charges in a very small
capacitor.
➢ If a charge exists in a capacitor, it's interpreted as 1 The absence of a charge will be interpreted as 0.
➢ Because DRAM uses capacitors there is a chance of leakage of charge.
➢ Thus it needs to use a constant refresh signal to keep the information in the memory (every few
millisecond)
➢ DRAM technology allows several memory units, called cells to be packed at very high density.
➢ Therefore, these chips can hold very large amount of information.
➢ Most PCs today use DRAM.
➢ Access time for DRAM is 80 nanoseconds or more, slower than SRAM, and two or three times faster
than ROM
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memory

DRAM

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memory
Read only memory (ROM)

➢ ROM is a non volatile memory and can be read only.

➢ It is used to store data and programs that are not to be altered

➢ Among other things ROM is needed for storing an initial program called boot strap loader.

➢ The bootstrap loader is a program whose function is to start the computer software operating when power is turned
on.

➢ Since RAM is volatile, its contents are destroyed when power is turned off . The contents of ROM remain unaltered
after power is turned off and on again

➢ The startup of a computer consists of turning the power on and starting the execution of an initial program.

➢ Thus when power is turned on, the hardware of the computer sets the program counter to the first address of the
bootstrap loader.

➢ The bootstrap program loads a portion of the operation of the operating system from disk to main memory and
control is then transferred to the operating system, which prepares the computer for general use.

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memory
Masked ROM

➢ They are permanent ROM recorded by masking Generally manufacturers use

this process to produce ROM in large numbers

PROM
➢ These are un programmed ROM The fuses on the ROM are not burned.

➢ A programmer can program this ROM according to his needs.

➢ The information stored is permanent.

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memory
EPROM

➢ These ROM can be reprogrammed and erased. Two types of such EPROM are available

UV EPROM

➢ The memory of such ROM can be erased by exposing the chip via a lid or window on the chip to ultraviolet light.

➢ The erase time generally varies between 10 to 30 minutes.

➢ The EPROM can be programmed by inserting the chip into a socket of the PROM programmer and providing
proper addresses.

➢ The programming time varies from 1 to 2 minutes.

EEPROM

➢ This does not require UV rays to be erased It can be completely erased or have certain byes changed, using
electrical pulses

➢ Writing to EEPROM is slower than writing to RAM, so it can not be used in high speed circuits. 50
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memory
FLASH MEMORY

➢This is a modified EEPROM. The difference is the erasure procedure.

➢EEPROM can be erased at a register level, but flash memory must be

erased either in its entirety or at the sector (block) level

Secondary Memory

➢Secondary memory are storage devices. These devices have high data
holding capacity.

➢They store programs that are not frequently used by the processor.
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memory
Performance of memory

➢ Access time (ta)

➢ Read access time: It is the average time required to read the unit of information from memory

➢ Write access time: It is the average time required to write the unit of information on memory

➢ Access rate ra = 1 /ta

➢ Cycle time (tc)

➢ It is the average time that lapses between two successive read operation Cycle rate (rc) =
bandwidth = (1/tc)

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memory
➢ Access modes of memory

➢ Random access
➢ In random access mode, the ta is independent of the location from which the data is accessed
like MOS memory

➢ Sequential access
➢ In that mode, the ta is dependent of the location form which the data is accessed like magnetic
type

➢ Semi random access

➢ The semi random access combines these two For e.g. In magnetic disk, any track can be
accessed at random But the access within the track must be in serial fashion
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Memory hierarchy
➢ Capacity, cost and speed of different types of memory play a vital role while designing a memory
system for computers.

➢ If the memory has larger capacity, more application will get space to run smoothly.

➢ It's better to have fastest memory as far as possible to achieve a greater performance. Moreover for
the practical system, the cost should be reasonable.a

➢ There is a tradeoff between these three characteristics cost, capacity and access time. One cannot
achieve all these quantities in same memory module because
➢ If capacity increases, access time increases (slower) and due to which cost per bit decreases.

➢ If access time decreases (faster), capacity decreases and due to which cost per bit increases.

➢ The designer tries to increase capacity because cost per bit decreases and the more application
program can be accommodated. But at the same time, access time increases and hence decreases
the performance.
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Memory hierarchy
➢ So the best idea will be to use memory hierarchy.

➢ Memory Hierarchy is to obtain the highest possible access speed while minimizing the total cost of
the memory system.

➢ Not all accumulated information is needed by the CPU at the same time.

➢ Therefore, it is more economical to use low-cost storage devices to serve as a backup for storing the
information that is not currently used by CPU

➢ The memory unit that directly communicate with CPU is called the main memory

➢ Devices that provide backup storage are called auxiliary memory

➢ The memory hierarchy system consists of all storage devices employed in a computer system from
the slow by high-capacity auxiliary memory to a relatively faster main memory, to an even smaller
and faster cache memory
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Memory hierarchy
➢ The main memory occupies a central position by being able to communicate directly with the CPU
and with auxiliary memory devices through an I/O processor

➢ A special very-high-speed memory called cache is used to increase the speed of processing by
making current programs and data available to the CPU at a rapid rate

➢ CPU logic is usually faster than main memory access time, with the result that processing speed is
limited primarily by the speed of main memory

➢ The cache is used for storing segments of programs currently being executed in the CPU and
temporary data frequently needed in the present calculations

➢ The memory hierarchy system consists of all storage devices employed in a computer system from
slow but high capacity auxiliary memory to a relatively faster cache memory accessible to high speed
processing logic. The figure below illustrates memory hierarchy.

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 Memory hierarchy

As we go down in the Hierarchy List

hierarchy ➢ Registers

➢ Cost per bit decreases ➢ L1 Cache

➢ L2 Cache
➢ Capacity of memory
➢ Main memory
increases
➢ Disk cache
➢ Access time increases
➢ Disk
➢ Frequency of access of ➢ Optical
memory by processor also ➢ Tape
decreases.

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Memory structure and its requirements
➢ Internally a memory consists of address decoder, input buffer, output buffer, registers with
address lines, data lines, and (𝑅𝐷’) (𝑊𝑅’), (𝐶𝑆’) control lines.

➢ The number of address lines will be determined by the memory capability.

➢ The number of data lines will be determined by memory size.

➢ For 2n X m memory capability, the number of address line =n and the number of data lines
=m.

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Address decoding

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Serial interface

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Parallel interface
➢ The device which can handle data at higher speed cannot support with serial interface.

➢ N bits of data are handled simultaneously by the bus and the links to the device directly.

➢ Achieves faster communication but becomes expensive due to need of multiple wires.

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Synchronizing the computer with peripherals
➢ The information exchanged between a microprocessor and an I/O interface circuit consists
of input or output data and control information.

➢ The status information enable the microprocessor monitor the device and when it is ready
then send or receive data.

➢ Control information is the command by microprocessor to cause I/O device to take some
action.

➢ If the device operates at different speeds, then microprocessor can be used to select a
particular speed of operation of the device.

➢ The techniques used to transfer data between different speed devices and computer is
called synchronizing. Different techniques under synchronizing are:
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Synchronizing the computer with peripherals
Simple I/O:
➢ For simple I/O, the buffer switch and latch switches i. e. LED are always connected to the input
and output ports.

➢ The devices are always ready to send or receive data.

➢ Here cross line indicate the time for new valid data.

Wait Interface( Simple strobe I/O)

➢ In this technique, microprocessor need to wait until the device is ready for the operation.

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Synchronizing the computer with peripherals
➢ Consider a simple keyboard consisting of 8 switches connected to a
microprocessor through a parallel interface circuit (Tri-state buffer).

➢ The switch is of dip switches.

➢ In order to use this keyboard as an input device the microprocessor should be

able to detect that a key has been activated.

➢ This can be done by observing that all the bits are in required order.

➢ The processor should repeatedly read the state of input port until it finds the
right order of bits i.e. at least 1 bit of 8 bits should be 0.

➢ Consider the tri-state A/D converter

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Synchronizing the computer with peripherals
➢ Used to convert analog to digital data which can be read by I/O unit of MP

➢ When SOC appears 1, I/O unit should ready for reading binary data/digital data.

➢ When EOC’s status is 1, then I/O unit should stop to read data.

➢ Strobe signal indicates the time at which data is being activated to transmit.

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Synchronizing the computer with peripherals
Single Handshaking:

➢ The peripheral outputs some data and send STB’ signal to microprocessor. “here
is the data for you.”

➢ Microprocessor detects asserted STB’ signal, reads the data and sends an
acknowledge signal (ACK) to indicate data has been read and peripheral can
send next data. “I got that one, send me another.”

➢ Microprocessor sends or receives data when peripheral is ready.

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Synchronizing the computer with peripherals
Double Handshaking:

➢ The peripheral asserts its STB’ line low to ask MP “Are you ready?”

➢ The MP raises its ACK line high to say “ I am ready”.

➢ Peripheral then sends data and raises its STB’ line low to say “Here is some valid
data for you.”

➢ MP then reads the data and drops its ACK line to say, “I have the data, thank
you, and I await your request to send the next byte of data.”

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Programmable peripheral interface (ppi) – 8255A
➢ The Intel 8255A is a general purpose programmable I/O device designed for use with Intel
microprocessors.

➢ It has 24 I/O pins that can be grouped primarily in two 8-bit parallel ports: A and B, with the
remaining bits as port C.

➢ The 8-bits of port C can be used as individual bits or be grouped in two 4-bits ports: Cupper (Cu) and
Clower (Cl).

➢ The functions of these ports are defined by writing a control word in the control register.

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Programmable peripheral interface (ppi) – 8255A
Block diagram:

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Programmable peripheral interface (ppi) – 8255A
Data Bus Buffer

➢ The 3-state bidirectional 8-bit buffer is used to interface the 8255A to the system data bus.

➢ Data is transmitted or received by the buffer upon execution of input or output instructions by the
CPU.

➢ Control words and status information are also transferred through the data bus buffer.

Read/Write Control Logic

➢ The function of the block is to manage all of the internal and external transfers of both data and
control or status words.

➢ It accepts inputs from the CPU address and control buses and in turn, issues commands to both of
the control groups.

➢ Chip Select (CS’): A “low” on this pin enables the communications between the 8255A and the CPU.
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Programmable peripheral interface (ppi) – 8255A
➢ Read (RD’): A “low” on this input enables the 8255A to send the data or status information to the
CPU on the data bus. In essence, it allows the CPU to read from the 8255A.

➢ Write (WR’): A “low” on this input pin enables the CPU to write data or control words into the
8255A.

➢ Reset (RESET): A “high” to this pin clears the control register and sets all ports (A, B and C) in the
input mode.

➢ A0 and A1: These input signals controls the selection of one of the three ports or the control word
register. They are connected to the least significant bits of the address bus.

➢ The CS’ signal is the master chip select, and A0 and A1 specify one of the I/O ports or the control
register as given below.

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Programmable peripheral interface (ppi) – 8255A

➢ Group A and Group B controls

➢ Each of the control blocks (Group A and Group B) accepts “commands” from the Read/Write control logic,
receives control word from the internal data bus and issues the proper commands to its associated ports.

➢ Control Group A – Port A and Port CUpper (C7 – C4)

➢ Control Group B – Port B and Port CLower (C3 – C0)

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Programmable peripheral interface (ppi) – 8255A
Control Word

➢ When A0 and A1 pins have value 1, the mapped address addresses the control register which is the
8-bit register to write the specific content according to the port conditions although it cannot be
read. The content of this register is called control word which specifies an I/O function for each port.

➢ To communicate with peripherals through 8255, following steps are necessary.

➢ Determine the Port addresses of Ports A, B and C and of the control register, according to Chip Select
logic and address lines A1 and A0.

➢ Write a control word in control register.

➢ Write I/O instructions to communicate with peripherals through Ports A, B and C.

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Programmable peripheral interface (ppi) – 8255A

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Programmable peripheral interface (ppi) – 8255A
Operating modes:

➢ Bit Set/Reset mode: The BSR mode is used to set or reset the bits in port C.

➢ I/O mode: The I/O mode is further divided into three modes: mode 0, mode 1 and mode 2.

➢ In mode 0, all ports function as simple I/O ports.

➢ Mode 1 is a handshake mode whereby ports A and/or B use bits from port C as handshake signals. In
the handshake mode, two types of I/O data transfer can be implemented: status check and interrupt.

➢ In mode 2, port A can be set up for bidirectional data transfer using handshake signals from port C
and port B can be set up either in mode 0 or mode 1.

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Programmable peripheral interface (ppi) – 8255A
BSR Mode (Bit Set/Reset)

➢ BSR mode is concerned only with eight bits of port C, which can be set or reset by writing an
appropriate control word in the control register.

➢ A control word with bit D7=0 is recognized as a control word and it does not alter any previously
transmitted control word with bit D7=1; thus the I/O operations of ports A and B are not affected by
a BSR control word.

➢ In the BSR mode individual bits of port C can be used for applications such as On/Off switch

BSR Control Word:

➢ This control word, when written in control register, sets or resets one bit at a time, as specified in
figure

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Programmable peripheral interface (ppi) – 8255A

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Programmable peripheral interface (ppi) – 8255A
Mode 0 (Basic Input/output)

➢ This functional configuration provides simple input and output operation for each of the three ports.
No ‘handshaking” is required; data is simply written to or read from a specified port..

➢ Mode 0 basic functional definitions:

➢ Two 8-bit ports and two 4-bit ports

➢ Any port can be input or output

➢ Outputs are latched

➢ Inputs are not latched

➢ 16 different input/output configurations are possible in this mode.

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Programmable peripheral interface (ppi) – 8255A
Mode 1 (Strobe Input/output)

➢ The functional configuration provides a means for transferring I/O data to or from a specified port in
conjunction with strobes or handshaking signals.

➢ In mode 1, port A and port B use the lines of port C to generate or accept these handshaking signals.

➢ Mode 1 basic functional definitions:

➢ Two groups (Group A and Group B)

➢ Each group contains one 8-bit data port and one 4-bit control/data port

➢ The 8-bit data port can be either input or output. Both inputs and outputs are
latched.

➢ The 4-bit port is used for control and status of the 8-bit data port.
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Programmable peripheral interface (ppi) – 8255A
Mode 2 (Strobe Bidirectional Bus I/O)

➢ The functional configuration provides a means for communicating with a peripheral device or a structure on a
single 8-bit bus for both transmitting and receiving data (bidirectional bus I/O).

➢ “Handshaking Signals” are provided to maintain proper bus flow discipline in a similar manner to Mode 1.

➢ Interrupt generation and enable/disable functions are also available.

➢ Mode 2 basic functional definitions:

➢ Used in Group A only

➢ One 8-bit bidirectional bus port (Port A) and a 5-bit control port (Port C)

➢ Both inputs and outputs are latched

➢ The 5-bit control port (Port C) is used for control and status for the 8-bit, bidirectional bus port
(Port A)

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Serial data transmission
➢ Data are sent one bit at a time over the transmission channel.

➢ However, since most processors process data in parallel, the transmitter

needs to transform incoming parallel data into serial data and the
receiver needs to do the opposite.

➢ Cost of communication hardware is considerable reduced since only a

single wire or channel is require for transmission.

➢ Slow as compared to parallel transmission.

➢ Serial data can be sent synchronously or asynchronously.

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Serial data transmission - advantages
➢ Data transmission over longer distance because ➢ Clock skew between different cables is not an issue
voltage loss is not much a problem in serial
➢ Serials can be clocked at higher data rate
communication.
➢ Serial cable can be longer than parallel
➢ Serial; 1 →-3V to -25V
➢ Cheaper to implement
➢ 0 → +3V to +25V
➢ But in serial mode of transfer, only one bit of a word
➢ Parallel; 1→ +5V
is transferred at a time so that data transfer rate is
➢ 0 → 0V very slow; it is the one of the demerit over parallel
data transfer
➢ Requires less number of wires than parallel and so
cheaper to transmit data.

➢ Crosstalk is less of an issue because there are fewer

conductors’ compared to that of parallel cables.

➢ Many IC and peripherals have serial interface

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Serial data transmission
Serial Synchronous Data Transmission

➢ Data is transmitted or received based on a clock pulse (i.e. one bit at each clock pulse)

➢ In order to interpret the data correctly, the receiving device must know the start and end of each
data unit.

➢ The transmitter must know the number of data units to be transferred and the receiver must be
synchronized with the data boundaries.

➢ Therefore, there must be synchronization between the transmitter and receiver.

➢ Usually one or more SYNC characters are used to indicate the start of each synchronous data stream
or frame of data.

➢ Transmitter sends a large block of data characters one after the other with no time between
characters.
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Serial data transmission
➢ Transmitting device sends data continuously to the receiving device.

➢ If the data is not ready to be transmitted, the line is held in marking condition.

➢ To indicate the start of transmission, the transmitter sends out one or more SYNC characters or a
unique bit pattern called a flag, depending on the system being used.

➢ The receiving device waits for data, when it finds the SYNC characters or the flag then starts
interpreting the data which shifts the data following the SYNC characters and converts them to
parallel form so they can be read in by a computer.

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Serial data transmission
➢ Advantages and Disadvantages of Synchronous Communication

➢ Main advantage of Synchronous data communication is the high speed.

The synchronous communications require high-speed
peripherals/devices and a good-quality, high bandwidth communication
channel.

➢ The disadvantage includes the possible in accuracy. Because when a

receiver goes out of Synchronization, loosing tracks of where individual
characters begin and end. Correction of errors takes additional time.

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Serial data transmission
Serial Asynchronous Data Transmission

➢ The receiving device does not need to be synchronized with the transmitting device.

➢ The transmitting device can send one or more data units when it is ready to send data.

➢ Each data unit must be formatted i.e. must contain start and stop bits for indicating beginning and
the end of data unit. It also includes one parity bit to identify odd or even parity of data.

➢ To send ASCII character, the framing of data should contain:

➢ 1 start bit: Beginning of data

➢ 8 bit character: Actual data transferred

➢ 1 or 2 stop bits: End of data

➢ When no data is being sent, the signal line is in a constant high or marking state.

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Serial data transmission
➢ The beginning of the data character is indicated by the line going low for 1 bit time and this bit is
called a start bit.

➢ The data bits are then sent out on the line one after the other where the least significant bit is sent
out first.

➢ Parity bit should contain to check for errors in received data.

➢ After the data bit and a parity bit, the signal line is returned high for at least 1 bit time to identify the
end of the character, this always high bit is referred to as a stop bit. Some older systems use 2 stop
bits.

➢ Asynchronous communication is used when slow speed peripherals communicate with the
computer.

➢ The main disadvantage of asynchronous communication is slow speed transmission.

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Serial data transmission
➢ Asynchronous communication however, does not require the complex
and costly hardware equipment's as is required for synchronous
transmission.

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Serial data transmission
➢ Synchronous versus Asynchronous serial data transmission

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Bit rate and baud rate

➢ Bit Rate: ➢ E.g. 2400 baud rate means “the channel

can change states up to 2400 time per sec”
➢ Measure of no of data bits transmitted per
sec. ➢ If one frame of data is coded with 1 bit
then baud rate and bit rate are same.
➢ E.g. 2400 bits per sec means 2400 zeros or
ones can be transmitted in one sec.

➢ Baud Rate:
➢ No of times a signal in a communication
channel changes state.

➢ Change state means change from 0 to 1 or

from 1 to 0 up to 2400 times per sec.
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 Standards in serial i/o
➢ The serial I/O technique is commonly used to interface different peripheral terminals such
as printers, modems with microcomputers which are designed and manufactured by
various manufacturers.

➢ Therefore, a common understanding must exist, among various manufacturing and user
groups that can ensure compatibility among different equipment.

➢ The standard is defined as the understanding which is accepted in industry and by users.

➢ A standard is normally defined by a professional organizations such as IEEE (Institute of

Electrical and Electronics Engineers), EIA (Electronic Industries Association) as a de jure
standard. However, a widespread practice can become a de facto standard.

➢ In serial I/O, data can be transmitted as either current or voltage.

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 Rs-232c
➢ RS-232C is an interface developed to standardize the interface between data terminal equipment (DTE) and
data communication equipment (DCE) employing serial binary data exchange.

➢ Modem and other devices used to send serial data are called data communication equipment (DCE).

➢ The computers or terminals that are sending or receiving the data are called data terminal equipment (DTE).

➢ RS- 232C is the interface standard developed by electronic industries Association (EIA) in response to the
need for the signal and handshake standards between the DTE and DCE.

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Rs-232c
RS-232C has following standardize features.

➢ It uses 25 pins (DB – 25P) or 9 Pins (DE – 9P) standard, where 9 pins standard does not use all
signals i.e. data, control, timing and ground.

➢ It describes the voltage levels, impendence levels, rise and fall times, maximum bit rate and
maximum capacitance for all signal lines.

➢ It specifies that DTE connector should be male and DCE connector should be female.

➢ It can send 20kBd for a distance of 50 ft.

➢ The voltage level for RS-232 are:

➢ A logic high or 1 or mark, -3V to -15V

➢ A logic low or 0 or space, +3v to +15v

➢ Normally ±12V voltage levels are used 93

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Rs-232c

➢ Mc1488 line driver converts logic 1 to -9V Logic 0 to +9v

➢ Mc1489 line receiver converts RS – 232 to TTL

➢ Signal levels of RS-232 are not compatible with that of the DTE and DCE which are TTL signals for
that line driver such as M 1488 and line receiver MC1489 are used.

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Rs-232c

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Rs-232c
➢ Data Terminal Ready (DTR):
➢ After the terminal power is turned on and terminal runs any self checks, it asserts data terminal ready (DTR’) signal to
tell the modem that it is ready.

➢ Data Set Ready (DSR):

➢ When the MODEM is powered up and ready to transmit or receive data, it will assert data set ready (DSR’) to the
terminal. Under manual control or terminal control, modem then dials up the computer. If the computer is available, it
will send back a specified tone.

➢ Request to send (RTS):

➢ When a terminal has a character ready to send, it will assert a request-to-send (RTS’) signal to the modem.

➢ Data Carrier Detect (DCD):

➢ The modem will then assert its data-carrier-detect (DCD’) signal to the terminal to indicate that it has established
connection with the computer.

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Rs-232c
➢ Clear to send (CTS):
➢ When the modem is fully ready to receive data, it asserts the clear-to-send (CTS’) signal back to the terminal.

➢ Ring indicator (RI):

➢ It indicates that a ring has occurred at modem. Deactivating DTR or DSR breaks the connection but RI works
independently of DTR i.e. a modem may activate RI signal even if DTR is not active.

➢ Transmitted Data (TxD):

➢ The terminal then sends serial data characters to the modem.

➢ Received Data (RxD):

➢ Modem will receive data from terminal through this line.

➢ Data Signal Rate Detect (DSRD):

➢ It is used for switching different baud rate.

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Rs-232c
Digital Data Transmission Using Modem and standard Phone Lines

➢ Standard telephone system can be used for sending serial data over long distances.

➢ However, telephone lines are designed to handle voice, bandwidth of telephone lines ranges from
300 HZ

➢ to 3400 HZ.

➢ Digital signal requires a bandwidth of several megahertz. Therefore, data bits should be converted
into audio tones, this is accomplished through modems.

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Rs-232c
➢ DTE asserts DTR’ to tell the modem it is ready.

➢ Then DCE asserts DSR’ signal to the terminal and dials up.

➢ DTE asserts RTS’ signal to the modem.

➢ Modem then asserts DCD’ signal to indicate that it has established connection with the computer.

➢ DCE asserts CTS’ signals, then DTE sends serial data.

➢ When sending completed, DTE asserts RTS’ high, this causes modem to un assert its CTS’ signal
and stop transmitting similar handshake taken between DCE and DTE other side.

➢ To communicate from serial port of a computer to serial port of another computer without
modem, null-modem is used.

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Rs-232c – null modem connection
➢ A zero modem serves for data exchange between DTEs.

➢ Since both the computers are configured as DTEs, directly connecting them by means of the conventional
serial interface cable is impossible; not even the plug fits into the jack of the second terminal.

➢ Also the TxD meets TxD and RxD meets RxD, DTR meets DTR and DSR meets DSR etc.

➢ This means that outputs are connected to outputs and inputs are connected to inputs. With this convention,
no data transfer is possible.

➢ For the transmission of data, it is required to twist the TxD and RxD lines.

➢ In this way, the transmitted data of one terminal (PC) becomes received data of other and vice versa.

➢ As shown in figure, activation of RTS to begin a data transfer gives rise to an activation of CTS on same DTE
and to an activation of DCD on other DTE.

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Rs-232c – null modem connection
➢ Further, an activation of DTR leads to rise of DSR and RI on other DTE. Hence for every DTE, it is
simulated that a DCE is on the end of line, although a connection between two DTEs is actually
present.

➢ Zero modem can be operated with standard BIOS and DOS functions.

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Rs-232c – connection to printer

➢ PC may send data faster than the printer can acknowledge it.

➢ Therefore, pin 19 (Buffer Full) of printer is connected to DSR of PC side.

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Rs-232c – connection to printer
➢ An overflow of data deactivates the DSR signal and communication
halts

➢ On PC RTS and CTS are connected to each other so that a transmission

request from PC immediately enables the transmission.

➢ Printer as DTE refers to print anything as long as no active signal is

present at inputs. Of CTS, DSR and DCD.

➢ This problem is resolved by connecting RTS with CTS and DTR with
DCD and DSR.
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Rs-423a
➢ A major problem with RS-232C is that it can only transmit data reliably for about 50 ft at its maximum rate of
20Kbd.
➢ If longer lines are used the transmission rate has to be drastically reduced due to open signal lines with a
common signal ground.
➢ Another EIA standard which is improvement over RS-232C is RS-423A.

➢ The standardize features of RS-423 are:

➢ This standard specifies a low impendence single ended signal which can be sent over 50 ohm coaxial cable and
partially terminated at the receiving end to prevent reflection.

➢ Voltage levels
➢ Logic High 4V - 6V negative

➢ Logic Low 4V - 6V positive

➢ It allows a maximum data rate of 100 Kbd over 40 ft line or a maximum baud rate of 1 Kbd over 4000 ft line.

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Rs-422a
It is a newer standard for serial data transfer. It specifies that each signal will be sent differentially over two
adjacent wires in a ribbon cable or a twisted pair of wires uses differential amplifier to reject noise.

➢ The term differential in this standard means that the signal voltage is developed between two signal lines
rather than between signal line and ground as in RS-232C and RS-423A.

➢ Any electrical noise induced in one signal line will be induced equally in the other signal line.
➢ A differential line receiver MC3486 responds only to the voltage difference between its two inputs so any
noise voltage that is induced equally on two inputs will not have any effect on the output of the differential
receiver.

➢ RS-422A has following standardized features:

➢ Logic high is transmitted by making ‘b’ line more positive than ‘a’ line.

➢ Logic low is transmitted by making ‘a’ line more positive than ‘b’ line.

➢ The voltage difference between the two lines must be greater than 0.4V but less than 12V.

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comparison

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DMA (DIRECT MEMORY ACCESS)
➢ The data transfer between a fast storage media such as magnetic disk and memory unit is limited
by the speed of the CPU

➢ Thus we can allow the peripherals directly communicate with each other using the memory buses,
removing the intervention of the CPU This type of data transfer technique is known as DMA or
direct memory access

➢ During DMA the CPU is idle and it has no control over the memory buses

➢ The DMA controller takes over the buses to manage the transfer directly between the I/O devices
and the memory unit

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DMA (DIRECT MEMORY ACCESS)
➢ Bus Request It is used by the DMA controller to request the CPU to relinquish the
control of the buses

➢ Bus Grant It is activated by the CPU to inform the external DMA controller that the
buses are in high impedance state and the requesting DMA can take control of the
buses Once the DMA has taken the control of the buses it transfers the data

➢ DMA transfer uses two signal

➢ HOLD

➢ HLDA

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DMA (DIRECT MEMORY ACCESS)
➢ HOLD

➢ Active high input signal to 8085 from another master requesting the use of address and data
bus

➢ After receiving the HOLD request, the MPU relinquishes the buses in the following machine
cycle
➢ All buses are tri stated and HOLD acknowledge signal is sent out

➢ MPU regains the control of the buses after HOLD goes low

➢ HLDA
➢ This is an active high output signal indicting that MPU is relinquishing control of the buses

➢ A DMA controller uses these signals as if it were a peripheral requesting the MPU for the control of the
buses

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DMA (DIRECT MEMORY ACCESS)

The sequence of DMA Transfer

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DMA (DIRECT MEMORY ACCESS)
The sequence of DMA Transfer

➢ Originally, microprocessor is connected to the memory as shown in fig with

switches closed for address, data and control buses When peripheral wants to
transfer data using DMA transfer, it sends DMA request, DREQ, signal to the DMA
controller

➢ If the input ( of the DMA controller is unmasked, the DMA controller will send a
hold request, HRQ signal to the microprocessors HOLD input

➢ The microprocessor finishes the current machine cycle and floats its buses,
sending out a hold acknowledge signal, HLDA, to the DMA controller

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DMA (DIRECT MEMORY ACCESS)
➢ When DMA controller receives HLDA signal, it will send out a control signal which
disconnects the processors from buses and connects DMA controller to the buses
Now DMA controller sends out the address of the byte to be transferred and send
out DMA acknowledge ( to the peripheral device to tell it to get ready to output
the byte

➢ Then the DMA transfer begins and finally when the data transfer is complete, the
DMA controller un asserts its hold request signal to the processor and releases the
buses

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DMA (DIRECT MEMORY ACCESS)
➢ DMA performs data transfer operation The different DMA transfer modes are as
follows
➢ Burst or Block transfer DMA

➢ Cycle steal or Single byte transfer DMA

➢ Transparent DMA

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PROGRAMMABLE DMA CONTROLLER – INTEL 8257

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PROGRAMMABLE DMA CONTROLLER – INTEL 8257
➢ It is a device to transfer the data directly between IO device and memory without
through the CPU. So it performs a high-speed data transfer between memory and
I/O device.

➢ The features of 8257 is,

➢ The 8257 has four channels and so it can be used to provide DMA to four I/O devices.
➢ Each channel can be independently programmable to transfer up to 64kb of data by
DMA.
➢ Each channel can be independently perform read transfer, write transfer and verify
transfer.

➢ The functional blocks of 8257 as shown in the above figure are data bus buffer,
read/write logic, control logic, priority resolver and four numbers of DMA
channels.
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PROGRAMMABLE DMA CONTROLLER – INTEL 8257
Operation of 8257 DMA Controller

➢ Each channel of 8257 has two programmable 16-bit registers named as address
register and count register.

➢ Address register is used to store the starting address of memory location for DMA
data transfer.

➢ The address in the address register is automatically incremented after every

read/write/verify transfer.

➢ The count register is used to count the number of byte or word transferred by
DMA.

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PROGRAMMABLE DMA CONTROLLER – INTEL 8257
➢ In read transfer the data is transferred from memory to I/O device.

➢ In write transfer the data is transferred from I/O device to memory.

➢ Verification operations generate the DMA addresses without generating the DMA
memory and I/O control signals.

➢ The 8257 has two eight bit registers called mode set register and status register.

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 Microprocessor System
1 2

3 4

55 6
 Microprocessor System
8
7

9 10

11 12
 Microprocessor System
14
13

16
15

17 18
 Microprocessor System
20
19

21 22

23 24
 Microprocessor System
26
25

28
27

29 30
 Microprocessor System
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 Microprocessor System
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 Microprocessor System
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 Microprocessor System
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 Microprocessor System
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Microprocessor System68

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Thank you