‭1.‬ ‭List out the advantages of using UVM class library.

‬
‭●‬ ‭Reusability of components across projects.‬
‭●‬ ‭Simplified testbench architecture using standardized methodologies.‬
‭●‬ ‭Improved productivity through built-in automation and methodology support.‬
‭●‬ ‭Enhanced debug capabilities with built-in reporting and error handling‬
‭mechanisms.‬
‭2.‬ ‭How blocking transport is implemented in a communication?‬
‭●‬ ‭Blocking transport refers to a method where the caller waits until the‬
‭transaction is complete before proceeding.‬
‭●‬ ‭In SystemVerilog, this can be implemented using tasks or functions that‬
‭contain‬‭ @(posedge)‬‭or‬‭ @(negedge)‬‭events to synchronize‬‭the timing of‬
‭data transactions.‬
‭3.‬ ‭What are the basic components of transaction level verification environment?‬
‭●‬ ‭Sequencer: Manages the flow of transactions between sequencer and driver.‬
‭●‬ ‭Driver: Transfers transactions from sequencer to the DUT's interface.‬
‭●‬ ‭Monitor: Observes and verifies transactions on the DUT's interface.‬
‭●‬ ‭Scoreboard: Compares expected results with actual results to verify‬
‭correctness.‬
‭●‬ ‭Agent: Combines sequencer, driver, and monitor into a cohesive unit for a‬
‭specific interface.‬
‭4.‬ ‭Explain the operating modes of an agent.‬
‭●‬ ‭Active Mode‬‭: Initiates and drives transactions on‬‭the interface.‬
‭●‬ ‭Passive Mode‬‭: Monitors transactions on the interface‬‭without initiating them.‬
‭●‬ ‭Monitor Mode‬‭: Only monitors transactions without affecting‬‭the interface.‬
‭5.‬ ‭Define Virtual sequences.‬
‭●‬ ‭Virtual sequences in UVM are sequences that coordinate the execution of‬
‭other sequences.‬
‭●‬ ‭They provide a mechanism to orchestrate complex test scenarios by‬
‭controlling the flow of sequences and handling inter-sequence dependencies.‬
‭6.‬ ‭Explain the types of coverage methods.‬
‭●‬ ‭Functional Coverage‬‭: Tracks whether specific functionalities‬‭of the DUT‬
‭have been exercised.‬
‭●‬ ‭Code Coverage‬‭: Measures how much of the HDL source‬‭code has been‬
‭executed.‬
‭●‬ ‭Assertion Coverage‬‭: Ensures that assertions within‬‭the design have been‬
‭validated during simulation.‬
‭7.‬ ‭Draw the class collaboration diagram of the register model.‬
‭●‬ ‭In a register model, classes like‬‭ register‬ register_field‬
‭,‬‭ ‭,‬
register_block‬
‭ register_model‬‭collaborate to‬‭model the registers‬
‭, and‬‭
‭and their behaviors within the DUT.‬
‭8.‬ ‭What are Pre-defined Functional Coverage Type Identifiers?‬
‭●‬ ‭These are predefined types in UVM that represent common functional‬
‭coverage metrics, such as transaction coverage (‬‭ UVM_CVR_TRANSACTION‬ ‭),‬
‭toggle coverage (‬‭ UVM_CVR_TOGGLE‬ ‭), and assertion coverage‬
‭(‭ U
‬ VM_CVR_ASSERT‬ ‭).‬
‭●‬ ‭They provide a standardized way to specify coverage goals and report‬
‭coverage results in the verification environment.‬
‭9.‬ ‭Explain FIFO Control and Status Registers.‬
‭●‬ ‭FIFO control and status registers manage the operation of FIFOs in digital‬
‭systems.‬
‭●‬ ‭They include registers to control FIFO operations (e.g., write enable, read‬
‭enable) and registers to monitor FIFO status (e.g., full, empty, almost full,‬
‭almost empty).‬
‭10.‬‭What are the three levels of access protection in APB Protocol?‬
 ‭●‬ N ‭ o Protection (NP)‬‭: No access protection is implemented; any master can‬
‭access the slave at any time.‬
‭●‬ ‭Secure Access (SA)‬‭: Access is restricted based on security attributes or‬
‭modes.‬
‭●‬ ‭Non-secure Access (NS)‬‭: Access is granted without security constraints.‬
‭11.‬‭What is virtual class in UVM?‬
‭●‬ ‭In UVM, a virtual class is a class that serves as a base class for other‬
‭classes. It cannot be instantiated on its own but provides common‬
‭functionality and interfaces that can be inherited by other classes.‬
‭12.‬‭Give the difference between RTL and TLM.‬
‭●‬ ‭RTL (Register Transfer Level)‬‭: RTL refers to a level‬‭of abstraction in digital‬
‭design where the behavior of a circuit is described using registers, logic‬
‭gates, and their interconnections. It describes the hardware functionality at a‬
‭detailed level.‬
‭●‬ ‭TLM (Transaction Level Modeling)‬‭: TLM refers to a higher level of‬
‭abstraction where communication between hardware components or‬
‭subsystems is described in terms of transactions or messages. It focuses on‬
‭the interactions and timing between components rather than the internal‬
‭hardware details.‬
‭13.‬‭What are checkers in UVM?‬
‭●‬ ‭Checkers in UVM are components used to monitor and verify the behavior or‬
‭properties of signals, transactions, or interfaces in a design. They compare‬
‭expected behavior (specifications) with actual behavior (simulation results)‬
‭and report any discrepancies or errors.‬
‭14.‬‭Mention the use of driver and sequencer.‬
‭●‬ ‭Driver‬‭: In UVM, a driver is responsible for transferring‬‭transactions generated‬
‭by sequences to the interface of the DUT (Design Under Test). It converts‬
‭sequence items into protocol-specific signals that can be applied to the DUT.‬
‭●‬ ‭Sequencer‬‭: A sequencer manages the flow of transactions‬‭between‬
‭sequences and drivers. It receives requests for transactions from sequences,‬
‭selects the appropriate driver, and sends the transaction items to the driver‬
‭for execution.‬
‭15.‬‭What are the basis testbench components?‬
‭●‬ ‭Environment‬‭: Contains agents, scoreboard, and other‬‭testbench‬
‭components.‬
‭●‬ ‭Agents‬‭: Includes sequencers, drivers, monitors, and‬‭potentially other‬
‭components for interfacing with the DUT.‬
‭●‬ ‭Scoreboard‬‭: Compares expected results with actual‬‭results to verify the‬
‭correctness of the DUT's behavior.‬
‭●‬ ‭Sequences and Tests‬‭: Define the stimulus and test‬‭scenarios applied to the‬
‭DUT.‬
‭●‬ ‭Configuration Database‬‭: Manages the runtime configuration‬‭and settings of‬
‭testbench components.‬
‭16.‬‭How will you create a test class?‬
‭●‬ ‭To create a test class in UVM, you typically define a new class that inherits‬
‭from‬‭ uvm_test‬‭or a derived test class.‬
‭●‬ ‭Implement the‬‭ run_phase‬‭task or method to define the‬‭test scenario and‬
‭sequences to be executed during simulation.‬
‭●‬ ‭Optionally, configure and connect other testbench components such as‬
‭sequences, environment, and DUT interfaces within the test class.‬
‭17.‬‭What is UVM register layer?‬
‭●‬ ‭The UVM Register Layer provides a standardized methodology for modeling‬
‭and accessing registers and memories within a DUT.‬
 ‭●‬ I‭t includes classes such as‬‭ uvm_reg‬ uvm_reg_block‬
‭,‬‭ uvm_reg_file‬
‭,‬‭ ‭,‬
‭and‬‭ uvm_mem‬‭to model register hierarchies and behaviors.‬
‭●‬ ‭The UVM Register Layer facilitates tasks like read/write operations, bit-field‬
‭accesses, register verification, and automatic register model creation.‬
‭18.‬‭Define UVM sequence.‬
‭●‬ ‭In UVM, a sequence represents a sequence of transactions or operations that‬
‭are applied to the DUT.‬
‭●‬ ‭Sequences are typically used to generate stimulus, check corner cases, and‬
‭perform specific test scenarios.‬
‭●‬ ‭They can be customized with constraints, randomization, and synchronization‬
‭to ensure comprehensive verification of the DUT.‬
‭19.‬‭Where is APB protocol used?‬
‭●‬ ‭APB (Advanced Peripheral Bus) protocol is commonly used in low-power and‬
‭low-frequency applications for connecting low-bandwidth peripherals to a‬
‭microprocessor or microcontroller.‬
‭●‬ ‭It is often used in embedded systems for controlling and monitoring peripheral‬
‭devices such as sensors, actuators, and communication interfaces.‬
‭20.‬‭What is active agent and passive agent in UVM?‬
‭●‬ ‭Active Agent‬‭: An active agent initiates and drives‬‭transactions on the‬
‭interface of the DUT. It includes components like sequencers and drivers.‬
‭●‬ ‭Passive Agent‬‭: A passive agent monitors transactions on the interface‬
‭without initiating them. It typically includes components like monitors and‬
‭scoreboard for verification purposes.‬