Introduction To PLD
Introduction To PLD
(PLD)
Shridhar S. Dudam
Agenda
Introduction to PLD
SPLD
CPLD
FPGA
Xilinx FPGA Architecture
Standard ASIC
Logic
SPLDs
(PAL/PLA/GAL) CPLDs FPGAs
• Flexibility.
• In system programmability.
• Less project development time.
• Best prototyping solution.
• Cost effective solutions.
• Involves less risk.
• Design security.
• Consumes less board area.
• Reconfigurable computing.
• Best suits hardware verification of design.
PLD Fundamental
Xilinx
Altera
Lattice
Quicklogic
Xilinx FPGA Architecture
IOBs
Interface between the FPGA and the outside world
Programmable interconnect
Other resources
Memory
Multipliers
Bank 3
Bank 1
Bank 2
4 I/O Banks,
Support for
Up to eight on-chip all I/O Standards
Digital Clock Managers including
to support multiple PCI, DDR333,
system clocks RSDS, mini-LVDS
Transceivers (MGTs)
Fabric
• Supports 10 Gbps
standards
Up to 24 per device • IP-Immersion™ Fabric
• Active Interconnect™
• 18Kb Dual-Port RAM
• Xtreme™ Multipliers
• 16 Global Clock Domains
MGT MGT
• PowerPC 405 Core
• 300+ MHz / 450+ DMIPS
Performance
• Up to 4 per device
Programmable Logic Devices
44
Outline
Overview
Slice Resources
I/O Resources
Memory and
Clocking
Spartan-3,
Spartan-3E, and
Virtex-II Pro
Features
Virtex-4 Features
Summary
Programmable Logic Devices
45
Slices and CLBs
Each Virtex-II CLB COUT COUT
BUFT
contains four slices BUF T
Slice S3
Local routing provides
feedback between slices
Slice S2
in the same CLB, and it Switch SHIFT
Matrix
provides routing to
neighboring CLBs Slice S1
to general routing
CIN CIN
resources
Programmable Logic Devices
46
Simplified Slice Structure
Each slice has four
outputs
Two registered outputs, Slice 0
two non-registered outputs
PRE
Two BUFTs associated LUT Carry D
CE
Q
F8
MUXF7 outputs (from the CLB
above or below)
F5
Slice S3
MUXF6 combines slices S2
F6
and S3
F5
Slice S2
MUXF6 outputs
Slice S1
F5
Slice S0
F5
A S CO
DI
CY_MUX
CI
CY_XOR
MULT_AND
AxB
LUT
B LUT
each CLB CE
controls CLR
Can be synchronous or
asynchronous LDCPE
12 Cycles
Operation A Operation B
64
4 Cycles 8 Cycles
64
Operation C Operation D - NOP
3 Cycles 9 Cycles
Paths are Statically
Balanced
12 Cycles
18 x 18 Output
8 x 8 signed
Multiplier (36 bits)
12 x 12 signed
Data_B 18 x 18 signed
(18 bits)
pairs
Left-hand SLICEM Slice X1Y0
SHIFTIN
(Memory) Switch
Matrix
LUTs can be
configured as memory Slice X0Y1
or SRL16
Right-hand SLICEL
(Logic) Slice X0Y0 Fast Connects
Xesium Clocking
Advanced CLBs Technology
200K Logic Cells 500 MHz
Tri-Mode
Ethernet MAC
XtremeDSP™ 10/100/1000 Mbps
Technology Slices
256 18x18 GMACs
1 Gbps SelectIO™
PowerPC™ 405 ChipSync™ Source synch,
with APU Interface XCITE Active Termination
450 MHz, 680 DMIPS
SelectIO
240–960 240–896 320–640
RocketIO
N/A 0–24 Channels N/A
PowerPC
N/A N/A
1 or 2 Cores
Ethernet MAC
N/A N/A
2 or 4 Cores
Application Notes
www.xilinx.com Documentation Application
Notes
Education resources
Designing with the Virtex-4 Family course
Spartan-3E Architecture free Recorded e-Learning