BITS Pilani

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BITS Pilani DS Rao
Sequential ciruit
Pilani|Dubai|Goa|Hyderabad
Digital Logic Design

Synchronous
Sequential Logic

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Two Classification
1. Synchronous
• The state of the memory elements are updated with the
arrival of each pulse
• This type of logical circuit is also known as clocked
sequential circuits.
2. Asynchronous
• No clock behavior of an asynchronous sequential circuit
• depends upon the input signals at any instant of time and
the order in which the inputs change.
• Memory elements in asynchronous circuits are regarded
as time-delay elements

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Sequential Circuits
• Asynchronous
Inputs Outputs
Combinational
Circuit
Memory
Elements

• Synchronous

Inputs Outputs
Combinational
Circuit
Flip-flops
Clock

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Latches

A latch is a memory device that can

maintain a binary state indefinitely.
 Latches are, in fact, asynchronous
devices and they usually do not require a
clock to operate.
 Therefore, they are not directly used in
clocked synchronous sequential circuits.
 They rather to be used to construct flip-
flops.
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Latches

• SR Latch S R Q0 Q Q’
0 0 0 0 1 Q = Q0

R 0 0
Q

S Q
0 1

Initial Value

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Latches

• SR Latch S R Q0 Q Q’
0 0 0 0 1 Q = Q0
0 0 1 1 0 Q = Q0

R 0 1
Q

S Q
0 0

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Latches

• SR Latch S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1 Q=0
R 1 0
Q

S Q
0 1

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Latches

• SR Latch S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1 Q=0
R 1 1
Q
0 1 1 0 1 Q=0

S Q
0 0

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Latches

• SR Latch S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R 0
Q=0
0 0 1 1 0 1
Q 1 0 0 1 0 Q=1

S Q
1 1

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Latches

• SR Latch S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R 0
Q=0
1 0 1 1 0 1
Q 1 0 0 1 0 Q=1
1 0 1 1 0 Q=1

S Q
1 0

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Latches

• SR Latch S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R 1
Q=0
0 0 1 1 0 1
Q 1 0 0 1 0
Q=1
1 0 1 1 0
1 1 0 0 0 Q = Q’

S Q
1 10

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Latches

• SR Latch S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R 1
Q=0
10 0 1 1 0 1
Q 1 0 0 1 0
Q=1
1 0 1 1 0
1 1 0 0 0 Q = Q’
1 1 1 0 0 Q = Q’
S Q
1 0

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Latches

• SR Latch
S R Q
R Q No change
Q0
0 0
0 1 0 Reset
1 0 1 Set
S Q 1 1 Q=Q’=0 Invalid

S S R Q
Q
0 0 Q=Q’=1 Invalid
0 1 1 Set
1 0 0 Reset
R Q
1 1 Q0 No change
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Controlled Latches
• SR Latch with Control Input
R R S S
Q Q
C C
S Q R Q
S R

C S R Q
0 x x Q0 No change
1 0 0 Q0 No change
1 0 1 0 Reset
1 1 0 1 Set
1 1 1 Q=Q’ Invalid Indeterminate
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Controlled Latches

• D Latch (D = Data) Timing Diagram

D S C
Q
C D
R Q
Q

t
C D Q
Output may
0 x Q0 No change
change
1 0 0 Reset
1 1 1 Set

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Controlled Latches

• D Latch (D = Data) Timing Diagram

D S C
Q
C D
R Q
Q

C D Q Output may
0 x Q0 No change change
1 0 0 Reset
1 1 1 Set

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Master-Slave Flip-Flops
(Pulse Triggered Flip-Flops) start here

• Aside from latches, two categories of flip-

flops.
– Master-slave flip-flops (pulse-triggered flip-flops)
– Edge-triggered flip-flops
• Latches have immediate output response
(known as transparency)
• May be undesirable:
– May be necessary to sense the current state of a
flip-flop while allowing new state information to be
entered.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Master-Slave SR Flip-Flop

• Two sections, each capable of storing a binary symbol.

• First section is referred to as the master and the second
section as the slave.
• Information is entered into the master on one edge or
level of a control signal and is transferred to the slave on
the next edge or level of the control signal.
• Each section is a latch.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Master-Slave SR Flip-Flop

• C = 0:
– Master is disabled. Any changes to S,R ignored.
– Slave is enabled. Is in the same state as the master.
• C = 1:
– Slave is disabled (retains state of master)
– Master is enabled, responds to inputs. Changes in state of master are not reflected in
disabled slave.
• C = 0:
– Master is disabled.
– Slave is enabled and takes on new state of the master.
• Important: For short periods during rising and falling edges, both master
and slave are disabled.
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Edge-Triggered Flip-Flops
1. C = 0. Regardless of input at D,
outputs of gates 2,3 are 1. So
𝑆 = 𝑅 = 1. State of latch is held.
2. Assume D = 0: Output of gate 4 is 1,
output of gate 1 is 0. When C goes to
1: all inputs to gate 3 are 1, output
changes to 0. Output of gate 2
remains at 1 since output of gate 1 is
0. So 𝑆 = 1, 𝑅 = 0. Output of gate 3
(0) is fed to input of gate 4. Output
of gate 4, gate 1 not affected by
changes to D.
3. Assume C = 0, D = 1. Outputs of
gates 2,3, are 1. Output of gate 4 is
0, output of gate 1 is 1. When C goes
𝑆 𝑅 Latch
to 1: output of gate 2 is 0, output of
gate 3 remains at 1. So 𝑆 = 0, 𝑅 = 1.
Output from gate 2 is input to gates
1, 3 so their outputs remain at 1.
Changes in D have no affect on state
of flip-flop while C = 1.
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Timing Diagram

During setup and hold times 𝑡𝑠𝑢 , 𝑡ℎ with respect to the

triggering edge of the clock, D input must not change.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

JK Flip-Flop

J K Q(t+1)
0 0 Q(t) No change
0 1 0 Reset
1 0 1 Set
1 1 Q’(t) Toggle
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
JK Flip Flop Realised using D Flipflop

FF data Output D FF Q\JK 00 01 11 10

inputs inputs 0 1 1
Q(n) 1 1 1
J K Q(n+1) D
0 0 0 0 0
1 0 0 1 1 𝑫 = 𝑱𝑸′ + 𝑲′ 𝑸
0 1 0 1 1
1 1 0 1 1
0 0 1 0 0
1 0 1 0 0
0 1 1 1 1
1 1 1 0 0

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

J-K F.F timing diagram

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Flip-Flop Characteristic Tables

D Q D Q(t+1)
0 0 Reset
Q 1 1 Set

J K Q(t+1)
J Q 0 0 Q(t) No change
0 1 0 Reset
K Q 1 0 1 Set
1 1 Q’(t) Toggle

T Q T Q(t+1)
0 Q(t) No change
Q 1 Q’(t) Toggle
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Flip-Flop Characteristic Equations

D Q D Q(t+1)
0 0 Q(t+1) = D
Q 1 1

J K Q(t+1)
J Q 0 0 Q(t)
0 1 0 Q(t+1) = JQ’ + K’Q
K Q 1 0 1
1 1 Q’(t)

T Q T Q(t+1)
0 Q(t) Q(t+1) = T  Q
Q 1 Q’(t)
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Flip-Flop Characteristic Equations
Analysis / Derivation

T Q T Q(t+1) T\Q(t) 0 1
0 Q(t) 0 1
Q 1 Q’(t) 1 1

Q(t+1) = T  Q

Similarly
T Q(t) Q(t+1)
For J K Flip flop already derived
0 0 0 No change as
0 1 1 D= Q(t+1)= JQ’ + K’Q
1 0 1
1 1 0 Toggle
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Flip-Flops with Direct Inputs
Asynchronous Preset and Clear

Preset

PR PR’ CLR’ D CLK Q(t+1)

D Q 1 0 x x 0
0 1 x x 1
Q 1 1 0 0
CLR 1 1 1 1
Reset

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Thanks

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956