BITS Pilani R.K.

Tiwary
Pilani|Dubai|Goa|Hyderabad
CONTROL UNIT OPERATION
 The execution of an instruction involves the execution of a sequence of
substeps, generally called cycles
 The Fetch Cycle
 The Indirect Cycle
 The Interrupt Cycle
 The Execute Cycle
 The Instruction Cycle
 control unit of a processor performs two tasks:
 step through a series of micro-operations in the proper sequence
 generates the control signals

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

CONTROL UNIT OPERATION
 The control signals generated by the control unit cause the opening and
closing of logic gates, resulting in the transfer of data to and from
registers and the operation of the ALU
 technique for implementing a control unit
 hardwired implementation
 Microprogrammed control
 Micro-operations are a sequence of more fundamental operations
which constitute the operation cycle.
 A single micro-operation generally involves a transfer between registers,
a transfer between a register and an external bus, or a simple ALU
operation

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Micro-Operations

A computer executes a program

Fetch/execute cycle
Each cycle has a number of steps
Called micro-operations
Each step does very little
Atomic operation of CPU
micro-operations needed to perform the subcycles of the
instruction cycle.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Constituent Elements of Program Execution

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

The Fetch Cycle
 Memory Address Register (MAR)
▪ Connected to address bus
▪ Specifies address for read or write op
 Memory Buffer Register (MBR)
▪ Connected to data bus
▪ Holds data to write or last data read
Program Counter (PC)
▪ Holds address of next instruction to be fetched
 Instruction Register (IR)
▪ Holds last instruction fetched
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Executing an Instruction

 Fetch the contents of the memory location pointed

to by the PC. The contents of this location are
loaded into the IR (fetch phase).

IR ← [[PC]]

 Assuming that the memory is byte addressable,

increment the contents of the PC by 4 (Assume 4
Byte instruction).
PC ← [PC] + 4

 Carry out the actions specified by the instruction in

the IR (execution phase).
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Processor Organization

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Internal organization of the processor

o ALU
o Registers for temporary storage
o Various digital circuits for executing different micro
o operations.(gates, MUX,decoders,counters).
o Internal path for movement of data between ALU and
registers.
o Driver circuits for transmitting signals to external units.
o Receiver circuits for incoming signals from external
units.
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
PC:
 Keeps track of execution of a program
 Contains the memory address of the next instruction to be fetched
and executed.
MAR:
Holds the address of the location to be accessed.
I/P of MAR is connected to Internal bus and an O/p to external bus.
MDR:
Contains data to be written into or read out of the addressed location.
IT has 2 inputs and 2 Outputs.
Data can be loaded into MDR either from memory bus or from internal
processor bus.
The data and address lines are connected to the internal bus via MDR and
MAR
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Registers:
The processor registers R0 to Rn-1 vary considerably from one
processor to another.
Registers are provided for general purpose used by programmer.
Special purpose registers-index & stack registers.
Registers Y,Z &TEMP are temporary registers :used by processor
during the execution of some instruction.
Multiplexer:
Select either the output of the register Y or a constant value 4 to be
provided as input A of the ALU.
Constant 4 is used by the processor to increment the contents of PC.
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
ALU:
Used to perform arithmetic and logical operation.
Data Path:
The registers, ALU and interconnecting bus are collectively
referred to as the data path.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Register Transfers
 The input and output gates
for register Ri are controlled
by signals in Rin and Riout .
 Rin Is set to1 – data available
on common bus are loaded
into Ri.
 Riout Is set to1 – the contents
of register are placed on the
bus.
 Riout Is set to 0 – the bus can
be used for transferring data
from other registers .
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Data transfer between two registers:

EX:

Transfer the contents of R1 to R4.

1. Enable output of register R1 by setting R1out=1. This places the contents

of R1 on the processor bus.

2. Enable input of register R4 by setting R4in=1. This loads the data from

the processor bus into register R4.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Fetch Sequence (symbolic)

t1: MAR <- (PC)

t2: MBR <- (memory)
PC <- (PC) +n
t3: IR <- (MBR)
(tx = time unit/clock cycle)
or
t1: MAR <- (PC)
t2: MBR <- (memory)
t3: PC <- (PC) +n
IR <- (MBR)
Assume n byte instruction

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Rules for Clock Cycle Grouping

Proper sequence must be followed

▪ MAR <- (PC) must precede MBR <- (memory)
Conflicts must be avoided
▪ Must not read & write same register at same time
▪ MBR <- (memory) & IR <- (MBR) must not be in same
cycle
Also: PC <- (PC) +n involves addition
▪ Use ALU
▪ May need additional micro-operations

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Sequence of Events, Fetch Cycle

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Interrupt Cycle
t1: MBR <-(PC)
t2: MAR <- save-address
PC <- routine-address
t3: memory <- (MBR)
This is a minimum
▪ May be additional micro-ops to get addresses
▪ N.B. saving context is done by interrupt handler routine, not micro-
ops

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

The Execute Cycle

Different for each instruction

e.g. ADD R1,X - add the contents of location X to Register
1 , result in R1
t1: MAR <- (IRaddress)
t2: MBR <- (memory)
t3: R1 <- R1 + (MBR)
Note no overlap of micro-operations

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Performing an Arithmetic or Logic Operation
 The ALU is a combinational circuit
R3= R1+R2
that has no internal storage.
 ALU gets the two operands from
MUX and bus. The result is
temporarily stored in register Z.
 What is the sequence of
operations to add the contents of
register R1 to those of R2 and store
the result in R3?
1. R1out, Yin
2. R2out, SelectY, Add, Zin
3. Zout, R3in
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Performing an Arithmetic or Logic Operation
Step 1: Output of the register R1 and
R3= R1+R2
input of the register Y are enabled,
causing the contents of R1 to be
transferred to Y.
Step 2: The multiplexer’s select signal is
set to select Y causing the multiplexer to
gate the contents of register Y to input A
of the ALU. At the same time contents of
R2 are gated into the bus and hence to
input B
Step 3: The contents of Z are transferred
to the destination register R3.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Register Transfers
Input and output gating for one register bit.

Rin clk Q

0 Q
Io Q
1 B
B

When Rout=1 B=Q. otherwise in

high impedance state

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Fetching a Word from Memory
. Connection and control signals for register MDR

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Execution of a Complete Instruction

 Add R1, (R3)

 Fetch the instruction
 Fetch the first operand (the contents of the memory location
pointed to by R3)
 Perform the addition
 Load the result into R1

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Execution of a Complete Instruction
Add (R3), R1

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Data Flow, Fetch Cycle
Add (R3), R1

WMFC: Wait for memory function check to accommodate the

variability in response time, The addressed device sets this signal to 1
to indicate that contents of the specified location has been read

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Example
Write the sequence of control steps needed to add the immediate number to
R1 as per the bus structure shown

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Example

1. PCout, MARin, Read, Select4, Add, Zin

2. Zout, PCin, Yin, WMFC
3. MDRout, IRin
4. PCout, MARin, Read, Select4, Add, Zin
5. Zout, PCin, Yin
6. R1out, Yin, WMFC
7. MDRout, SelectY, Add, Zin
8. Zout, R1in, End

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Execute Cycle (ISZ)

ISZ X - increment and skip if zero

▪ t1: MAR <- (IRaddress)
▪ t2: MBR <- (memory)
▪ t3: MBR <- (MBR) + 1
▪ t4: memory <- (MBR)
▪ if (MBR) == 0 then PC <- (PC) + 1
Notes:
▪ if is a single micro-operation
▪ Micro-operations done during t4

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Execute Cycle (BSA)

BSA X - Branch and save address

▪ Address of instruction following BSA is saved in X
▪ Execution continues from X+1
▪ t1: MAR <- (IRaddress)
▪ MBR <- (PC)
▪ t2: PC <- (IRaddress)
▪ memory <- (MBR)
▪ t3: PC <- (PC) + 1

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Multiple-Bus Organization
• Allow the contents of two different
registers to be accessed
simultaneously and have their
contents placed on buses A and B.

• Allow the data on bus C to be

loaded into a third register during the
same clock cycle.

• Incrementer unit.

• ALU simply passes one of its two

input operands unmodified to bus C

 control signal: R=A or R=B

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Instruction Cycle

Each phase decomposed into sequence of elementary micro-operations

E.g. fetch, indirect, and interrupt cycles
Execute cycle
▪ One sequence of micro-operations for each opcode
Assume new 2-bit register
▪ Instruction cycle code (ICC) designates which part of cycle processor is
in
– 00: Fetch
– 01: Indirect
– 10: Execute
– 11: Interrupt

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Flowchart for Instruction Cycle

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Requirements for CONTROL OF THE
PROCESSOR

the following three-step process leads to a characterization of the control

unit
1. Define the basic elements of the processor.
2. Describe the micro-operations that the processor performs.
3. Determine the functions that the control unit must perform to cause
the micro-operations to be performed
4. The control unit performs two basic tasks:
• Sequencing: The control unit causes the processor to step through a
series of micro-operations in the proper sequence, based on the
program being executed.
• Execution: The control unit causes each micro-operation to be
performed
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Control Unit
Clock
Block Diagram of the Control Unit
▪ One micro-instruction (or set of
parallel micro-instructions) per clock
cycle
Instruction register
▪ Op-code for current instruction
▪ Determines which micro-instructions
are performed
Flags
▪ State of CPU
▪ Results of previous operations
From control bus
▪ Interrupts
▪ Acknowledgements
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Example Control Signal Sequence - Fetch

MAR <- (PC)

▪ Control unit activates signal to open gates between PC and MAR
MBR <- (memory)
▪ Open gates between MAR and address bus
▪ Memory read control signal
▪ Open gates between data bus and MBR

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Data Paths and Control Signals

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Hardwired Implementation (1)

Control unit inputs

Flags and control bus

– Each bit means something

Instruction register

– Op-code causes different control signals for each different

instruction

– Unique logic for each op-code

– Decoder takes encoded input and produces single output

– n binary inputs and 2n outputs

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Hardwired Implementation (2)

Clock

– Repetitive sequence of pulses

– Useful for measuring duration of micro-ops

– Must be long enough to allow signal propagation

– Different control signals at different times within instruction cycle

– Need a counter with different control signals for t1, t2 etc.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Control Unit with Decoded Inputs

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Detailed Block Description

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Generating Zin
Control sequence for an unconditional branch instruction

Step Action
Add (R3), R1
1 PCout , MAR in , Read, Select4,Add, Z in
2 Zout , PCin , Yin , WMF C
3 MDR out , IR in
4 Offset-field-of-IRout, Add, Z in
5 Z out , PCin , End

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Generating Zin

Branch Add

T4 T6

T1

Zin = T1 + T6 • ADD + T4 • BR + …

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Problems With Hard Wired Designs

 Complex sequencing & micro-operation logic

 Difficult to design and test
 Inflexible design
 Difficult to add new instructions

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Generating End

End = T7 • ADD + T5 • BR + (T5 • N + T4 • N) • BRN +…

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Microprogrammed Control
Control signals are generated by a program similar to machine language programs.
Control Word (CW); microroutine; microinstruction

Add (R3), R1

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Micro-programmed Control Implementation

 Use sequences of instructions to control complex operations

Called micro-programming or firmware
 All the control unit does is generate a set of control signals
 Each control signal is on or off
 Represent each control signal by a bit
 Have a control word for each micro-operation
 Have a sequence of control words for each machine code
instruction
 Add an address to specify the next micro-instruction,
depending on conditions
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Micro-programmed Control Implementation

Today’s large microprocessor

▪ Many instructions and associated register-level hardware
▪ Many control points to be manipulated
This results in control memory that
▪ Contains a large number of words
– corresponding to the number of instructions to be
executed
▪ Has a wide word width
– Due to the large number of control points to be
manipulated
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Micro-program
 Word Length Based on 3 factors
▪ Maximum number of simultaneous micro-operations supported
▪ The way control information is represented or encoded
▪ The way in which the next micro-instruction address is specified
 Types
Each micro-instruction specifies single (or few) micro-operations to be
performed
▪ (vertical micro-programming)
Each micro-instruction specifies many different micro-operations to be
performed in parallel
▪ (horizontal micro-programming)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Micro-program
 Vertical Micro-programming
 Width is narrow
 n control signals encoded into log2 n bits
 Limited ability to express parallelism
 Considerable encoding of control information requires external
memory word decoder to identify the exact control line being
manipulated
 Horizontal Micro-programming
 Wide memory word
 High degree of parallel operations possible
 Little encoding of control information

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Typical Microinstruction Formats

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Micro-program Organization
ofControl Memory
Compromise

 Divide control signals into

disjoint groups
 Implement each group as
separate field in memory word
 Supports reasonable levels of
parallelism without too much
complexity

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956