2EC201

Digital Logic Design

Lecture : Verilog Language

 Outline
▪ Lexical Conventions in Verilog HDL
▪ Whitespace, comments, number
specification, string, operators, identifiers
▪ Logic Values
▪ Data Types in Verilog HDL
➢ Value set and strengths
➢ Nets and Registers
➢ Vectors
➢ Integer, Real, and Time Register Data Types
➢ Arrays, Memories, Parameters and Strings

2
Lexical Conventions
in
Verilog HDL
 Lexical Conventions
❖ Very similar to C
o Verilog is case-sensitive
o All keywords are in lowercase
o A Verilog program is a string of tokens which
can be:
▪ Whitespace
▪ Comments
▪ Numbers
▪ Strings
▪ Keywords
▪ Identifiers
4
 Lexical Conventions (cont’d)
❖Whitespace ❖Comments
o Blank space (\b) o Used for readability and
o Tab (\t) documentation
o Newline (\n) o Just like C:
// single line comment
/* multi-line comment */
❖ Whitespace is ignored
in Verilog except in
strings

5
 Lexical Conventions (cont’d)
❖ Number Specification
o Sized numbers
o Unsized numbers
o Unknown and high-impedance values
o Negative numbers

6
 Lexical Conventions (cont’d)
❖Sized numbers
o General syntax: <size>’<base><number>
▪ <size> :
number of bits (in decimal)
▪ <base> :
– d or D for decimal (radix 10)
– b or B for binary (radix 2)
– o or O for octal (radix 8)
– h or H for hexadecimal (radix 16)
▪ <number> :
is the number in radix <base>
▪ Examples:
– 4’b1111
– 12’habc
– 16’d255

7
 Lexical Conventions (cont’d)
❖Unsized numbers
o Default base is decimal
o Default size is at least 32
o Examples:
▪ 23232
▪ ’habc
▪ ’o234
o Examples:
▪ 23232 //32-bit decimal number
▪ ’habc //32-bit hex number
▪ ’o234 //32-bit octal number
8
Lexical Conventions (cont’d)
❖ X or Z values
o Unknown value: lowercase x
▪ 4 bits in hex, 3 bits in octal, 1 bit in
binary
o High-impedance value: lowercase z
▪ 4 bits in hex, 3 bits in octal, 1 bit in
binary

o Examples:
▪ 6’ox //this is 6-bit octal no -> xxxxxx

9
 Value Set

Value level HW Condition

0 Logic zero, false
1 Logic one, true
x Unknown
z High imp., floating

10
High Impedance: Logic

11
 Lexical Conventions (cont’d)
❖ Negative numbers
o Put the sign before the <size>
o Two’s complement is used to store the value
o Examples:
▪ -6’d3 //6-bit negative no 2’s
complement form
▪ 4’d-2 // illegal
▪ -6’sd3 //used for performing signed
integer math

12
 Lexical Conventions (cont’d)
❖ Strings
o Sequence of character
o As in C, use double-quotes in single line
without carriage return
o Examples:
▪ “Hello world!”
▪ “a / b” //5-character

14
 Lexical Conventions (cont’d)
❖ Operators
o Unary
a = ~b;
o Binary
a = b && c;
o Ternary
a = b ? c : d; // the only ternary operator

15
Operators

16
Keywords

17
Data Types in Verilog HDL
 Data Types
❖ Value set and Strength levels
❖ Nets and Registers
❖ Vectors
❖ Integer, Real, and Time Register Data Types
❖ Arrays
❖ Memories
❖ Parameters
❖ Strings

19
 Value Set
❖ Hardware modeling requirements
o Value Level – Verilog supports - 4
o Value Strength – Verilog supports – 8
▪ Used to resolve conflict between
drivers of different strength
▪ Used to accurately model
– Signal contention
– MOS devices
– Dynamic MOS
– Other low-level details/devices

20
 Net Data Type
❖ Used to represent connections between HW elements
o Values continuously driven on nets
▪ Continuous assignment (assign)
▪ Module or gate instantiation (output ports)
❖ Keyword: wire
o Default: One-bit values
▪ unless declared as vectors
o Default value: z
o Examples
▪ wire a;
▪ wire b, c;
▪ wire d=1’b0; //net d fixed to logic value 0

21
 Register Data Types
❖ Registers represent data storage elements
o Retain value until next assignment
o Similar to “variables” in other high level language
o NOTE: this is not a hardware register or flipflop
o Keyword: reg
o Default value: x
o Example:
reg reset;
initial
begin
reset = 1’b1;
#100 reset=1’b0;
End
22
Register Data Types (continue)

❖ Registers can also be declared as signed

variable
❖ Such registers can be used for signed
arithmetic
❖ Example:
o reg signed [63:0] m //64-bit signed value

23
 Vectors
❖ Vector ≡ Multiple-bit width data
❖ Applicable to both net and register data types

❖ Syntax:
o wire/reg [msb_index : lsb_index] data_id;
❖ Example
wire a;
wire [7:0] bus;
wire [31:0] busA, busB, busC;
reg clock;
reg [0:40] virtual_addr;

24
 Vectors( cont’d) Variable Vector Part Select

❖ Consider
wire [7:0] bus;
wire [31:0] busA, busB, busC;
reg [0:40] virtual_addr;

❖ Bit-select and part-select allowed:

busA[7]
bus[2:0] // three least-significant bits of bus
bus[0:2] // illegal
virtual_addr[0:1] /* two most-significant bits * of virtual_addr */

25
26
 Vectors( cont’d) Variable Vector Part Select

o reg [255:0] data1; //Little endian notation

o reg [0:255] data2; //Big endian notation
o reg [7:0] byte;

data1 255 to 248 …. 31 to 24 …. 7 to 0

//Using a variable part select, one can choose parts
o byte = data1[31-:8]; //starting bit = 31, width =8 => data1[31:24]
o byte = data1[24+:8]; //starting bit = 24, width =8 => data1[31:24]
o byte = data2[31-:8]; //starting bit = 31, width =8 => data2[24:31]
o byte = data2[24+:8]; //starting bit = 24, width =8 => data2[24:31]

data2 0 to 7 …. 24 to 31 …. 248 to 255

27
 Vectors( cont’d) Variable Vector Part Select
//The starting bit can also be a variable. The width has
//to be constant. Therefore, one can use the variable
//part select in a loop to select all bytes of the vector.

for (j=0; j<=31; j=j+1)

byte = data1[(j*8)+:8];

//Sequence is [7:0], [15:8]... [255:248]

//Can initialize a part of the vector data1 [(byteNum*8)+:8] = 8'b0;

//If byteNum = 1, clear 8 bits [15:8]

28
 Examples: Nets and Registers
 Wires and registers can be bits, vectors,
and arrays

wire a; // Simple wire

tri [15:0] dbus; // 16-bit tristate bus
tri #(5,4,8) b; // Wire with delay
reg [-1:4] vec; // Six-bit register

integer imem[0:1023]; // Array of 1024 integers

reg [31:0] dcache[0:63]; // A 32-bit memory

29
 Register Data Types (cont’d)
❖ Integer
o Keyword: integer
o Very similar to a vector of reg
▪ For manipulating quantities
▪ integer variables are signed numbers
▪ reg vectors are unsigned numbers, unless
specified
– reg signed [63:0] m; // 64 bit signed value
o Bit width: implementation-dependent (at least 32-bits)
▪ Designer can also specify a width:
integer [7:0] tmp;
o Examples:
integer counter;
Initial
counter = -1;
30
 Register Data Types (cont’d)
❖ Real
o Keyword: real
o Real no constant and real register
o Values:
▪ Decimal notation: 12.24
▪ Scientific notation: 3e6 (=3x106)
▪ Default value: 0

31
 Register Data Types (cont’d)
❖ Real
o Cannot have range declaration
o When assigned to integer => the real no is
rounded off to the nearest integer
o Example:
real delta;
initial
begin
delta = 4e10;
delta = 2.13;
End

integer i;
initial
i = delta; // i gets the value 2 (rounded value of 2.13)

32
 Register Data Types (cont’d)
❖ Time
o Verilog simulation is done with respect to simulation
time
o Used to store values of simulation time
o time register data type
o Keyword: time
o Bit width: implementation-dependent (at least 64)
o $time system function gives current simulation time
o Example:
time save_sim_time;
initial
save_sim_time = $time;

33
 Arrays
❖ Data types: wire, reg, integer, time,
real, realtime and vector register
etc..
❖ Single dimensional array
❖ Multi-dimensional array is also possible
❖ Syntax:
<data_type> <array_var_name> [start_idx : end_idx]
[start_idx : end_idx] ...
[start_idx : end_idx];
❖ Access:
<array_name> [<subscrip/index>]
For multidimensional indexes for each dimension

34
 Arrays
❖ Examples:
integer count [0:7]; //array of 8 count variable
reg bool [31:0]; // array of 32 one-bit boolean
time chk_point [1:100];
integer matrix[4:0][0:16]; //two dimentional
reg [4:0] port_id [0:7];
reg [63:0] array_4d [15:0][7:0][7:0][255:0];
wire w_array1[7:0][5:0]; //array of single bit wires
wire [7:0] w_array2 [5:0]; //array of 8-bit vector wire
❖ Difference between vectors and arrays??
❖ Do not confuse: array vs register vector

35
 Arrays (cont’d)
❖ Examples (cont’d)
integer count[0:7];
time chk_point[1:100];
reg [4:0] port_id[0:7];
integer matrix[4:0][0:16];
reg [63:0] array_4d[15:0][7:0][7:0][255:0];

count[5] = 0;
chk_point[100] = 0;
port_id[3] = 0;
matrix[1][0] = 33559;
array_4d[0][0][0][0][15:0] = 0;

36
 Memories
❖ RAM, ROM and register-files used many times
in digital systems
❖ Modeled as a one-dimensional array of
registers
❖ Memory = array of registers (register data
type) in Verilog
❖ Word = an element of the array
o Can be one or more bits

37
 Memories (continue..)
❖ Examples:
reg membit [0:1023];
reg [7:0] membyte[0:1023];

membyte[511] //fetches 1 byte word addr:511

❖ Note the difference (as in arrays):

❖ n 1-bit register Vs one n-bit register
reg membit[0:127];
reg [0:127] register;

38
 Have you learned this topic?
❖ Various data types
o 4-valued logic: 0, 1, x, z
o Strength levels
o Register vs. Net data types
▪ reg, integer, real, time register data
types
▪ wire data type
o Vectors
o Arrays

39