Combinational circuit Introduction ‘The combinational circuit consist of logic gates whose outputs at any time is determined directly from the present combination of input without any regard to the previous input. A combinational circuit performs a specific information processing operation fully specified logically by a set of Boolean functions. A combinatorial circuit is a generalized gate. In general such a circuit has m inputs and n outputs, Such a circuit ean always be constructed as n separate combinatorial circuits, each with exactly one output. For that reason, some texts only discuss combinatorial circuits with exactly one output. In reality, however, some important sharing of intermediate signals may take place if the entire n-output circuit is constructed at once. Such sharing can significantly reduce the number of gates required to build the circuit, When we build a combinatorial circuit from some kind of specification, we always try to make it as good as possible. ‘The only problem is that the definition of "as good as possible" may vary greatly. In some applications, we simply want to minimize the number of gates (or the number of transistors, really). In other, we might be interested in as short a delay (the time it takes a signal to traverse the circuit) as possible, or in as low power consumption as possible, In ‘general, a mixture of such criteria must be applied. Describing existing circuits using Truth tables To specify the exact way in which a combinatorial circuit works, we might use different methods, such as logical ‘expressions or truth tables. A truth table is @ complete enumeration of all possible combinations of input values, cach one with its associated output value, ‘When used to describe an existing circuit, output values are (of course) either 0 or 1. Suppose for instance that we wish to make a truth table for the following circuit: % a - b All we need to do to establish a truth table for this circuit is to compute the output value for the circuit for each possible ‘combination of input values. We obtain the following truth table: ‘AF. Kana Digital Logic Design. Page 27Specifying circuits to build ‘When used as a specification for a circuit, a able may have some output values that are not specified, pethaps because the corresponding combination of input values can never occur in the particular application. We can indicate such unspecified output values with a dash - For instance, let us suppose we want a citcuit of four inputs, interpreted as two nonnegative binary integers of two binary digits each, and two outputs, interpreted as the nonnegative binary integer giving the quotient between the two input numbers. Since division is not defined when the denominator is zero, we do not care what the output value is in this case, Of the sixteen entries in the truth table, four have a zero denominator, Here is the truth table: x1 x0 yl yO|z1 20 Unspecified output values like this can greatly decrease the number of circuits necessary to build the circuit. The reason is simple: when we are free to choose the output value in a particular situation, we choose the one that gives the fewest total number of gates, Circuit minimization is a difficult problem from complexity point of view. Computer programs that try to optimize circuit design apply a number of heuristics to improve speed. In this course, we are not concerned with optimality. We are therefore only going to discuss a simple method that works for all possible combinatorial circuits (but that can waste large numbers of gates). A separate single-output circuit is built for each output of the combinatorial circuit. ‘Our simple method starts with the truth table (or rather one of the acceptable truth tables, in case we have a choice). Our circuit is going to be a two-layer circuit. The first layer of the circuit will have at most 2" AND-gates, each with n inputs (where » is the number of inputs of the combinatorial circuit), The second layer will have a single OR-gate with as many inputs as there are gates in the first layer, For each line of the truth table with an output value of 1, we put down a AND- ‘gate with » inputs. For each input entry in the table with a I in it, we connect an input of the AND-gate to the corresponding input. For each entry in the table with a 0 in it, we connect an input of the AND-gate to the corresponding input inverted. ‘The output of each AND-gate of the fist layer is then connected to an input of the OR-gate of the second layer. ‘As an example of our general method, consider the following truth table (where a - indicates that we don't care what value is chosen): ‘AF. Kana Digital Logic Design. Page 28xyz|ab 000|-0 oor o1ofi- 01100 100/01 101|0- 110 11110 ‘The first step is to arbitrarily choose values for the undefined outputs. With out simple method, the best solution is to choose a 0 for cach such undefined output. We get this table: xyzlab 900]00 oori11 010/10 011/00 100/01 101]00 110]00 1itfio Now, we have to build two separate single-output circuits, one forthe a column and one forthe b column, Aax'y'zix'yz!txyz, Bex'yzexy'z) For the first column, we get three 3-input AND-gates in the first layer, and a 3-input OR-gate in the second layer. We get three AND -gates since there are three rows in the a column with a value of 1, Each one has 3-inputs since there are three inpuls, x, y, and z of the circuit. We get a 3-input OR-gate in the second layer since there are three AND -gates in the first layer, Here is the complete circuit for the first column: For the second column, we get two 3-input AND -gates in the first layer, and a 2-input OR-gate in the second layer. We get two AND-gates since there are two rows in the b column with a value of 1. Each one has 3-inputs since again there are three inputs, x, y, and z of the circuit. We get a 2-input AND-gate in the second layer since there are two AND-gales in the first layer. Here is the complete circuit for the second column: AF. Kana Digital Logic Design. Page 29Now, all we have to do is to combine the two circuits into a single one: in > While this circuit works, it is not the one with the fewest number of gates. In fact, since both output columns have a 1 in the row correspoding to the inputs 0 0 1, itis clear that the gate for that row can be shared between the two subeireuits x oy og In some cases, even smaller circuits can be obtained, if one is willing to accept more layers (and thus a higher circuit delay), ‘AF. Kana Digital Logic Design. Page 30Boolean functions Operations of binary variables can be described by mean of appropriate mathematical function called Boolean function. A Boolean function define a mapping from a set of binary input values into a set of output values. A Boolean funetion is formed with binary variables, the binary operators AND and OR and the unary operator NOT. For example , a Boolean function f(x, %2%3,..--.%,) =y defines a mapping from an arbitrary combination of binary input values (X),.2%5-1002%q) into a binary value y. a binary function with n input variable can operate on 2° distinets values, Any such function can be described by using a truth table consisting of 2" rows and n columns. The content of this table are the values produced by that function when applied to all the possible combination of the n input variable, Example ‘The function f, representing x.y, that is f{x,y)"xy. Which mean that f=1 ifx=1 and y=1 and £0 otherwise. For cach rows of the table, there is a value of the function equal to 1 or 0. The function f is equal to the sum of all rows that gives a value of 1 A Boolean function may be transformed from an algebraic expression into a logic diagram composed of AND, OR and NOT gate, When a Boolean function is implemented with logic gates, each literal in the function designates an input to a gate and each term is implemented with a logic gate. e.g Complement of a function ‘The complement of a function F is F” and is obtained from an interchange of 0's to 1s and 1’s to O's in the value of F. the complement of a function may be derived algebraically trough De Morgan’s theorem (A8BICH...)'= ABC. (ABC....'= A= BC ‘The generalized form of de Morgan's theorem state that the complement of function is obtained by interchanging AND and OR and complementing each literal. FeX'YZ'4 Po(XYZ4X'YZY =(XYZY(XYZ! ZIV XML) (XYZ XHVHZ) ‘AF. Kana Digital Logic Design. Page 31Canonical form(Minterns and Maxterms ) A binary variable may appear either in it normal form or in it complement form . consider two binary variables x and y combined with AND operation, Since each variable may appears in either form there are four possible combinations: xy, x'y, xy'xy. Each of the term represent one distinct area in the Venn diagram and is called minterm or a standard product. With n variable, 2° minterms can be formed. Ina similar fashion, n variables forming an OR term provide 2° possible combinations called maxterms or standard sum, Each maxterm is obtained from an OR term of the n variables, with cach variable being primed if the corresponding bit is | and un-primed if the corresponding bit is 0, Note that cach maxterm is the complement of its corresponding minterm and vice versa. X[¥|Z | Minterm | maxterm 0 [010 [xyz | X+ytz 0 fo 1 [xyz of 0 [x yz" of 1 [xy 1010 [xyz 1/01 [xyz To [xyz Th [i [xyz A Boolean function may be expressed algebraically from a given truth table by forming a minterm for each combination of variable that produce a I and taken the OR of those terms, Similarly, the same function can be obtained by forming the maxterm for each combination of variable that produces 0 and then taken the AND of those term, Itis sometime conve jent to express the bolean function when itis in sum of minterms, in the following notation: F(X,Y,Z)-X(1,4,5,6,7) . the summation symbol, stands for the ORing of the terms; the number follow ing it are the minterms of the function. The letters in the parenthesis following F form list of the variables in the order taken when the minterm is converted to an AND term, 80, FOX Y,Z)-L(1,4,5,6,7) = XVZERY'ZAXY ZAXVZ XYZ Sometime it is convenient to express a Boolean function in its sum of minterm. If itis not in that case, the expression is ‘expanded into the sum of AND term and if there is any missing variable, it is ANDed with an expression such as xx" where x is one of the missing variable, To express a Boolean function as a product of maxterms, it must first be brought into a form of OR terms. This can be done by using distributive law x+xz=(x+y)(xtz). then if there is any missing variable, say x in each OR term is ORded with xx’ 4g, represent F=xy-x'z as a product of maxterm (xy +x’Yxytz) Cohx Wy tx Woctayytz) (ytx"xtzytz) ‘Adding missing variable in cach term (ytx)§ x'tytzz! ae'tytz)( xtytz) (wiz) xtztyy’ xytaiixty't2) ‘AF. Kana Digital Logic Design. Page 32(izi= yhztax! ~(xtyi2\(x'tyi2) F> ( xtyta)( xty'tz) (x'tyt)(x"4y42) ‘A convenient way to express this function is as follow Fexys2)= [1 (0.2455) Standard form Another way to express a boolean function is in satndard form. Here the term that form the function may contains one, ‘two or nay number of literals. There are two types of standard form. The sum of product and the product of sum. ‘The sum of product(SOP) is a Boolean expression containing AND terms called product term of one or morc literals cach, The sum denotes the ORing of these terms eg, Foxtay'tx'yz the product of sum (POS)is a Boolean expression containing OR terms called SUM terms. Each term may have any number of literals. The product denotes the ANDing of these terms og. Fexixty)x'ty-2) 4 boolean function may also be expressed in a non standard form. In that case, distributive law can be used fo remove the parenthesis Foqytewyx'y't2'w) = xye'y't2w)taw(n'y tw) Xyx'y tayz'w! dawx'y! ¢2welw xyz'w'tawx'y! ‘A Boolean equation can be reduced to a minimal number of literal by algebraic manipulation. Unfortunately, there are no specific rules to follow that will guarantee the final answer. The only methods is to use the theorem and postulate of Boolean algebra and any other manipulation that becomes familiar Describing existing circuits using Logic expressions To define what a combinatorial circuit does, we can use a logic expression ot an expression for short. Such an (sometimes with suffixes) as names of inputs and ‘outputs, and the operators +, . and a horizontal bar or a prime (which stands for not). As usual, multiplication is expression uses the two constants 0 and 1, variables such as x, yank considered to have higher priority than addition, Parentheses are used to modify the priority. If Boolean functions in either Sum of Product or Product of Sum forms can be implemented using 2-Level implementations, For SOP forms AND gates will be in the first level and a single OR gate will be in the second level. For POS forms OR gates will be in the first level and a single AND gate will be in the second level. ‘Note that using inverters to complement input variables is not counted as a level ‘AF. Kana Digital Logic Design. Page 33,Examples: (XH YYEXZX(YZ)" ‘The equation is neither in sum of product nor in product of sum. The implementation is as follow , pe a Le XXKAXK, The equation is_in sum of product. The implementation is in 2-Levels. AND gates form the first level and a single OR ate the second level. 4 i: (X+1(¥+02) The equation is neither in sum of product nor in product of sum. The implementation is as follow Power of logic expressions A valid question is: can logic expressions describe all possible combinatorial eircuits?. The answer is yes and here is why: You can trivially convert the truth table for an arbitrary circuit into an expression. The expression will be in the form of ‘a sum of products of variables and there inverses. Each row with output value of | of the truth table corresponds to one term in the sum. In such a term, a variable having a | in the truth table will be uninverted, and a variable having a 0 in the truth table will be inverted. ‘AF. Kana Digital Logic Design. Page 34Take the following truth table for example: xyzlf 000/0 o01]0 O10tL O11|O 100/1 101]0 110]0 Wit ‘The corresponding expression is: XVZ+XYZ4XYZ Since you can describe any combinatorial circuit with a truth table, and you can describe any truth table with an expression, you can describe any combinatorial circuit with an expression, Simplicity of logic expressions There are many logic expressions (and therefore many circuits) that correspond to a certain truth table, and therefore to certain function computed, For instance, the following two expressions compute the same function: x(YZ) XY+XZ, The left one requires two gates, onc and-gate and one or-gate. The second expression requires two and-gates and one or-gate. It seems obvious that the first one is preferable to the second one. However, this is not always the case. It is not always true that the number of gates is the only way, nor even the best way, to determine simplicity We have, for instance, assumed that gates are ideal. In reality, the signal takes some time to propagate through a gate. ‘We call this time the gate delay. We might be interested in circuits that minimize the total gate delay, in other words, circuits that make the signal traverse the fewest possible gates from input to output. Such circuits are not necessarily the same ones that require the smallest number of gates. Circuit minimization ‘The complexity of the digital logic gates that implement a Boolean function is directly related to the complexity of the algebraic expression from which the function is implemented. Although the truth table representation of a function is unique, it can appear in many different forms when expressed algebraically. Simplification through algebraic manipulation A Boolean equation can be reduced to a minimal number of literal by algebraic manipulation as stated above. Unfortunately, there are no specific rules to follow that will guarantee the final answer. The only methods is to use the theorem and postulate of Boolean algebra and any other manipulation that becomes familiar eg. simplify x*x'y exon ovary simplify xy'z-x'yzny’ xyzix'yziny=xalyty}oxy’ xzixy’ AF. Kana Digital Logic Design. Page 35,Simplify xy +x’2tyz xy tx’ztyz= xy ox’2+y2(Xx)) xy tx’ztyaxtyzx’ xy(142) +x'2(14y) Karnaugh map ‘The Kamaugh map also known as Veitch diagram or simply as K map is a two dimensional form of the truth table, drawn in such a way that the simplification of Boolean expression can be immediately be seen fom the location of 1's in the map. The map is a diagram made up of squares , each sqare represent one minterm. Since any Boolean function can be expressed as a sum of minterms, it follows that a Boolean function is recognised graphically in the map from the area enclosed by those squares whose minterms are included in the function, ‘A two variable Boolean function can be represented as follow A Ag ; 8 iB , ae | ae’ ° ae | AB 3 [1 ‘A three variable function can be represented as follow A x a 10 c wec | asc’ | apc’ ° wee | ac | asc | asic c [2 AF. Kana Digital Logic Design. Page 36A four variable Boolean function can be represented in the map bellow A e 00 01 1" 10 © 0 o > jor c on To simplify a Boolcan function using karnaugh map, the first step is to plot all ones in the function truth table on the map. The next step is to combine adjacent I's into a group of one, two, four, cight, sixteen. The group of minterm should be as large as possible. A single group of four minterm yields a simpler expression than two groups of two minterms, Ina four variable karnaugh map, 1 variable product term is obtained if 8 adjacent squares are covered 2 variable product term is obtained if 4 adjacent squares are covered 3 variable product term is obtained if 2 adjacent squares are covered | variable product term is obtained if 1 square is covered. ‘A square having a 1 may belong to more than one term in the sum of product expression The final stage is reached when each of the group of minterms are ORded together to form the simplified sum of product expression The kamaugh map is not a square or rectangle as it may appear in the diagram, The top edge is adjacent to the bottom ‘edge and the left hand edge adjacent to the right hand edge. Consequent, two squares in karnaugh map are said to be adjacent if they differ by only one variable Implicant In Boolean logic, an implicant is a "covering" (sum term or product term) of one or more minterms in a sum of products (or maxterms in a product of sums) of a boolean function. Formally, a product term P in a sum of products is an implicant of the Boolean function F if P implies F, More precisely: P implies F (and thus is an implicant of F) if F also takes the value 1 whenever P equals 1 where + Fis Boolean of n variables. + Pisa product term ‘This means that P <= F with respect to the natural ordering of the Boolean space. For instance, the function fosore0) = sy +92 bw ‘AF. Kana Digital Logic Design. Page 37is implied by xy, by xyz, by ayew, by w and many others; these are the implicants of f Prime implicant ‘A prime implicant of a function is an implicant that cannot be covered by a more general (more reduced - meaning with ‘ewer literals) implicant. W.V. Quine defined a prime implicant of F to be an implicant that is minimal - that is, ifthe removal of any literal from P results in a non-implicant for F. Essential prime implicants are prime implicants that cover ‘an output of the function that no combination of other prime implicants is able to cover. A a8 —_— Non prime implicant o 8% 1 10 Prime © 00 on 1 1 ° be aa L4 prime implicant c T 10] \* prime implicant 8 A a8 00 01 a 10 © Essential prime imalicant r 00 T o1 hb > Non Essential prime implicant Th 1 4 c Essential prime implicant 1 |e tfi 10 a In simplifying a Boolean function using kamaugh map, non essential prime implicant are not needed AF. Kana Digital Logic Design. Page 38Minimization of Boolean expressions using Karnaugh maps. Given the following truth table for the majority function, a [b| C| Mioutput) ooo fo ‘oo T fo ooo opr Tt 1/010 [0 Torr Tt Tio [i Torr ‘The Boolean algebraic expression is m= a’be + ab‘e + abe! + abe, the minimization using algebraic manipulation can be done as follows. m=a'be +abe + ab‘e~ abe + abe’ + abe (a! + adbe + afb! + b)e + ab(e! +e) =be+ac-ab ‘The abe term was replicated and combined with the other terms. To use a Kamaugh map we draw the following map which has a position (square) corresponding to each of the 8 possible combinations of the 3 Boolean variables, The upper left position corresponds to the 000 row of the truth table, the lower right position corresponds to 101 So 10 « 1 ° 1 1 1 [2 ‘The 1s are in the same places as they were in the original truth table. The 1 in the frst row is at position 110 (a= 1, b= 1,e=0), ‘The minimization is done by drawing circles around sets of adjacent 1s. Adjacency is horizontal, vertical, or both. The circles must always contain 2" 1s where n is an integer. ‘AF. Kana Digital Logic Design. Page 39So on 10 ‘We have circled two Is. The fact that the circle spans the two possible values of a (Gand 1) means that the a term is eliminated from the Boolean expression corresponding to this circle, Now we have drawn circles around all the Is. Thus the expression reduces to be +ac+ab as we saw before. ‘What is happening? What does adjacency and grouping the 1s together have to do with minimization? Notice that the 1 at position 111 was used by all 3 circles. This | corresponds to the abe term that was replicated in the original algebraic minimization. Adjaceney of 2 1s means that the terms corresponding to those 1s differ in one variable only. In one case that variable is negated and in the other it is not ‘The map is easier than algebraic minimization because we just have to recognize patterns of Is in the map instead of using the algebraic manipulations. Adjacency also applies to the edges of the map. Now for 4 Boolean variables. The Kamaugh map is drawn as shown below. A a —_ wo oO nw co 1 00 1 [2 | oa > 1 fa fa ox c i fa a ‘AF. Kana Digital Logic Design. Page 40The following corresponds to the Boolean expression + ABICD’ Q= ABCD + A'BCD + ABCD + ABC’D + ABCD + ABCD’ + AB'CI RULE: Minimization is achieved by drawing the smallest possible number of circles, each containing the largest possible number of Is. Grouping the 1s together results in the following. A The expression for the groupings above is. D+ AC+AB Q ‘This expression requires 3 2-input AND gates and 1 3-input OR gate. ‘Other examples -A'B+AB A A ° 8 Ts ° =B ft 1 a [2 BIC+A'BIC+A'BC'+ABC+ABC AF. Kana Digital Logic Design. Page 41o 6a 10 ¢ ye B 3. F=AB+A'BC’D+A‘BCD+AB'C’D’ A AB o «68a 10 co ir 1 00 fr on D —-=BDFABHAC'D! h lox c 1 on B 4, ABIC+A'CD+ABD A D ——-=BID+AC’D’+A’C’D4A'B'C ‘AF. Kana Digital Logic Design. Page 425, FeABICD'VABCD'tA’BCDIABCD!A’BCD+ABCD A £8 00 o1 u 10 © 1 1 00 ir on dD =BD+D'B’ k aa c 10/7 T Obtaining a Simplified product of sum using Karnaugh map The simplification of the product of sum follows the same rule as the product of sum, However, adjacent cells to be ‘combined are the cells containing 0. In this approach, the obtained simplified function is F, sinee F i represented by the square marked with 1, The function F can be obtained in product of sum by applying de morgan’s rule on F FABCD'tABCD'*AB'CD'+A'BCD+AB'CD'tA'BCD'+AB'CD A ‘The obtained simplified F=AB+CD+BD’, Since F”=F, By applying de morgan’s rule to F’, we obtain F"-(AB-CD+BD’ (A'B(C'+D(B'+D) which is he simplified F in product of sum. AF. Kana Digital Logic Design. Page 43,Don't Care condition Sometimes we do not care whether a 1 or 0 occurs for a Alp |c |p |F 0100 [0 _|o 010 jo ft [0 010 tte o1¢ fa oto [o_o oi je ft otto To CO tooo Tor 110 lo 1/0 Tet fo Tx To tx Life fo x Ti lo 11x Lot ex Th ffi {x FA'BICD'+A'B'CD+A’BCD+A’BCD_ ‘The X in the above stand for "don’t care" because (in this case) the inputs will never occur. stain set of inputs. It may be that those inputs will never occur so it makes no difference what the output is. For example, we might have a BCD (binary coded decimal) code which consists of bits to encode the digits 0 (0000) through 9 (1001). The remaining codes (1010 through 1111) are not sed. If'we had a truth table forthe prime numbers 0 through 9 it would be we dont care whether @ 1 or 0 is the value for that combination of inputs A AB — oo 86 10 co 0 ° x 0 00 0 ft x 0 o1 =BD+B'C T h x ¥ aa c 1 0 x x 10 ‘AF. Kana Digital Logic Design. Page 44The tabulation method(Quine-McCluskey) For function of five or more variables, itis difficult to be sure that the best selection is made. In such case, the tabulation method can be used to overcome such difficulty. The tabulation method was first formulated by Quine and later improved by McCluskey. Its also known as Quine-MeCluskey method. ‘The Quine-McCluskey algorithm (or the method of prime implicants) is a method used for minimization of boolean functions. It is functionally identical to Karnaugh mapping, but the tabular form makes it more efficient for use in computer algorithms, and it also gives a deterministic way to check that the minimal form of a Boolean function has been reached. The method involves two steps: Finding all prime implicants of the function. Use those prime implicants in a prime implicant chart to find the essential prime implicants of the function, as well as ‘other prime implicants that are necessary to cover the function, Step 1: finding prime implicants ‘Minimizing an arbitrary function: ABCD f m0 0000 0 ml 0001 0 m20010 0 m3 0011 0 m40100 1 ms.0101 0 m6 0110 0 m7 0111 0 m8 1000 1 m9 1001 x ml0 1010 1 mil 1011 1 mI2 1100 1 mI3.1101 0 ml4.1110 x mIS 1111 1 ‘One can easily form the canonical sum of products expression from this table, simply by summing the minterms (leaving out don'-care terms) where the function evaluates to one: F(A.BC.D)= A’BC’D' + ABIC’D' + ABICD’ + AB'CD + ABCD’ + ABCD. Of course, that's certainly not minimal. So to optimize, all minterms that evaluate to one are first placed in a minterm table, Don't-care terms are also added into this table, so they can be combined with minterms: ‘AF. Kana Digital Logic Design. Page 45,Number of Is Minterm Binary Representation 1 m4 0100 m8 — 1000 2 m9 1001 ml0 1010 mi2 1100 3 mil 1011 mid 1110 4 mis 1111 At this point, one ean start combining minterms with other minterms. If two terms vary by only a single digit changing, that digit can be replaced with a dash indicating that the digit doesnt matter. Terms that cant be combined any more are marked with a "*". When going from Size 2 to Size 4, treat “as a third bit value. Ex: -110 and -100 or -11- can be combined, but not 110 and O11-. (Trick: Match up the first.) Number of Is Minterm 0-Cube | Size 2 Implicants | Size 4 Implicants 1 m4 0100 |m(4,12) -100* | m(8,9,10,11) 10-—* m8 1000 |m(8,9) 100- | m(8,10,12,14) 1-0* |m(8,10) 10-0 | 2 m9 1001 |m(8,12) 1-00 | m(10,11,14,15) 1-1 m10 1010 | mi2_— 1100 [m(9,11) 10-1 | |m(10,11) 101- | 3 mil 1011 |m(10,14) 1-10 | mi4 1110 |m(2,14) 11-0 | | 4 miS 111 |m(115) 1-1 | |ma4is)11- | At this point, the terms marked with * can be seen as a solution. That is the solution is F-AB'+AD'+AC+BC'D' If the karnaugh map was used, we should have obtain an expression simplier than this. To obtain a minimal form, we need to use the prime implicant chart Step 2: prime implicant chart ‘None of the terms can be combined any further than this, o at this point we construct an essential prime implicant table. Along the side goes the prime implicants that have just been generated, and along the top go the minterms specified AF. Kana Digital Logic Design. Page 46carlier. The don’t care terms are not placed on top - they are omitted from this section because they are not necessary inputs. ho flo fit ja jis (4,12) Kk K -100 BCD) (8,9,10,11) x 10-(AB)) f(8,10,12,14) x 1-0(AD)) hn(10,11,14,15) k | kk ft-ac In the prime implicant table shown above, there are § rows, one row for each of the prime implicant and 6 columns, cach representing one minterm of the function. X is placed in each row to indicate the minterms contained in the prime implicant of that row. For example, the two X in the first row indicate that minterm 4 and 12 are contained in the prime implicant represented by (-100) ie. BC'D’ ‘The completed prime implicant table is inspected for columns containing only a single x. in this example, there are two minterms whose column have a single x. 4,15. The minterm 4 is covered by prime implicant BC’D’. that is the selection of prime implicant BC'D’ guarantee that minterm 4 is included in the selection. Similarly, for minterm 15 is covered by prime implicant AC. Prime implicants that cover minterms with a single X in their column are called essential prime implicants ‘Those essential prime implicant must be selected. Now we find out each column whose minterm is covered by the selected essential prime implicant For this example, essential prime implicant BC’D' covers minterm 4 and 12, Essential prime implicant AC covers 10, 11 and 15, An inspection of the implicant table shows that, all the minterms are covered by the essential prime implicant except the minterms 8, The minterms not selected must be included by the selection of one or more prime implicants. From this example, we have only one minterm which is 8. It ean be included in the selection either by including the prime implicant AB' or AD’. Since both of them have minterm 8 in their selection, We have thus found the minimum set Of prime implicants whose sum gives the required minimized function: F-BCD'tAD+AC OR F+ BCD'+AB+AC. Both of those final equations are functionally equivalent to this original (very area-expensive) equation: F(AB.C.D) = A’BCD' + ABC + ABICI + ABICD + ABCD’ + ABCD Implimenting logical circuit using NAND and NOR gate only. In addition to AND, OR, and NOT gates, other logic gates like NAND and NOR are also used in the design of digital circuits The NAND gate represents the complement of the AND operation. Its name is an abbreviation of NOT AND. The graphic symbol for the NAND gate consists of an AND symbol with a bubble on the ‘output, denoting that a complement operation is performed on the output of the AND gate as shown earlier AF. Kana Digital Logic Design. Page 47‘The NOR gate represents the complement of the OR operation. Its name is an abbreviation of NOT OR. The graphic symbol for the NOR gate consists of an OR symbol with a bubble on the output, denoting that a complement operation is performed on the output of the OR gate as shown earlier. ‘A universal gate is @ gate which can implement any Boolean function without need to use any other gate type. The NAND and NOR gates are universal gates. In practice, this is advantageous since NAND and NOR gates are ‘economical and easier to fabricate and are the basic gates used in all IC digital logic families. Infact, an AND gate is typically implemented as a NAND gate followed by an inverter not the other way around. Likewise, an OR gate is typically implemented as a NOR gate followed by an inverter not the other way around. NAND Gate is a Universal Gate To prove that any Boolean function can be implemented using only NAND gates, we will show that the AND, OR, and NOT operations can be performed using only these gates. A universal gate is a gale which can implement any Boolean function without need to use any other gate type. Implementing an Inverter Using only NAND Gate ‘The figure shows two ways in which a NAND gate can be used as an inverter (NOT gate). 1, AILNAND input pins connect to the input signal A gives an output A’. (A.AY'=A" . A (A.A) A A 2. One NAND input pin is connected to the input signal A while all other input pins are connected to logic 1. The output will be A’ x (Aay=a" Implementing AND Using only NAND Gates ‘An AND gate can be replaced by NAND gates as shown in the figure (The AND is replaced by a NAND gate with its output complemented by a NAND gate inverter). A (apy, A AB AB B B Implementing OR Using only NAND Gates ‘An OR gate can be replaced by NAND gates as shown in the figure (The OR gate is replaced by a NAND gate with all its inputs complemented by NAND gate inverters). ‘AF. Kana Digital Logic Design. Page 48(AB Y=A+B ‘Thus, the NAND gate is a universal gate since it can implement the AND, OR end NOT functions, NOR Gate is a Universal Gate: To prove that any Boolean function can be implemented using only NOR gates, we will show that the AND, OR, and NOT operations can be performed using only these gates. Implementing an Inverter Using only NOR Gate ‘The figure shows two ways in which a NOR gate can be used as an inverter (NOT gate). |All NOR input pins connect to the input signal A gives an output A’. A (A+ay’ 2, One NOR input pin is connected to the input signal A while all other input pins are connected to logic 0. The output will be A’ * (Atoy=ar Implementing OR Using only NOR Gates ‘An OR gate can be replaced by NOR gates as shown in the figure (The OR is replaced by a NOR gate with its output complemented by a NOR gate inverter) A (ase) AtB A >” —_— B B Implementing AND Using only NOR Gates ‘An AND gate can be replaced by NOR gates as shown in the figure (The AND gate is replaced by a NOR gate with all its inputs complemented by NOR gate inverters) ‘AF. Kana Digital Logic Design. Page 49Thus, the NOR gate is @ universal gate since it can implement the AND, OR and NOT functions. Equivalent Gates: ‘The shown figure summarizes important cases of gate equivalence. Note that bubbles indicate a complement operation (inverter. ANAND gate is equivalent to an inverted-input OR gate, sj ate A (asy ni any —. 8 s ‘An AND gate is equivalent to an inverted-input NOR gate, A+B : »— : = —~ a 5 AOR gate is equivalent to an inverted-input AND gate. ABS (A+B) A (ary x aay —- a 8 ‘An OR gate is equivalent to an inverted-input NAND gate. i ne ° j7 >> : = —=—* Ss B ‘Two NOT gates in series are same as @ buffer because they cancel each other as A’ Av=A ‘AF. Kana Digital Logic Design. Page 50‘Two-Level Implementations: We have seen before that Boolean functions in either SOP or POS forms can be implemented using 2-Level implementations. For SOP forms AND gates will be in the first level and a single OR gate will be in the second level For POS forms OR gates will be in the first level and a single AND gate will be in the second level ‘Note that using inverters to complement input variables is not counted as a level To implement a function using NAND gates only, it must first be simplified to @ sum of product and to implement function using NOR gates only, it must first be simplified to a product of sum ‘We will show that SOP forms can be implemented using only NAND gates, while POS forms can be implemented using only NOR gates through examples. Example 1: Implement the following SOP function using NAND gate only F=XZ+VZ+X'YZ, Being an SOP expression, itis implemented in 2-Ievels as shown in the figure. Introducing two successive inverters at the inputs of the OR gate results in the shown equivalent implementation, Since ‘two successive inverters on the same line will not have an overall effect on the logic as itis shown before. -{ > a > By associating one of the inverters with the output of the first evel AND gate and the other with the input of the OR tate, itis clear that this implementation is reducible to 2-level implementation where both levels are NAND gates as shown in Figure. N < ‘AF. Kana Digital Logic Design. Page 51N=>- io 2 > : . D>=D- ‘AF. Kana Digital Logic Design. Page 54