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Set-2 - Sol

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6 views2 pages

Set-2 - Sol

Uploaded by

efenglishlive2023
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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University Kasdi Merbah Ouargla

Faculty of New Technologies of Information and Communication


Department of Electronics and Telecommunication
Option : L3 Electronics Subject : Microprocessor System

Solution of Recitation N°2 : Semiconductor Memories


Solution of Exercise 1 :
 There are 65536 possibilities for each pixel⇒ log2(65536) = log2(216) = ln
(65536)/ln(2)=16 ⇒ We need 16 bits (i.e., 2 Bytes) for coding each pixel.
Total number of pixel in the screen is 1280×1024 = 1310720 pixels.
Total number of bits in the screen is = 1280×1024×16= 20971520 bits.
 The size of memory (in megabytes) occupied by a screen page::
Total number of bytes in the screen is = 20971520 bits/(8 bit)= 2621440 bytes
⇒ 2621440 Bytes /(220)= 2.5 MBytes.
⇒ We need 2.5 MBytes to represent the content of a screen page.
Solution of Exercise 2:
For a memory with the capacity of 16 k × 32.
1- The number of bits for each word is given (32 bits).
2- The number of words it can store is = 16× 210=16 ×1024 = 16384 words de 32 bits.
3- The number of cells contained in the memory is = 16384×32 = 524 288 bits..
4- The total number of different addresses is 16× 210 = 16384 different addresses.
Solution of Exercise 3:
A memory can store 8 K words of 16 bits.
1-- A) The number of data output lines is 16 lines.
B) The number of address lines is = 13 lines = ln(8×210)/ln(2).
2-- The memory capacity in bytes is = (8×210 × 16)/8 = 16 k Bytes.

Solution of Exercise 4:
We have a memory of 2K×8 bits.
1- The number of words that can be stored in this memory is = 2×210 =2048 words.
2- The total number of bits in this memory is = 2×210× 8= 16384 bits.
3- The number of address lines required is = 11 = ln(2×210)/ln(2).

Solution of Exercise 5:
We have several RAMs (M1) having a capacity of 2 Mbits with a 4-bit data bus, a CS input and
a WE input. We want to create a RAM (M2) with a capacity of 4 Mbits. The Command and Data
buses of the two RAMs are identical.

Dr A LATI Page 1/2 UKMO


University Kasdi Merbah Ouargla
Faculty of New Technologies of Information and Communication
Department of Electronics and Telecommunication
Option : L3 Electronics Subject : Microprocessor System

1- The size of the address buses of the two types of memory:


M1 => (2 Mbits/4) words of 4 bits = (2 ×220 bits/22) words of 4 bits = 219 words of 4 bits => 19 lines of addresse.
M2=> (4 Mbits/4) words of 4 bits = (22 ×220 bits/22) words of 4 bits = 220 words of 4 bits => 20 lines of addresse.
2- The address bits to determine the CS of the M1 memories:
The type of assembly we must carry out is to put two M1 boxes in series with different CS via a decoder
3- The wiring diagram:

4- The possible addresses of the boxes in hexadecimal:


Binary Addresses Hexadecimal Addresses

Boxes Beginning End Beginning End


A19 A18 ………… A0 A19 A18 ………… A0 A4 A3 A2 A1 A0 A4 A3 A2 A1 A0

B1 0 0 ……………… 0 → 0 1 ……………… 1 0 0 0 0 0 → 7 F F F F

B2 1 0 ……………… 0 → 1 1 ……………… 1 8 0 0 0 0 → F F F F F

5- Addresse (51510) => 51510 = 00203 => B1


6- Addresse (9A84416) => 9A84416 ==> B2

Dr A LATI Page 2/2 UKMO

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