Architecture

• MP is a programmable digital device.

• Designed with registers, flip-flop’s (FF)
& timing circuits.
• MP has a set of instructions, designed
internally, to manipulate data &
communicate with peripherals.
 Cont..
• This process of data manipulation &
communication is determined by logic
design of MP, called the Architecture.
• MP can be programmed to perform
fun’c on given data by selecting
necessary instructions from its set.
 CONT
• These instructions are given to MP by
writing into its memory.
• Writing (or entering) instructions &
data is done through an input device
(keyboard).
• MP reads or translates one instruction at
a time, matches it with its instruction set,
& performs data manipulation indicated
by instruction.
 Cont.
• Result stored in memory or sent to
such output devices as LED or a CRT
terminal.
• MP can respond to external signals.
• It can be interpreted, reset or asked to
Wait to synchronize with slower
peripherals.
 Cont.

• All fun’c performed by the MP can

be classified in 03 general categories:
1. MP-initiated op’n
2. Internal op’n
3. Peripheral (externally initiated
op’n).
 8086 Internal Architecture
• SEE FIG. HALL (P-29) & RAFIQ’N (P-
171).
• 8086 MP is internally divided into 02
separate functional units:
1. Bus Interface Unit (BIU)
2. Execution Unit (EU).
-Dividing the work bet’n these units
speeds up processing.
Fig: 8086 internal block diagram
 1.BIU (Bus Interface Unit)
FUNCTIONS:
• BIU sends out address
• Fetches instruction from memory
• Read data from memory & ports.
• BIU interfaces 8086 to outside world.
• BIU handle all transfer of data &
addresses on buses for EU.
 2. EU (Execution Unit)
FUNCTIONS:
• EU executes instruction that have
already been fetched by the BIU.
• EU tells BIU where to fetch
instructions or data from, decodes
instruction, & executes
instructions.
• BIU & EU fun’c independently.
EU (decode & executes instructions).
1. Control circuitry, Instruction
decoder & ALU:
• Control circuitry directs internal
op’n.
• Decoder translates instructions
fetched from memory into a series
of actions which EU carries out.
 2.FLAG REGISTERS:
• A flag register is a FF which
indicates some condition produced by
the execution of an instruction or
controls certain op’n of EU.
• Flag register in the EU holds the
status flags typically after an ALU
op’n.
• 16-bit flag resister contains 09 active
flags.
 2. Flag (cont.)

• EU has a 16-bit ALU which can

arithmetic & logical op’n(addition,
subtraction, OR, XOR, increment,
Decrement, complement or shift
binary numbers).
 2.1. Flag Resister
• A flag resister is a FF which
indicates some condition produced
by the execution of an instruction
or controls certain op’n of the EU.
• The flag register in the EU holds
the status flags typically after an
ALU op’n.
 2.1 Cont.
• 16 bits flag resister contains 09 active
flags.
• 06 flags are used to indicate some
condition produced by an instruction.
• 06 conditional flags are:
1. Carry flag (CF) 2. Parity flag (PF)
3.Auxiliary carry flag (AC) 4.zero
flag(ZF) 5.Sign flag (SF) 6.Overflow flag
(OF)
For fig see rafiq (p-176(3.3) & hall-29(2.8))

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF
1. Carry flag (CF):
• CF is set, if an arithmetic op’n results in
a carry. Otherwise it is reset.
2. Parity flag (PF):
• PF is set if the result has even parity,
PF is zero for odd parity.
• If the result has an even number of 1,
flag is set, for odd no. of 1, flag is
reset.
3. Auxiliary carry flag (AF):
• AF is used by BCD arithmetic
instructions.
• In an arithmetic op’n, when a
carry is generated by digit 3 &
passed to digit 4, the AF flag is set.
4. Zero flag (ZF):
• ZF is set(1) if result is zero, ZF is
zero(0) for nonzero result.
 5. Sign flag (SF):
• SF is set if most significant bit of the
result is 1(negative).
• Cleared to zero, for non-negative
result.
6. Overflow flag (OF):
• OF set, if there is an arithmetic
overflow, that is, if the size of the result
exceeds the capacity of destination
location.
• 03 remaining flag used to control
certain op’n of processor.
• 06 conditional flag are set/reset by
EU on the basis of the results of some
arithmetic or logical op’n.
• Control flags are set/reset with
specific instruction put in your prog.
7.Trap (Trace) flag (TF):
• Setting TF to one places the 8086 in
the single-step mode.
• in this mode, 8086 generates an
internal interrupt after execution of
each instruction.
• User can write a service routine at
the interrupt address vector to display
the desired registers & memory
location.
7. TF (Cont…)
• User can thus debug a program.
8. Interrupt flag (IF):
• Used to allow or prohibit the
interruption of a program.
-if I=1, INTR pin is enable.
-if I=0, INTR “ “ disable.
9. Direction flag (DF):
•-DF select either increment or
decrement mode during string
instructions.
• If D =1, register automatically
decrement.
• If D = 0, register “ ” incremented.
 General Purpose Registers:
• See fig.(2-7), P-29, Hall.
• The EU has 08 general purpose
registers.
• AH, AL, BH, BL, CH, CL, DH, DL.
• These registers can be used
individually for temporary storage of 8-
bit data.
 Cont..
• Certain pairs of these general purpose
registers can be used together to store
16-bit data words.
• The acceptable register pairs are AH
& AL, BH & BL, CH& CL, DH & DL.
 Cont..
• AH-AL pair refereed to as AX register.
• BH-BL ………………….BX register.
• CH-CL……………………CX register.
• DH-DL…………………DX register.
• Adv. Of using internal register for the
temporary storage of data is that, since data
is already in EU, it can be accessed much
more quickly than it could be accessed in
external memory.
 AX register:
• Called 16-bit accumulator while AL
is 8-bit accumulator.
• The use of accumulator register is
assumed by some instructions.
• I/O instructions always AX/AL for
inputting or outputting 16 or 8-bit
data to or from on I/O port.
 Cont..
• Multiplication & division instructions
also use the AX/AL.
-the AL register is same as 8085 A
register.
BX Register:
• Base register, only general purpose
register whose contents can be used for
addressing 8086 memory.
•BX register similar to 8085 H, L register
-8086 BH & BL are equivalent to 8085
H & L registers.
CX Register:
• Counter register, because instructions
such as SHIFT, ROTATE, & LOOP,
use the contents of CX as a counter.
 CX cont..
• Example, LOOP START,
automatically decrement CX by 1
without affecting flags & will check if
[CX] = 0.
• If it is zero, 8086 executes next
instruction otherwise, 8086 branches
ti the label STRRT.
 * DX Register:
• Data register.
• Used to hold high 16-bit result
(data) in 16*16 multiplication or
high 16-bit dividend (data) before a
32/16 division & 16-bit remainder
after division.
 ** Two position Registers:
• SP (Stack Pointer)
• BP (Base Pointer)
• Used to access data in the stack
segment (SS).
• SP is used as an offset from the
current SS during execution of
instruction that involve stack segment
in external memory.
 SP (cont.)
• SP contents are automatically updated
(increment or decrement) due to
execution of POP or PUSH instruction.
• BP contains an offset address in the
current SS. This offset is used by
instructions utilizing based addressing
mode.
 ** Two Index Register:
• SI ( Source Index) Register
• DI (Destination Index) Register
• Used in indexed addressing.
• Instruction that process data string
use SI & DI together with DS &
ES, in order to distinguish bet’n
source & destination address.
 BIU
1) The Queue:
-The BIU instruction queue is a
first-in-first-out (FIFO) group of
registers in which up to 06 bytes of
instruction code are perfected from
memory ahead of time.
 Queue (cont..)
• This is done in order to speed up
prog. Execution by overlapping
instruction fetch with execution.
• When EU is ready for its next
instruction, it simply reads instruction
byte for the instruction from queue in
the BIU.
 Queue (cont..)
• This is much faster than sending out
an address to system memory &
waiting for memory to send back to
the next instruction byte/bytes.
• Except in the cases of JMP &
CALL instructions, where queue
must be dumped & then reloaded
starting from a new address.
 Queue(cont..)
• This prefetch-&-queue scheme
greatly speeds up processing.
• Fetching next instruction while
current instruction executes is
called Pipelining.
2. Adder:

• BIU contains a dedicated adder,

which is used to produce 20-bit
address.
3. Control System:
• The control system generates all the
bus control signals such as-READ &
WRITE signals for memory & I/O.
 4. Segment Register:
• 8086 BIU sends out 20-bit address.
• It can address any of 2(20) =
1,048,576 bytes (1MB) in memory.
• However, at any time, 8086 works
with only four(04) 65,536 byte
(64KB) segment within this 1MB
range.
 Segment Register (cont.)
• 8086 directly address 04 segments
(64*4 = 256KB) at a particular time.
• 04 segment register in BIU are
used to hold the upper 16 bit of the
starting address with a particular
time.
 Segment Register (cont.)
• 04, 16-bit segment registers:
• Code Segment (CS)
• Data Segment (DS)
• Stack Segment (SS)
Extra Segment (ES)
* See fig. (2.9) P-30, Hall.
 Cont..
• Fig. Shows how these 04
segments might be positioned in
memory at a given time.
• 04 segment can be separated as
shown or for small programs which
do not need all 64KB in each
segment, they can overlap.
 Cont..
• SS: A segment register is used to
hold to upper 16-bits of the starting
address for each of the segments.
• CS: Code segment registers, holds
upper 16-bits of the starting address
for the segment from which BIU is
currently fetching instruction code
byte.
 CS (cont.)
• BIU always inserts zeros for the
lowest 04-bits of the 20-bits storing
address for a segment.
• If CS register contains 348AH, then
CS will start at address 348A0H.
• In otherwords, a 64KB segment can
be located anywhere within 1MB
address space, but segment will always
start at an address with zeros in lowest
4 bits.
 CS (cont...)
• This constraint was put on the
location of segment so that it is
only necessary to store &
manipulate 16-bit numbers when
working with the starting address
of a segment.
• The part of a segment starting
address stored in a segment register
is often called the segment base.
 * SS
• A stack is a section of memory
set aside to store address & data
while a subprogram executes.
• SS register points to the current
stack.
• Used to hold upper 16-bits of the
starting address for prog. Stack.
 SS (cont.)
• 20-bit physical stack address is
calculated from SS & SP(stack pointer)
for stack instructions such as PUSH &
POP.
* DS Register:
• Points to current data segment;
operands for most instructions are
fetched from this segment.
* ES Register:
• Points to the extra segment in which
data (in excess of 64K pointed to by DS)
is stored.
• Segments can be contiguous, partially
overlapped, fully overlapped or
disjointed.
•Example: see fig. P-173, Rafiquzzaman.
 Segment register (cont.)
• SEGMENT 0 &1- Contiguous(adjacent)
• SEGMENT 1 & 2-partially overlapped
•SEGMENT 2 & 3-fully overlapped
SEGMENT 2 & 4-disjoint
• Every segment must start on 16-byte
memory boundaries. 00000H, 00010H,
00020H, 00030H, …………, FFFFFH.
5. Instruction Pointer (IP):
• CS register holds upper 16 bits of
starting address of the segment
from which BIU is currently
fetching instruction code bytes.
• IP Register holds 16 bits
address/offset of the next code byte
within this code segment.
 IP (cont.)
• The value contained in IP is
refereed to as an offset because this
value must be offset from (added
to) segment base register in CS to
produce required 20-bit physical
address sent out by BIU.
* See fig.(2-10(a)), P-31, Hall.
 IP (cont.)
• The CS register contains points to
the base/start of current code
segment.
• IP contains the distance/offset
from this base address to the next
instruction byte to be fetched.
*See fig 2-10 (b).
 IP (cont..)
• Fig 2-10 (b) shows, how 16-bit
offset in IP added to 16-bit segment
base address in CS to produce 20-bit
physical address.
• Two 16-bit no. are not added
directly in line, because CS register
contains only upper 16 bits of the
base address for code segment.
 IP (Cont.)
• BIU automatically inserts zeros for
lowest 04 bits of segment base
address.
• If CS register, contains 348AH,
starting address for code segment
348A0H.
• When BIU adds offset of 4214H in
IP to this segment base address, result
is a 20-bit physical address of
 IP(cont.)
• Alternative way of representing a
20-bit physical address is:
Segment base : Offset form
CS : IP
348A : 4214
Stack Segment Register & Stack Pointer
Register:
• Upper 16-bits of starting address
kept in stack segment register.
• SP register in EU holds 16-bit offset
from start of the segment to memory
location where a word was most
recently stored on the stack.
 SS & SP register (cont.)
• The memory location where a word
most recently stored is called top of
stack.
* See fig (2-11(a), P-31, Hall.
• The physical address for a stack
read/stack write is produced by adding
content of SP register to the segment
base addressed represented by the upper
16 bits of base address in SS.
 SS & SP register (cont)
• See fig (2-11(b)), P-31, Hall.
• 5000H in SS represents a segment base
address, 50000H.
• When FFE0H in SP is added to this,
resultant physical address can be
represented either as a single no.
5FFE0H or SS:SP form as 5000:FFE0H.
Real Mode Memory Addressing
• Real mode op’n allows MP to
address only the 1st 1MB of memory
space.
• 1st 1MB of memory is called either
real memory or conventional memory
system.
• DOS operating system requires MP
to operate in real mode.
 Segments & Offsets
• A combination of segment
address & an offset address access
a memory location in real mode.
• All real mode memory address
must consists of a segment address
plus an offset address.
 Segments & offsets (cont.)
• Segments address located within
one of segment register, defines the
beginning address of any 64KB
memory segment.
• Offset address selects any location
within 64KB memory segment.
• Segment in real mode always have a
length of 64KB.
 Segment & Offset (cont.)
• See fig.(2.3), P-57, Brey.
• A memory segment begins at
location 10000H & ends at location
1FFFFH-64KB in length.
• An offset address, sometimes called
a displacement, of F000H selects
location 1F000H in memory system.
 Segment & offset (cont.)
• Offset or displacement is the
distance above the start of the
segment.
• Segment register contains a 1000H,
its address a starting segment at
location 10000H.
• In real mode, each segment register
is internal appended with 0H on its
rightmost end.
 Segment & offset (cont.)
• This form a 20 bit memory
address, allowing it to access the
start of a segment.
• MP must generate a 20-bit
memory address to access a
location within first 1M of
memory.
 Segment & offset (Cont.)
•For example:
• When a segment register contains a
1200H, it address a 64KB memory
segment beginning at location 12000H.
Likewise, if a segment register
contains a 1201H, it address a memory
segment beginning at location 12010H.
 Segment & offset (cont.)
• Because of internally appended 0H, real
mode segments can begin only at a 16-
byte boundary in memory system. This
16-byte boundary often called a
Paragraph.
• Because a real mode segment of memory
is 64K in length, once the beginning
address is known, ending address is found
by adding FFFFH.
 segment & Offset (cont)
• Example:
• If a segment register contains
3000H, the 1st address of the
segment is 30000H.
• Last address of segment, 30000H
+ FFFFH = 3FFFFH.
• See Table (2-1), P-58, Brey.
 Example of segment addresses
` Segment Register Starting Address Ending Address

2000H 20000H 2FFFFH

2001H 20010H 3000FH

2100H 21000H 30FFFH

AB00H AB000H BAFFFH

1234H 12340H 2233FH
Segment & offset (cont.)
• The offset address, which is a part
of address, is added to the start of the
segment to address a memory
location within the memory segment.
• Example:
• If segment address is 1000H &
offset address 2000H, MP Address
memory location 12000H.
Segment & Offset (Cont.)
“The offset address is always
added to the starting address of
the segment to locate the data”.
• the segment & offset address is
sometimes written as 1000:2000 for
a segment address of 1000H with
an offset of 2000H.
 Default Segment & Offset Registers
• MP has a set of rules that apply to
segments whenever memory is
addressed.
• These rules, which apply in real mode,
define the segment register & offset
register combination.
• CS register is always used with IP to
address next instruction in a program.
Default segment & offset (cont.)
• This combination is CS:IP.
• CS register defines the start of the
code segment & IP locates the next
instruction within the code segment.
• This combination (CS:IP) locates
next instruction executed by MP.
Default segment & offset (cont.)
• Example:
if CS = 1400H & IP = 1200H
-MP fetches its next instruction from
memory location 14000H + 1200H =
15200H.
• Another default combination is
Stack.
 Default segment & offset (cont.)
• Stack data is referred through stack
segment at memory location addressed
by either SP or BP.
• These combination referred to as SS:SP
or SS:BP.
• Example:
if SS = 2000H & BP = 3000H, MP address
memory location, 20000H + 3000H =
23000H for SS memory location.
Solve the following Questions:
Q1. What are program visible registers?
- Programming model of 8086 through
P4 is considered to be program visible
because it registers are used during
application programming & specified by
instructions.
 Questions (cont)
Q2. What are the purpose of IP registers?
Q3. What is the purpose of segment
register in real mode op’n of the MP?
Q4. In real mode, show starting & ending
addresses of each segment located by
following segment register values:
(a) 1000H (b) 1234H © 2300H
(d) E000H (e) AB00H
 Questions (cont.)
Q5. Find memory address of the next
instruction executed by the MP, when
operated in the real mode, for the
following CS:IP combinations.
(a) CS= 1000H & IP= 2000H
(b) CS=2000H & IP=1000H
(C) CS=2300H & IP= 1A00H
(d) CS=1A00H & IP= B000H
(e) CS= 3456H & IP= ABCDH