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verilog codes

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0% found this document useful (0 votes)
5 views

verilog codes

Uploaded by

Wizard
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Verilog codes Data flow model

1.write a verilog program for full adder

using halfadder and also testbench.

Halfadder:

module half_adder(input a,b,output sum,carry );

assign sum=a^b;

assign carry=a&b; //dataflow

Endmodule

Full adder

module full_adder(a1,b1,c1,sum1,carry1);

input a1,b1,c1;

output sum1,carry1;

wire [2:0]w;

half_adder ha1(.a(a1),.b(b1),.sum(w[0]),.carry(w[1]));

half_adder ha2(.a(w[0]),.b(c1),.sum(sum1),.carry(w[2]));

or r1(carry1,w[2],w[1]);
endmodule
CIRCUIT

SIMULATION RESULT:
2. Write a verilog programe for 2:4
decoder and also testbench.

RTL CODE:

module decoder2_4(d0,d1,y0,y1,y2,y3);

input d0,d1;

output y0,y1,y2,y3;

assign y0=~d0&~d1;

assign y1=~d0&d1;

assign y2=d0&~d1;

assign y3=d0&d1;

endmodule
TEST BENCH:

module decode2_4_tb();

reg s0,s1;

wire a0,a1,a2,a3;

decoder2_4 dut(.d0(s0),.d1(s1),.y0(a0),.y1(a1),.y2(a2),.y3(a3));

integer i;

initial

begin

{s0,s1}=0;

end

initial begin

for(i=0;i<4;i=i+1)

begin

{s0,s1}=i;

#10;

end

#20 $finish;

end

initial

$monitor("s0=%b,s1=%b,a0=%b,a1=%b,a2=%b,a3=%b",s0,s1,a0,a1,
a2,a3);
endmodule
CIRCUIT :

SIMULATION RESULT:
3. write an RTL and testbench for a 4:1 MUX using 2:1

MUX.

RTL:

module mux4_1(input i0,i1,s,output y );

assign y=~s&i0|s&i1;

Endmodule

TESTBENCH:

module mux24_1(input s0,s1,i0,i1,i2,i3,output y1 );

wire [1:0]w;

mux4_1 m1(.s(s0),.i0(i0),.i1(i1),.y(w[0]));

mux4_1 m2(.s(s0),.i0(i2),.i1(i3),.y(w[1]));

mux4_1 m3(.s(s1),.i0(w[0]),.i1(w[1]),.y(y1));

endmodule
SIMULATION:
4. Write aRTL and testbenchfor a
bidirectional buffer and verify the same
using testbench.
RTL:

module bidirbuff(inout a,b,input ctrl );

bufif1 s1(a,b,ctrl);

bufif0 s0(b,a,ctrl);

endmodule

TESTBENCH:

module bidirbuff_tb();

wire a1,b1;

reg ctrl1;

reg temp1,temp2;

integer i;

bidirbuff dut(.a(a1),.b(b1),.ctrl(ctrl1));

initial

begin

for (i=0;i<8;i=i+1)

begin

{temp1,temp2,ctrl1}=i;
#10;

end

#1000 $finish;

end

assign b1=ctrl1?temp1:1'bz;

assign a1=~ctrl1?temp2:1'bz;

initial

$monitor("a=%b,b=%b,ctrl=%b",a1,b1,ctrl1);

Endmodule

RTL:
SIMULATION:
5. Write a RTL and testbench for a4-bit ripple carry adder

using 1-bit full adder.


RTL:

TOP LEVEL:
module adder4bit (

input a, b, cin,

output sum, cout);

assign sum = a ^ b ^ cin;

assign cout = (a & b) | (b & cin) | (a & cin);

endmodule

RIPPLE CARRY ADDER:

module rca

( input [3:0] a, b,

input cin,

output [3:0] sum,

output cout );

wire [3:0] carry;

adder4bit fa0 (.a(a[0]), .b(b[0]), .cin(cin), .sum(sum[0]),


.cout(carry[0]));
adder4bit fa1 (.a(a[1]), .b(b[1]), .cin(carry[0]), .sum(sum[1]),
.cout(carry[1]));

adder4bit fa2 (.a(a[2]), .b(b[2]), .cin(carry[1]), .sum(sum[2]),


.cout(carry[2]));

adder4bit fa3 (.a(a[3]), .b(b[3]), .cin(carry[2]), .sum(sum[3]),


.cout(cout));

endmodule
TESTBENCH:

module rca_tb();

reg [3:0] a, b;

reg cin;

wire [3:0] sum;

wire cout;

integer i;

rca dut (

.a(a),

.b(b),

.cin(cin),

.sum(sum),

.cout(cout)

);

initial begin

{a, b, cin} = 0;

for (i = 0; i < 512; i = i + 1) begin

{a, b, cin} = i;

#10;

end

#20 $finish;
end

initial begin

$monitor(" a=%b, b=%b, cin=%b | sum=%b, cout=%b", a, b, cin,


sum, cout);

end

endmodule
RTL:
SIMULATION:

6. Write a RTL code for 8:3 priority encoder using

structural model and verify the same using testbench.

Binary encoder:

module binenc8_3(input [7:0]i,output [2:0]y);

assign y[0]=i[1]|i[3]|i[5]|i[7];

assign y[1]=i[2]|i[3]|i[4]|i[7];

assign y[2]=i[4]|i[5]|i[6]|i[7];

endmodule
Priority encoder:

module prioenc(input [7:0]d ,output [7:0]p,idle);

assign
p[0]=d[0]&(~d[1])&(~d[2])&(~d[3])&(~d[4])&(~d[5])&(~d[6]
)&(~d[7]);

assign
p[1]=d[1]&(~d[2])&(~d[3])&(~d[4])&(~d[5])&(~d[6])&(~d[7]
);

assign p[2]=d[2]&(~d[3])&(~d[4])&(~d[5])&(~d[6])&(~d[7]);

assign p[3]=d[3]&(~d[4])&(~d[5])&(~d[6])&(~d[7]);

assign p[4]=d[4]&(~d[5])&(~d[6])&(~d[7]);

assign p[5]=d[5]&(~d[6])&(~d[7]);

assign p[6]=d[6]&(~d[7]);

assign p[7]=d[7];

assign
idle=~d[0]&(~d[1])&(~d[2])&(~d[3])&(~d[4])&(~d[5])&(~d[
6])&(~d[7]);

endmodule
8:3 priority encoder using structural model:

module binprioenc(input [7:0]c,output idle1,[2:0]y1 );

wire [7:0]w;

prioenc p1(.d(c),.p(w),.idle(idle1));

binenc8_3 p2(.i(w),.y(y1));

endmodule
TESTBENCH:

module binprioenc_tb();

wire empty;

wire [2:0]z;

reg [7:0]j;

integer i;

binprioenc dut(.idle1(empty),.c(j),.y1(z));

initial

begin

j=0;

end

initial

begin

for(i=0;i<256;i=i+1)

begin

j=i;

#10;

end

#20;

$finish;

end

initial
$monitor("j=%b;empty=%b,z=%b",j,empty,z);

Endmodule

CIRCUIT:

SIMULATION:
7. Write an RTL for 4:1 mux using
decoder and tristate buffer and verify the
same testbench.

Tri state buffer:

module mux4_1tribuf(input a,ctrl ,output b );

bufif1(b,a,ctrl);

endmodule

odule mux4_1tribuf(input a,ctrl ,output b );

bufif1(b,a,ctrl);

endmodule
2:4Decoder:

module dec2_4(input i0,i1,output [3:0]y );

assign y[0]=~i0&~i1;

assign y[1]=~i0&i1;

assign y[2]=i0&~i1;

assign y[3]=i0&i1;

endmodule

4:1 MUX using tristate buffer and decoder:

module mux4_1tribuf1(input i0,i1,i2,i3,s0,s1,output e);

wire [3:0]w;

dec2_4 g1(.i1(s1),.i0(s0),.y(w));

mux4_1tribuf r0(i0,w[0],e);

mux4_1tribuf r1(i1,w[1],e);

mux4_1tribuf r2(i2,w[2],e);

mux4_1tribuf r3(i3,w[3],e);

endmodule
Testbench:

module mux4_1tribuf1_tb();

reg i0,i1,i2,i3,s1,s0;

wire e;

integer i;

mux4_1tribuf1 dut(i0,i1,i2,i3,s0,s1,e);

initial

begin

{i0,i1,i2,i3,s0,s1}=0;

end

initial

begin

for(i=0;i<64;i=i+1)

begin

{i0,i1,i2,i3,s0,s1}=i;

#10;
end

#20 $finish;

end

initial begin

$monitor("Time=%0t | i0=%b, i1=%b, i2=%b, i3=%b, s0=%b, s1=%b,


e=%b", $time, i0, i1, i2, i3, s0, s1, e);

end

endmodule

CIRCUIT:
SIMULATION:

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