VASIREDDY VENKATADRI INSTITUTE OF TECHNOLOGY

(Autonomous)
Approved by AICTE, Permanently Affiliated to JNTUK, NAAC Accredited with
‘A’ Grade, ISO 9001:2015 Certified
Nambur (V), Pedakakani (M), Guntur (Dt.), Andhra Pradesh – 522 508
[Branch Program: Computer Science and Engineering (Internet of Things) –
CSO]

SUBJECT TITLE: COMPUTER ORGANIZATION

COURSE CODE YEAR AND SEMESTER L P T C
II B. TECH II SEM 3 0 0 3
FUNDAMENTALS OF COMPUTING & DIGITAL LOGIC
PRE REQUISITES
DESIGN

COURSE OBJECTIVES
1. To recognize basic structures of computers and to summarize various
machine instructions.
2. To learn and use the addressing modes and types of instructions.
3. To analyze ALU & I/O organization of a computer.
4. To summarize various memory systems.
5. To analyze functionalities done by processing unit and also learn micro
programmed control.
SYLLABUS
UNIT-I: BASIC STRUCTURE OF A COMPUTER 10
Hours
Introduction: Introduction, Functional unit, Basic Operational concepts, Bus
structures, System Software, Performance. Number Representation:
Integer - unsigned, signed (sign magnitude, 1’s complement, 2’s
complement); Characters - ASCII coding, other coding schemes; Real
numbers - fixed and floating point, IEEE754 representation. Machine
Instructions: Instruction and Instruction Sequencing: Register Transfer
Notation, Assembly Language Notation, Basic Instruction Types

UNIT-II: ADDRESSING MODES AND TYPES OF INSTRUCTIONS 10

Hours
Addressing Modes: Addressing Modes, Basic Input/output Operations, and
role of Stacks and Queues in computer programming equation.
Components of Instructions: Logical Instructions, shift and Rotate
Instructions. Type of Instructions: Arithmetic and Logic Instructions,
Branch Instructions, Input and output operations.

UNIT-III ALU AND I/O ORGANIZATION 10 Hours

Basic Building Blocks for the ALU: Adder, Subtracter, Shifter,
Multiplication and division circuits. I/O Organization: Accessing I/O Devices,
Interrupts: Interrupt Hardware, Enabling and Disabling Interrupts, Handling
Multiple Devices, Direct Memory Access. Buses: Synchronous Bus,
Asynchronous Bus, Interface Circuits, Standard I/O Interface: Peripheral
Component Interconnect (PCI) Bus, Universal Serial Bus (USB)

UNIT-IV: THE MEMORY SYSTEMS 7

Hours
Memory: Basic memory circuits, Memory System Consideration, Read- Only
Memory: ROM, PROM, EPROM, EEPROM, Flash Memory, Cache Memories:
Mapping Functions, Interleaving. Secondary Storage: Magnetic Hard Disks,
Optical Disks.

UNIT-V: PROCESSING UNIT 11

Hours
Fundamental Concepts: Register Transfers, Performing an Arithmetic or
Logic Operation, Fetching a Word from Memory, Execution of Complete
Instruction, Hardwired Control. Micro Programmed Control:
Microinstructions, Micro program Sequencing, Wide Branch Addressing
Microinstructions with next –Address Field. Pipeline: Parallel Processing,
Pipelining, Instruction Pipeline, RISC Pipeline, Array Processor.

TEXT BOOKS
1. Computer Organization, Carl Hamacher, Zvonks Vranesic, Safea Zaky, 5th
Edition, McGraw Hill.
2. Computer Architecture and Organization by William Stallings, PHI Pvt. Ltd.,
Eastern Economy Edition, Sixth Edition, 2003
REFERENCE BOOKS
1. Computer Architecture and Organization, John P. Hayes, 3rd Edition,
McGraw Hill.
2. Computer System Architecture by M Morris Mano, Prentice Hall of India,
2001

COURSE OUTCOMES
CO1 The student will be able to recognize basic structures of computers
and to summarize various machine instructions.
CO2 The student will be able to learn and use the addressing modes and
types of instructions.
CO3 The student will be able to analyze I/O organization of a computer.
CO4 The student will be able to summarize various memory systems.
CO5 The students will be able to analyze functionalities done by
processing unit and also learn micro programmed control.

Assessment Pattern
End Examination : 60 Marks
Internal Assessment : 40 Marks
---------
: 100 Marks
---------
 Internal Assessment:
Descriptive Test (Written Test-15M + Seminar-5M) : 20 Marks
Objective Test : 10 Marks
Assignment Test (Open Book System) : 10 Marks
-----------
: 40 Marks
-----------
Note:
1. a) The written test is for 90 minutes for 30 marks containing3 questions
without choice and will be scaled down to 15 marks. Fist mid-term Unit-
 1(12M), Unit-2(12M), & Half of Unit-3(6M). Second mid-term the
remaining half of Unit-3(6M), Unit-4 (12M) & Unit-5 (12M).
b) The Seminar on the subject topics covered should be conducted for
10 Minutes for 5 Marks, which will assess the comprehension &
expressivity skills of students in the concepts of their Course.
2. The Objective test is for 20 minutes with 20 multiple choice questions
for 20 marks and will be scaled down to 10 marks.
3. The Assignment Test (Open Book System) is for 50 minutes for 20
marks contain 3 questions and will be scaled down to 10 marks. Fist
mid-term Unit-1(8M), Unit-2(8M), & Half of Unit-3(4M). Second mid-term
the remaining half of Unit-3(4M), Unit-4 (8M) & Unit-5 (8M). Students
can bring a maximum of three printed text books related to that
subject.
4. The total marks secured in each mid-term examination are evaluated
for 40 marks.
5. Internal marks can be calculated with 70% weighted for better of the
two mids and 30% weightage for other mid exam.
Ex: Final Internal Marks = Best Mid Marks X 0.7 + Other Mid Marks X 0.3
 End Examination
1. The semester end examinations will be conducted for 60 marks
consist of five questions carrying 12 marks each. Each of these
questions is from one unit and may contain a maximum of 3 sub-
questions.
For each question there will be an “either” “or” choice, which means that
there will be two questions from each unit and student can answer either
of the two questions.
S. Bloom’s Mid- Mid- Semester End
No. Taxonomy 1 2 Exam
1 Remember 25 25 20
2 Understand 25 20 25
3 Apply 20 20 20
4 Analyze 15 15 15
5 Evaluate 10 10 10
 6 Create 05 10 10

Relationship of the course outcomes to program outcomes

CO-PO & PSO MATRIX
CO/PO PO1 PO2 PO3 PO11 PO12 PSO1 PSO2
CO1 2 - - - - - 2
CO2 2 - 2 - - - 2
CO3 - 2 2 - - 2 -
CO4 - 2 2 - - 2 -
CO5 2 2 2 2 2 - 2

1 – Slight 2 – Moderate 3 – Substantial “-“ – No

(Low) (Medium) (High) relation

JUSTIFICATIONS
PO/ Correlati
CO Justification
PSO on Level
Use basic mathematics and engineering
PO1 2 knowledge in understanding the mathematical
CO
computations in arithmetic operations.
1
Able to analyze the computations and
PSO2 2 instructions to create new instruction set for a
modern computer.
Use engineering knowledge in understanding
PO1 2 the concepts of addressing modes and able to
chose the relevant mode of instructions.
CO
Can design new modes of addressing in
2 PO3 2
instructions.
Able to introduce the best addressing modes in
PSO2 2
the design of modern computer.
Analyze various kinds of Interrupts possible in
PO2 2
working of a digital computer.
Able to design better interrupt handling
CO PO3 2 routines in I/O management with the best
3 utilization of central processing unit.
The knowledge on interrupt service routines
PSO1 2 can help in developing robust computer
designs.
CO PO2 2 Analyze various memory management
 PO/ Correlati
CO Justification
PSO on Level
techniques.
Able to solve problems interleaved memory
PO3 2
4 models in modern computer.
Can develop efficient memory management
PSO1 2
models in modern computers.
Analyze various kinds of programmed control
PO1 2
instructions.
Can develop programs to interact with
PO2 2
hardware.
Can extend the solutions to solve complex
PO3 2
problems.
CO
Can develop solutions that can be embedded in
5 PO11 2
hardware units.
The model developed can be used as a frame
PO12 2
work to develop new applications.
Use knowledge of different hardware
PSO1 2 architectures instruction sets in developing a
modern digital computer.

JUSTIFICATION
This course will explore the concepts of Computer Organization that helps in
understanding various architectures of modern computer with its processing
units. Memory management, I/O management and performance
measurement of modern computer can be understood.
 MICRO SYLLABUS
UNIT-I: BASIC STRUCTURE OF A COMPUTER 10
Hours
Introduction: Introduction, Functional unit, Basic Operational concepts, Bus
structures, System Software, Performance. Number Representation:
Integer - unsigned, signed (sign magnitude, 1’s complement, 2’s
complement); Characters - ASCII coding, other coding schemes; Real
numbers - fixed and floating point, IEEE754 representation. Machine
Instructions: Instruction and Instruction Sequencing: Register Transfer
Notation, Assembly Language Notation, Basic Instruction Types
UNIT-I MODULE MICRO CONTENT NO. OF
HRS
Functional unit, Basic
Introduction to Operational concepts
Computer Bus structures, System 2
Structure Software
Performance
unsigned, signed (sign
Complement of
Introductio magnitude, 1’s
number system
n complement, 2’s
and subtraction 3
complement);
using complement
Characters - ASCII coding,
method
other coding schemes
IEEE 754 Standard 32-bit
Floating-Point
single precision, 64-bit 2
Representation
double precision
Machine Instruction and Register Transfer
Instruction Instruction Notation, Assembly
s Sequencing Language Notation 3
Basic Instruction Basic Instruction Types
Types

UNIT-II: ADDRESSING MODES AND TYPES OF INSTRUCTIONS 10

Hours
Addressing Modes: Addressing Modes, Basic Input/output Operations, and
role of Stacks and Queues in computer programming equation.
Components of Instructions: Logical Instructions, shift and Rotate
Instructions. Type of Instructions: Arithmetic and Logic Instructions,
Branch Instructions
NO. OF
UNIT-II MODULE MICRO CONTENT
HRS
Addressing Modes Types of addressing modes 3

Addressing Basic Input/output

Modes & Operations
Basics of I/O
Operations role of Stacks and Queues 2
operations
in computer programming
equation
Logical
Components Instructions, shift Logical Instructions, shift
of 2
Instructions and Rotate and Rotate Instructions
Instructions
Arithmetic and Logic
Type of Basic Instruction Instructions, 3
Instructions Types
Branch Instructions

UNIT-III ALU AND I/O ORGANIZATION 10 Hours

Basic Building Blocks for the ALU: Adder, Subtracter, Shifter,
Multiplication and division circuits. I/O Organization: Accessing I/O Devices,
Interrupts: Interrupt Hardware, Enabling and Disabling Interrupts, Handling
Multiple Devices, Direct Memory Access. Buses: Synchronous Bus,
Asynchronous Bus, Interface Circuits, Standard I/O Interface: Peripheral
Component Interconnect (PCI) Bus, Universal Serial Bus (USB).
NO. OF
UNIT-III MODULE MICRO CONTENT
HRS
Building
Adder, Subtracter, Shifter, 4
Blocks For ALU
Multiplication and division circuits.
The ALU
Accessing I/O Devices, Interrupts:
I/O I/O
Interrupt Hardware, Enabling and
Organizati Organizat 3
Disabling Interrupts, Handling Multiple
on ion
Devices, Direct Memory Access
Synchronous Bus, Asynchronous Bus,
Buses Buses 3
Interface Circuits, Peripheral
 Component Interconnect (PCI) Bus,
Universal Serial Bus (USB)
Branch Instructions

UNIT-IV: THE MEMORY SYSTEMS 7

Hours
Memory: Basic memory circuits, Memory System Consideration, Read- Only
Memory: ROM, PROM, EPROM, EEPROM, Flash Memory, Cache Memories:
Mapping Functions, Interleaving Secondary Storage: Magnetic Hard Disks,
Optical Disks.
UNIT-IV MODULE MICRO CONTENT NO. OF HRS
Basic
Memory System
Memory Memory 2
Consideration
Circuits
Read- Only Read- Only ROM, PROM, EPROM,
2
Memory Memory EEPROM, Flash Memory
Cache Cache Mapping Functions,
2
Memories Memories INTERLEAVING
Secondary Secondary Magnetic Hard Disks,
1
Storage Storage Optical Disks

UNIT-V: PROCESSING UNIT 11

Hours
Fundamental Concepts: Register Transfers, Performing an Arithmetic or
Logic Operation, Fetching a Word from Memory, Execution of Complete
Instruction, Hardwired Control. Micro Programmed Control:
Microinstructions, Micro program Sequencing, Wide Branch Addressing
Microinstructions with next –Address Field. Pipeline: Parallel Processing,
Pipelining, types of pipelining, hazards of pipelining.
UNIT-V MODULE MICRO CONTENT NO. OF HRS
Performing an Arithmetic
Register or Logic Operation,
2
Transfers Fetching a Word from
Fundamenta
Memory
l Concepts
Execution of
Execution of Complete
Complete 2
Instruction
Instruction,
 Microinstructio
Microinstructions 2
Micro ns
Programme Wide Branch Addressing
Micro program
d Control Microinstructions with next 2
Sequencing
–Address Field.
Parallel processing,
Pipelining Pipelining pipelining, types and 3
hazards