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Ddco 4
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Ddco 4
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a . 4 ' yor GES SeHENE usN [ | | LLU] | BCS302 Third Semester B.E./B.Tech. Degree Examination, Dec.2023/Jan.2024 Digital Design and Computer Organization Time: 3 hrs. Max. Marks: 100 Note: I. Answer any FIVE full questions, choosing ONE full question from each module. 2M: Marks , L: Bloom's level , C: Course outcomes. Module—1 Mit] Cc | QA [a. | Obtain a minimum product of sums with a Kamnaugh map. 10) 13 | Cor Fw, x y.2)=x'z' + wyet wy zt y. b. | Find the minimum sum of products for each function using a Karnaugh | 10| £3 | COL map i) Fi(a.b,c)=Mo Mz +Ms + Ms i) Fa(d, ¢, ) = Zam(0, 1, 2, 4) | ii) Fu Qawtes tes | OR Q2 |a.| Identify the prime implicants and essential prime implicants of the | 10) L3 | COT following functions: | i) MA,B,C, D)=E(1, 3, 4,5, 10, 11, 12, 13, 14, 15) ii) RW, X, ¥,Z)= LO, 1, 2,5, 7, 8, 10, 15). | b.| Write the verilog code for the given expression using dataflow and|S [12 | COt | behavioral model where Y =(AB’ + A’B) (CB+ AD) (AB'C + AC), ©. | Write the verilog code and time diagram for the given circuit with|S | 12 | COI propagation delay where the AND, OR gate has a delay of 30ns and 10ns. > Lp —» I o | Fig.Q.2(0) ‘Module ~2 Q3 a. | What is Latch? With neat diagram, explain S-R latch using NOR gate. | 10 | L3 | CO2 Derive characteristics equation. Tb. | What is priority encoder? Design 4:2 priority encoder with necessary | 10] L3 | CO2 diagrams. OR Qa Ta. | Design and explain four bit adder with carry look ahead. 10] 13 | Coz b. | What is multiplexer? Design 9:1 mux using 2:1 mux. 10/13 | Coz Lof2BCS302 Moduie ~3 QS | a. | Explain four types of operation performed by computer with an example. | 10] L2 | CO3 b. | Show how below expression will be executed in one address, two address [ 10 | L1 | CO3 zero address and three address processor in an accumulator organization X=(A*B)+(C*D). OR Q.6 | a. | What is addressing mode? Explain different types of addressing mode with | 10] L2 | CO3 an examples. in With a neat diagram, explain basic operational concepts of a computer. 10) 12 | Cos Module —4 Q7 a. | Explain the following with respect to interrupts with diagram. 10] 12 | COs i) Vector interrupt )) Interrupt nesting iii) Simultaneous request. b. | Explain Direct Memory Access with a neat diagram. 10/12 | Cos ‘OR Q8 | a. | What is Bus arbitration? Explain different types of bus arbitration. 10] (2 | Cos b. | Discuss different types of mapping functions of coaches. 10 | 12 | COS ‘Module —5 Q9 a. | Draw and explain the single-bus organization of the data path inside a[ 10] L2 | COs processor. b. | List out the actions needed to execute the instruction ADD (R3), RI write and explain the sequence of control steps for the execution of the same. | ea At ____OR- Q.10 | a. | Analyze how does execution of complete instruction carry out. 10] 14] Cos \b. | What is pipeline? Explain the performance of pipeline with an exampie. | 10 L4 | COS 2of2
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