Module 4
Module 4
Why HDL?
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DEPARTMENT OF ECE DIGITAL SYSTEM DESIGN USING VERILOG (BEC302)
➢ Verilog is case sensitive. Halfadder and halfadder are two different modules in verilog.
The declaration starts with predefined word module.
➢ The name of the module should start with alphabetical letter and can include special
character underscore (_). It is user selected.
➢ Semicolon (;) is a line separator. The order in which the inputs, &outputs and their
declarations are written is irrelevant.
➢ “=” is assignment operator, and symbols ^ and & are used for: “xor” and “and”
respectively.
➢ The doubles slashes (//) signal a comment command or /*… ........*/ the pair is used to
write a comment of any length.
➢ The program ends with predefined word endmodule
Verilog ports
input: the port is only an input port. In any assignment statement, the port should appear
only on the right hand side of the assignment statement.(i.e., port is read.)
output: the port is an output port. In contrast to VHDL, the Verilog output port can appear on
either side of the assignment statement.
inout: this port can be used as both an input and output. The inout port represents a
bidirectional bus.
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DEPARTMENT OF ECE DIGITAL SYSTEM DESIGN USING VERILOG (BEC302)
1.4 Operators
HDL has a extensive list of operators. Operator performs a wide variety of functions.
Functions classified
1. Logical operators such as and, or, nand, nor, xor, xnor and not
2. Relational operators: to express the relation between objects. The operators include =,
/=, <, <=, >and >=.
3. Arithmetic operators: such as +, -, * and division.
4. Shifts operators: To move the bits of an objects in a certain direction such as right or left
sll, srl, sla, sra, rol and ror .
Logical operators
These operator performs Logical operations, such as and, or, nand, nor, xor, xnor, and not.
The operation can be on two operands or on a single operand. The operand can be single bit
or multiple bits.
Verilog Equivalent Operand Result
operator logic type type
(bitwise)
& Bit Bit
| Bit Bit
^ Bit Bit
~^ Bit Bit
~ Bit Bit
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DEPARTMENT OF ECE DIGITAL SYSTEM DESIGN USING VERILOG (BEC302)
Verilog logical operator can be classified as Bitwise, Boolean logical and reduction logical
operators.
The bitwise operators are similar to VHDL logical operators. They operate on the
corresponding bits of two operands. These are shown in table1.1
Example Z= x & y, if x=1011 and y=1010 are 4-bit signals then z=1010 is logical and operation
of x and y.
Boolean operators operate on the two operands. The result is Boolean true (1) or false (0).
These are shown in table 1.2
Example for z= x && y, if x=1011 and y=0001 then Z=1, 2nd case if x=1010 and y=0101 then
z=0;
For z! =x if x=1111 then z=0;
Operators Operation Number of
operands
&& AND two
|| OR two
Table 1.2 Boolean operators
Reduction operators: These operators operate on a single operand. The result is Boolean.
Example y=&x, if x=1010 then y= (1&0&1&0) =0
Operators Operation Number of
operands
& Reduction AND One
| Reduction OR One
~(&) Reduction One
NAND
~(|) Reduction NOR One
^ Reduction XOR One
~(^) Reduction One
XNOR
! Negation One
Table 1.3 Verilog Reduction logical operators
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DEPARTMENT OF ECE DIGITAL SYSTEM DESIGN USING VERILOG (BEC302)
Verilog has a set of Relational operator similar to VHDL. Returns Boolean values false (0) or
true (1).
The result can also be of type unknown (X) when any of the operand include don’t care or
unknown (X) or high impedance. Table 1.4 shows the list of Verilog Relational operators
Example: if (A==B), if the values of A or B contains one or more don’t care or Z bits. The value
of the expression is unknown.
If A is equal to B, then result of the expression (A==B) is true (1).
If A is not equal to B, then result of the expression (A==B) is false (0).
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DEPARTMENT OF ECE DIGITAL SYSTEM DESIGN USING VERILOG (BEC302)
Data types
The data or operands used in the language must have several types to match the need for
describing the hardware.
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DEPARTMENT OF ECE DIGITAL SYSTEM DESIGN USING VERILOG (BEC302)
Parameters:
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DEPARTMENT OF ECE DIGITAL SYSTEM DESIGN USING VERILOG (BEC302)
Array: there is no predefined word “array”. Registers and integers can be used as arrays.
Parameter N=4;
Parameter M=3;
Reg signed [M: 0] carry [0:N]
Reg [M: 0] b [0: N];
Integer sum [0: N];
The above statement declares an array by the name sum. It has 5 elements, and each element
is an integer type.
array carry has 5 elements, and each elements is 4bits. They are in 2’S complement form
The array b has 5 elements, each element is 4 bits. The value of each bit can be 0, 1, X or Z;
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DEPARTMENT OF ECE DIGITAL SYSTEM DESIGN USING VERILOG (BEC302)
Dataflow is a type of hardware description which shows how the signal flows from
system inputs to outputs. It uses signal assignment statements which are executed concurrently
when an event occurs on the signals on the right side of the statement.
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DEPARTMENT OF ECE DIGITAL SYSTEM DESIGN USING VERILOG (BEC302)
The above gate network has two inputs A and B, two outputs
Y1 and Y2. The outputs will get evaluated simultaneously
whenever an event occurs on either of the inputs A or B or
both, assuming the propagation delay of both the gates to be
same.
2. Sequential program execution: In this method all the statements are executed
sequentially in the order of their appearance.
Example program1:
VHDL dataflow description Verilog dataflow description
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DEPARTMENT OF ECE DIGITAL SYSTEM DESIGN USING VERILOG (BEC302)
Above example shows HDL code, describing a system using dataflow description. The
entity (module) name is system. I1 and I2 are the two inputs and O1 and O2 are the two outputs.
St1 and st2 are signal assignment statements which assigns value to the outputs O1 and O2.
SIGNAL DECLARATION:
Input and output signals are declared in the entity (module) as ports. Intermediate
Signals (other than input and output signals) are declared using the predefined word signal in
VHDL and wire in Verilog as shown in the below example. In Verilog signals are declared
using reg when the value of the signal needs to be stored.
signal s1, s2 : bit; --VHDL
wire s1, s2; // Verilog
SIGNAL ASSIGNMENT STATEMENTS:
A signal assignment statement is used to assign a value to a signal. The left hand side
of the statement should be declared as a signal. The right hand side can be a signal, a variable,
or a constant. ‘<=’ is a signal assignment operator in VHDL and in verilog predefined word
assign is used.
Execution of signal assignment statement has two phases. In the above example of
system, assume that an event at T0 occurs on either signal I1 or I2. This event changes the value
of I1 from 0 to 1 and also the value of I2 from 0 to 1.
1. Calculation: The value of O1 is calculated using the current values of I1 and I2 at time
T0. The value 1 and 1=1 is calculated. This is not yet assigned to O1.
2. Assignment: The calculated value 1 is assigned to O1 after a delay time. The delay
time can be implicitly or explicitly specified. If no delay time is specified, the HDL
uses a default, small delay of Δ (delta) seconds.
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DEPARTMENT OF ECE DIGITAL SYSTEM DESIGN USING VERILOG (BEC302)
One of the primary mechanisms for dataflow modeling in VHDL is the concurrent
signal assignment statement. It has the following form,
LHS_target <= RHS_expression;
The value computed by the RHS_expression is assigned to the LHS_target. ‘<=’ is called the
signal assignment oprator.
Example: C <= A and B;
Right hand side expression A and B is computed and the value is assigned to the LHS_target
C.
expression n;
When there is an event on any of the operands present in the boolean_condition or the
expression, the execution of when-else starts. The boolean condition1 is evaluated first. If the
result is true then expression1 is assigned to the target signal. If the result is false, next
condition2 is checked. If the result is true then expression2 is assigned to the target or else
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DEPARTMENT OF ECE DIGITAL SYSTEM DESIGN USING VERILOG (BEC302)
condition3 is cheked and so on. If no conditions are true then expression n is assigned to the
target_signal.
The target_signal will receive the value of the first expression whose boolean condition
is TRUE. If more than one condition is true, the value of the first condition that is TRUE will
be assigned.
Though the when-else statement is a concurrent statement, within the body the
execution is sequential. Hence the first condition gets the highest priority. This special feature
of when-else can be used to describe “priority encoders”.
Example: Z <= A when s0=’0’ and s1=’0’ else
B when s0=’0’ and s1=’1’ else
C when s0=’1’ and s1=’0’ else
D when s0=’1’ and s1=’1’;
In this example, the statement is executed any time an event occurs on A, B, C, D, s0 or s1.
The first condition(s0=0 and s1=0) is checked, if false, the second condition is checked and so
on and when the condition is true the corresponding value is assigned to Z.
The conditional signal assignment will be executed if any of the signals in the
conditions or expression change.
entity MUX is
port (A, B, C, D: in std_logic;
SEL: in std_logic_vector (1 down to 0);
Z : out std_logic );
end MUX;
architecture MUX41 of MUX is
begin
Z <= A when SEL = “00” else
B when SEL = “01” else
C when SEL = “10” else
D;
end MUX41;
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DEPARTMENT OF ECE DIGITAL SYSTEM DESIGN USING VERILOG (BEC302)
For example if the value of the choice_expression matches with choice1, then
expression1 is assigned to the target_signal.
* The choice expression must contain atleast one signal because an EVENT can occur only on
a signal. For example if the choice_expression is Y then Y must be a signal. If
choice_expression is X+Y, then either of X or Y must be a signal.
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