Advanced VLSI

21EC71
Course Outcomes (CO)
• Understand the VLSI design flow
• Describe the concept of ASIC design methodology
• Create floorplan including partition and routing with the use of CAD
algorithms
• Will have better insights into VLSI back-end design flow
• Learn verification basics and System Verilog
Text Books
• Michael John Sebastian Smith, Application - Specific Integrated
Circuits, Addison-Wesley Professional, 2005.
• Chris Spear, System Verilog for Verification – A guide to learning the
Test bench language features, Springer Publications, Second Edition,
2010
Activity Based Learning
• Use EDA tool to design basic Analog blocks like amplifiers and 4-bit
RAM
• Project using System Verilog
Module 1
• Introduction to ASICs: Full custom, Semi-custom and Programmable
ASICs, ASIC Design flow, ASIC cell libraries. CMOS Logic: Data path
Logic Cells: Data Path Elements, Adders: Carry skip, Carry bypass,
Carry save, Carry select, Conditional sum, Multiplier (Booth encoding),
Data path Operators, I/O cells, Cell Compilers. (Text Book 1)
Introduction to ASICs
• An ASIC (application-specific integrated circuit) is a chip customized for a
specific application.
• The primary objective of ASICs is to achieve a specific functionality with the
highest possible efficiency.

• This efficiency can be in terms of power consumption, performance, cost, or a

combination of these factors.

• By designing an ASIC to perform a specific function, it is possible to optimize its

design to achieve the best possible performance for that function.

• This targeted approach often results in significant efficiency gains compared to

using a general-purpose IC for the same function.
Evolution of ASIC
• In the early days, integrated circuits were not application-specific. They were
general-purpose chips that could be used in a variety of applications.
• However, as the demand for more precise and efficient electronic devices grew,
the need for specialized integrated circuits became apparent. This led to the
development of ASICs, designed to perform a specific function in an electronic
device
• The evolution of ASICs has been marked by continuous improvement and
innovation. Each new generation of ASICs has brought significant improvements
in terms of performance, power efficiency, and cost-effectiveness. This has made
ASICs an integral part of modern electronic devices and systems
Why ASIC ?
• With the advent of VLSI in the 1980s engineers began to realize the
advantages of designing an IC that was customized or tailored to a
particular system or application rather than using standard ICs alone.
• Microelectronic system design then becomes a matter of defining the
functions that you can implement using standard ICs and then implementing
the remaining logic functions (sometimes called glue logic ) with one or
more custom ICs .
• As VLSI became possible you could build a system from a smaller number
of components by combining many standard ICs into a few custom ICs.
• Building a microelectronic system with fewer ICs allows you to reduce cost
and improve reliability.
• Examples of ICs that are not ASICs include standard parts such as:
memory chips sold as a commodity item—ROMs, DRAM, and
SRAM; microprocessors; TTL or TTL-equivalent ICs at SSI, MSI, and
LSI levels.
• Examples of ICs that are ASICs include: a chip for a toy bear that
talks; a chip for a satellite; a chip designed to handle the interface
between memory and a microprocessor for a workstation CPU; and a
chip containing a microprocessor as a cell together with other logic.
Application of ASIC
• Telecommunication
• Cryptocurrency Mining
• Consumer Electronics
Transistor technology
• MOS (Metal-Oxide-Semiconductor):
• MOS technology generally refers to any type of transistor that uses an oxide layer between the
gate and the substrate to control the flow of current. It is the foundational technology behind
most semiconductor devices.
• Types:
• MOS transistors can be classified into different types, including NMOS and PMOS transistors.
• Applications:
• MOS technology is used in various applications, including digital circuits, analog circuits, and
memory devices.
• Advantages:
• Low power consumption.
• High packing density.
• Disadvantages:
• Slower switching speed compared to bipolar junction transistors (BJTs).
• Limited current-driving capability.
• NMOS (N-Channel MOSFET):
• NMOS is a type of MOSFET where the majority carriers are electrons. NMOS
transistors are faster than PMOS because electrons have higher mobility than holes.
• Applications:
• NMOS technology is commonly used in digital circuits, particularly in older logic
families like NMOS logic.
• Advantages:
• Faster operation due to higher electron mobility.
• Simpler design and lower cost compared to PMOS.
• Disadvantages:
• Higher power consumption in static conditions (due to leakage current).
• Cannot efficiently implement logic gates like CMOS does (requires both NMOS and
PMOS for complementary logic).
• CMOS (Complementary Metal-Oxide-Semiconductor):
• CMOS technology uses both NMOS and PMOS transistors to implement logic gates. It is the
most widely used technology in modern digital integrated circuits, including
microprocessors, microcontrollers, and memory devices.
• Applications:
• CMOS is used in nearly all modern digital logic circuits, microprocessors, microcontrollers,
and application-specific integrated circuits (ASICs).
• Advantages:
• Extremely low static power consumption (only consumes power during switching).
• High noise immunity.
• Scalable to very large integration (VLSI) and ultra-large scale integration (ULSI).
• Disadvantages:
• Slightly more complex design and fabrication process compared to NMOS-only technology.
• Slower switching speed compared to BiCMOS for certain applications.
• BiCMOS (Bipolar Complementary Metal-Oxide-Semiconductor):
• BiCMOS technology combines the advantages of both CMOS and bipolar junction transistor
(BJT) technologies. It integrates both MOSFETs and BJTs in the same circuit, leveraging the
high-speed capability of BJTs with the low-power and high-density advantages of CMOS.
• Applications:
• Used in high-performance analog and mixed-signal circuits, RF circuits, and high-speed
digital circuits. Common in applications like RF amplifiers, analog-to-digital converters, and
some types of microprocessors.
• Advantages:
• High-speed operation due to BJTs.
• Better analog performance, with high current-driving capability.
• Combines low power consumption and high noise immunity from CMOS.
• Disadvantages:
• More complex and expensive fabrication process compared to pure CMOS or NMOS.
• Higher power consumption than CMOS in digital circuits due to the presence of BJTs.
Summary
Conclusion
• MOS is the general category under which NMOS, PMOS, and CMOS
technologies fall.
• NMOS is faster than PMOS but consumes more power, and it has
largely been supplanted by CMOS in most digital applications.
• CMOS is the dominant technology in modern electronics due to its
low power consumption and scalability.
• BiCMOS combines the best of CMOS and BJT, making it suitable for
high-speed and analog applications but at a higher cost and
complexity
ASIC Types

• Full Custom
• Semi Custom
• Programmable
Full Custom ASICs
• A full-custom IC includes some (possibly all) logic cells that are customized
and all mask layers that are customized.
• A microprocessor is an example of a full-custom IC
• Customizing all of the IC features in this way allows designers to include
analog circuits, optimized memory cells, or mechanical structures on an IC
• Full-custom ICs are the most expensive to manufacture and to design.
• The manufacturing lead time (the time it takes just to make an IC—not
including design time) is typically eight weeks for a full-custom IC.
• These specialized full-custom ICs are often intended for a specific
application
• It makes sense to take this approach only if there are no suitable
existing cell libraries available that can be used for the entire design.
• This might be because existing cell libraries are not fast enough, or
the logic cells are not small enough or consume too much power.
• There is one growing member of this family, though, the mixed
analog/digital ASIC
• Bipolar technology has historically been used for precision analog
functions.
• Suppose we have transistors T1, T2, and T3 on an analog/digital ASIC.
The three transistors are all the same size and are constructed in an
identical fashion.
• Transistors T1 and T2 are located adjacent to each other and have the
same orientation.
• Transistor T3 is the same size as T1 and T2 but is located on the other
side of the chip from T1 and T2 and has a different orientation.
• ICs are made in batches called wafer lots. A wafer lot is a group of
silicon wafers that are all processed together.
• Usually there are between 5 and 30 wafers in a lot.
• Each wafer can contain tens or hundreds of chips depending on the
size of the IC and the wafer
• If we were to make measurements of the characteristics of transistors
T1, T2, and T3 we would find the following:
• Transistors T1 will have virtually identical characteristics to T2 on the
same IC. We say that the transistors match well or the tracking
between devices is excellent.
• Transistor T3 will match transistors T1 and T2 on the same IC very
well, but not as closely as T1 matches T2 on the same IC.
• Transistor T1, T2, and T3 will match fairly well with transistors T1, T2,
and T3 on a different IC on the same wafer. The matching will depend
on how far apart the two ICs are on the wafer.
• Transistors on ICs from different wafers in the same wafer lot will not
match very well.
• Transistors on ICs from different wafer lots will match very poorly.
Semi Custom ASIC
• Semi-Custom ASICs offer a balance between customization and cost-
effectiveness.
• Unlike Full Custom ASICs, where every aspect of the chip is custom-designed,
Semi-Custom ASICs involve some pre-designed components.
• These pre-designed components, known as cells or blocks, are selected from a
library and arranged to create the desired functionality.
• Standard Cell-Based ASICs (Cell based IC or CBIC)
• Uses predefined logic cells (AND gates, OR gates, mux and flipflops)
known as standard cells
• The standard cell area (flexible block) in a CBIC are built with rows of
standard cells
• The standard cell area may be used in combination with larger
predesigned cells (like microcontrollers)known as mega cells
• The ASIC designer defines only the placement of the standard cells
and the interconnect in a CBIC
• Standard cells can be placed anywhere on the si
• This means that all the mask layers of a CBIC are customised and are
unique to a particular customer
• Advantages
• Designers save time, money and reduce risk by using a predesigned,
pretested and pre characterised standard cell library.
• In addition each standard cell can be optimised individually. During
the cell design of the cell library each and every transistor in every
standard cell can be choosen to maximize speed or minimize the area
• Disadvantages are the time and expense of designing or buying the
standard cell library and the time needed to fabricate all layers of the
ASIC for each new design
• Features:
• All mask layers are customised
• Custom blocks can be embedded
• Manufacturing lead time is about 8 weeks
Gate array based (Masked Gate Array-MGA)
• It consist of a pre-fabricated chip with a large array of unconnected transistors.
• The final interconnections are added in the last few layers of the fabrication
process, creating the desired functionality.
• This approach reduces fabrication time and cost, as the same base chip can be
used for different designs.
• However, it offers less flexibility and performance compared to Standard Cell-
based ASICs.
• Following are the types of gate array based ASICs
• Channeled gate arrays
• Channelless gate arrays
• Structured gate arrays
• Channeled gate
• Important features of this type MGA are
• Only the interconnect is customized
• Interconnect uses predefined spaces between rows of base cells
• Manufacuring lead time is between 2 days to 2 weeks
• Channelless Gate Array:
• Also known as channel-free gate array, sea-of gate array or SOG array
• Important features are:
• Only some (the top few) mask layers are customized
• Manufacturing lead time is between 2 Days to 2 Weeks
• The key difference between channelless and channeled gate array is that there
are no predefined areas set aside for routing between cells on a channelless gate
array
• Instead we route over the top of the gate array devices
• We can do this because we customize the contact layer that defines the
connections between metal1, first layer of the metal and the transistor.
• Structured gate array (Embedded gate array/ masterslice or master
image)
• It combines the features of CBICs and MGAs
• One of the disadvantage of the MGA is the fixed gate array base cell
• This makes the implementation of memory difficult and inefficient
• In embedded gate array we set aside some of the IC area and
dedicate it to some of the function
• This embedded area can either contain a different base cell that is
more suitable for building memory cells or it can contain a complete
circuit block like microcontroller
• Important features of this type of MGA are
• Only the interconnects is customised
• Custom blocks can be embedded
• Manufacturing lead time is between 2 days to 2 weeks
• Programmable Logic Devices (PLDs)
• PLDs are standard ICs that are available in standard configurations
and are sold in very high volume to many different customers
• PLDs may be configured or programmed to create a part customized
to a specific applications and so they belong to ASIC family
• Important features are
• No customized mask layers or logic cells
• Fast design turnaround
• A single large block of programmable interconnect
• A matrix of logic macrocells that usually consist of programmable array logic
followed by a flip flop or latch
• The simplest form of programmable IC are ROM
• The most common types of ROM use a metal fuse that can be blown
permanently
• An EPROM uses programmable MOS transistors whose characteristics
are altered by applying a high voltage
• Field Programmable Gate Array (FPGA)
• FPGA is larger and more complex than PLD
• Important Characteristics are
• None of the mask layers are customised
• The core is a regular array of programmable basic logic cells that can
implement combinational as well as sequential logic
• A matrix of programmable interconnects surronds the basic logic cells
• Programmable I/o cells surround the core
• Design turnaround is a few hours
Design Flow
• 1. Design entry. Enter the design into an ASIC design system, either using a
hardware description language ( HDL ) orschematic entry .
• 2. Logic synthesis. Use an HDL (VHDL or Verilog) and a logic synthesis tool
to produce a netlist —a description of the logic cells and their connections.
• 3. System partitioning. Divide a large system into ASIC-sized pieces.
• 4. Pre layout simulation. Check to see if the design functions correctly.
• 5. Floor planning. Arrange the blocks of the netlist on the chip.
• 6. Placement. Decide the locations of cells in a block.
• 7. Routing. Make the connections between cells and blocks.
• 8. Extraction. Determine the resistance and capacitance of the
interconnect.
• 9. Post layout simulation. Check to see the design still works with the
added loads of the interconnect.
ASIC Cell Libraries
• Key part of ASIC design
• For a programmable ASIC , the FPGA companies supplies a library of
logic cells in the form of design kit, normally it costs upto few
thousand dollars.
• For MGA and CBICs there are 3 choices:
• the ASIC vendor will supply a cell library or you can buy a cell library from a
third party library vendor, or you can build your own library
• To create a cell library each cell must contain the following:
• A physical layout
• A behavioural model
• A Verilog/vhdl model
• A detailed timing model
• A test stratergy
• A circuit schematic
• A wire load model
• A routing model
Datapath Logic Cells
• Suppose we wish to build an n -bit adder (that adds two n -bit
numbers) and to exploit the regularity of this function in the layout.
We can do so using a datapath structure.
• The following two functions, SUM and COUT, implement the sum and
carry out for a full adder ( FA ) with two data inputs (A, B) and a carry
in, CIN:
• SUM = A ⊕ B ⊕ CIN = SUM(A, B, CIN) = PARITY(A, B, CIN)
• COUT = A · B + A · CIN + B · CIN = MAJ(A, B, CIN).
• The sum uses the parity function ('1' if there are an odd numbers of
'1's in the inputs). The carry out, COUT, uses the 2-of-3 majority
function ('1' if the majority of the inputs are '1'). We can combine
these two functions in a single FA logic cell, ADD(A[ i ], B[ i ], CIN, S[ i],
COUT), shown in Figure
• S[ i ] = SUM (A[ i ], B[ i ], CIN)
• COUT = MAJ (A[ i ], B[ i ], CIN)

• Now we can build a 4-bit ripple-carry adder ( RCA ) by connecting four of these
ADD cells together as shown in Figure (b).
• The i th ADD cell is arranged with the following: two bus inputs A[ i ], B[ i ]; one
bus output S[ i ]; an input, CIN, that is the carry in from stage (i – 1) below and is
also passed up to the cell above as an output; and an output, COUT, that is the
carry out to stage ( i + 1) above.
• In the 4-bit adder shown in Figure(b) we connect the carry input, CIN[0], to VSS
and use COUT[3] and COUT[2] to indicate arithmetic overflow.
• Notice that we build the ADD cell so that COUT[2] is available at the top of the
datapath when we need it
• Figure(c) shows a layout of the ADD cell. The A inputs, B inputs, and S
outputs all use m1 interconnect running in the horizontal direction—
we call these data signals. Other signals can enter or exit from the top
or bottom and run vertically across the datapath in m2—we call these
control signals
• We can also use m1 for control and m2 for data, but we normally do
not mix these approaches in the same structure. Control signals are
typically clocks and other signals common to elements.
• To build a 4-bit adder we stack four ADD cells creating the array
structure shown in Figure d
RCA
Datapath Elements
• Figure shows some of the data path elements for adder
Adders: CSA
CLA
Conditional Sum Adder
Multiplier
Datapath Operators
I/O cells
• Figure shows tri state bidirectional output buffer
• When the output enable signal is high the circuit functions as non
inverting buffer driving the value of DATAIN onto the I/O pad
• This allows multiple drivers to be connected to the bus
• It is upto the designer to make sure that a bus never has two drivers-a
problem known as contension
Cell Compilers
• The process of handcrafting circuits and layouts for a full customed IC
is a tedious time consuming and error prone task.
• There are 2 types of automated layer assembly tools known as silicon
compilers.
• The first kind produces a specific kind of circuit : a RAM compiler or
multiplier compiler
• Second type of compiler is usually more flexible, providing
programming language that assembles layout from an input
command file
• In addition to producing layout we also need a model compiler so
that we verify the circuit at behavioural level.
• We need a netlist from the netlist compiler so that we can simulate
the circuit and verify that it works correctly at structural level