Advanced VLSI

21EC71
Course Outcomes (CO)
• Understand the VLSI design flow
• Describe the concept of ASIC design methodology
• Create floorplan including partition and routing with the use of CAD
algorithms
• Will have better insights into VLSI back-end design flow
• Learn verification basics and System Verilog
Text Books
• Michael John Sebastian Smith, Application - Specific Integrated
Circuits, Addison-Wesley Professional, 2005.
• Chris Spear, System Verilog for Verification – A guide to learning the
Test bench language features, Springer Publications, Second Edition,
2010
Module 4
• Procedural Statements and Routines: Procedural
statements, Tasks, Functions and void functions, Task and
function overview, Routine arguments, returning from a
routine, Local data storage, time values.
• Connecting the test bench and design: Separating the test
bench and design, The interface construct, Stimulus timing,
Interface driving and sampling, System Verilog assertions.
(Text Book 2)
Introduction
• SystemVerilog introduces many incremental improvements to
make this easier by making the language look more like C,
especially around argument passing.
Procedural Statements
• SystemVerilog adopts many operators and statements from C and C++. You can
declare a loop variable inside a for loop that then restricts the scope of the loop
variable and can prevent some coding bugs.
• The increment ++ and decrement -- operators are available in both pre- and post-
form. If you have a label on a begin or fork statement, you can put the same label
on the matching end or join statement.
• This makes it easier to match the start and finish of a block. You can also put a
label on other SystemVerilog end statements such as endmodule, endtask,
endfunction, and others
• Example 1 New procedural statements and operators
initial
begin : example
integer array[10], sum, j; // Declare i in for statement
for (int i=0; i<10; i++) // Increment i
array[i] = i; // Add up values in the array
sum = array[9];
j=8;
do // do...while loop
sum += array[j]; // Accumulate
while (j--); // Test if j=0
$display("Sum=%4d", sum); // %4d - specify width
end : example // End label
Example 2 Using break and continue while reading a file
initial begin
logic [127:0] cmd;
integer file, c;
file = $fopen("commands.txt", "r");
while (!$feof(file)) begin
c = $fscanf(file, "%s", cmd);
case (cmd)
"": continue; // Blank line - skip to loop end
"done": break; // Done - leave loop
// Process other commands here
...
endcase // case(cmd)
end
$fclose(file);
end
Tasks, Functions, and Void Functions
• Verilog makes a very clear differentiation between tasks and functions.
The most important difference is that a task can consume time while a
function cannot. A function cannot have a delay, #100, a blocking
statement
such as @(posedge clock) or wait(ready), or call a task.
• Additionally, a Verilog function must return a value, and the value
must be used, as in an assignment statement.
• In SystemVerilog, if you want to call a function and ignore its return
value, cast the result to void. This might be done if you are calling the
function to use a side effect.
Example 3 Ignoring a function’s return value
void’(my_func(42));

Task and Function Overview

• Routine begin...end removed
The first improvement you may notice in SystemVerilog is that begin...end blocks
are optional, while Verilog-1995 required them on all but single line routines. The
task / endtask and function / endfunction keywords are enough to define the
routine boundaries.
Example 4 Simple task without begin...end

task multiple_lines;
$display("First line");
$display("Second line");
endtask : multiple_lines
• Routine Arguments
Many of the SystemVerilog improvements for routine make it easier
to declare arguments and expand the ways you can pass values to
and from a routine.

C-style Routine Arguments

Argument Direction
Advanced Argument Types
Default Argument Values
Common Coding Errors
Returning from a Routine
• SystemVerilog adds the return statement to make it easier for you to control the
flow in your routines. The following task needs to return early because of error
checking. Otherwise, it would have to use an else clause, that would cause more
indentation and be harder to read.
Example 5 Return in a task
task load_array(int len, ref int array[]);
if (len <= 0) begin
$display("Bad len");
return;
End // Code for the rest of the task
...
endtask
A return statement can simplify your functions.
Local Storage
• When Verilog was created in the 1980s, its primary goal was describing
hardware. Because of this, all objects in the language were statically allocated. In
particular, routine arguments and local variables were stored in a fixed location,
rather than pushing them on a stack like other programming languages.
• After all, how can you build a silicon representation of a recursive routine?
However, software engineers who were used to the behavior of stack-based
languages such as C were bitten by these subtle bugs, and were limited in their
ability to create complex testbenches with libraries of routines.
Time Values
SystemVerilog has several new constructs to allow you to unambiguously specify time
values in your system.
• Time units and precision
When you rely on the ‘timescale compiler directive, you must compile the files in the
proper order to be sure all the delays use the proper scale and precision. The timeunit
and timeprecision declarations eliminate this ambiguity by precisely specifying the
values for every module. Example 6 shows these declarations. Note that if you use
these instead of ‘timescale, you must put them in every module that has a delay.
• Time literals
SystemVerilog allows you to unambiguously specify a time value plus units. Your
code can use delays such as 0.1ns or 20ps. Just remember to use timeunit and
timeprecision or ‘timescale. You can make your code
• Example 6 Time literals and $timeformat
module timing;
timeunit 1ns;
timeprecision 1ps;
initial begin
$timeformat(-9, 3, "ns", 8);
#1 $display("@%t", $realtime); // @1.000ns
#2ns $display("@%t", $realtime); // @3.000ns
#0.1ns $display("@%t", $realtime); // @3.100ns
#41ps $display("@%t, $realtime); // @3.141ns
end
endmodule
Connecting the Testbench and Design
• Introduction
• There are several steps needed to verify a design: generate stimulus, capture
responses, determine correctness, and measure progress. But first, you need the
proper testbench, connected to the design.
• Your testbench wraps around the design, sending in stimulus and capturing he
design’s response. The testbench forms the “real world” around the design,
mimicking the entire environment.
• For example, a processor model needs to connect to various busses and devices,
which are modeled in the testbench as bus functional models. A networking device
connects to multiple input and output data streams that are modeled based on
standard protocols.
• A video chip connects to buses that send in commands, and then forms images
that are written into memory models. The key concept is that the testbench
simulates everything not in the design under test.
The testbench – design environment
• Separating the Testbench and Design
• In an ideal world, all projects have two separate groups: one to create the design
and one to verify it. In the real world, limited budgets may require you to wear
both hats.
• Each team has its own set of specialized skills, such as creating synthesizable RTL
code, or figuring out new ways to find bugs in the design.
• These two groups each read the original design specification and make their own
interpretations
Communication between the testbench and DUT
• Communication with ports
The following code fragments show the elements of connecting an RTL block to a testbench. Most of the code
and declarations have been left out for clarity. SystemVerilog has expanded the classic reg type so that you
can use it like a wire to connect blocks. In recognition of its new capabilities, the reg type has the new name of
logic. The only place where you cannot use a logic variable is a net with multiple drivers, where you must use
a net such as wire.
Example 1 Arbiter model using ports
module arb_port (output logic [1:0] grant,
input logic [1:0] request,
input logic reset,
input logic clk);
...
always @(posedge clk or posedge reset) begin
if (reset)
grant <= 2'b00;
else
...
end
endmodule
 The Interface Construct
• Designs are so complex that even the communication between them may need to be
separated out into separate entities. To model this, SystemVerilog uses the interface
construct that you can think of as an intelligent bundle of wires. They contain the
connectivity, synchronization, and optionally, the functionality of the communication
between two or more blocks. They connectdesign blocks and/or testbenches.
Using an interface to simplify connections
Connecting interfaces and ports
Grouping signals in an interface using modports
Using modports with a bus design
Creating an interface monitor
Interface trade-offs
•Stimulus Timing
• The timing between the testbench and the design must be carefully orchestrated.
At a cycle level, you need to drive and receive the synchronous signals at the
proper time in relation to the clock. Drive too late or sample too early, and your
testbench is off a cycle.
Controlling timing of synchronous signals with a clocking block
Timing problems in Verilog
Testbench – design race condition
The program block and timing regions
Specifying delays between the design and testbench