Application Note: Spartan-3 FPGA Family

Using Spartan-3 IP Cores

XAPP474 (v1.0) July 11, 2003

Summary This document provides an overview of the Xilinx CORE Generator™ System and the Xilinx
Intellectual Property (IP) offerings that facilitate the Spartan™-3 design process. For more
detailed and complete information, consult the CORE Generator Guide available at
http://www.xilinx.com/support/software_manuals.htm, and the Xilinx IP Center available at
http://www.xilinx.com/ipcenter/index.htm.

The CORE The Xilinx CORE Generator System is the cataloging, customization, and delivery vehicle for IP
Generator cores targeted to Xilinx FPGAs. The CORE Generator provides centralized access to a catalog
of ready-made IP functions ranging in complexity from simple arithmetic operators, such as
System adders, accumulators, and multipliers to system-level building blocks, such as filters,
transforms, and memories. Cores can be displayed alphabetically, by function, by vendor, or by
type. Each core comes with its own data sheet, which documents the core’s functionality in
detail.
The CORE Generator user interface makes it very easy to access the latest Spartan-3 IP
releases and to get helpful, up-to-date information. Links to partner IP providers also are built
in for the various partner-supplied AllianceCORE products. The use of CORE Generator IP
cores in Spartan-3 designs enables designers to shorten design time, and it also helps them
realize high levels of performance and area efficiency without any special knowledge of the
Spartan-3 architecture.
When installing the CORE Generator software, the designer gains immediate access to dozens
of cores supplied by the LogiCORE program. In addition, data sheets are available for all
AllianceCORE products, and additional, separately licensed, advanced function LogiCORE
products are also available. New and updated Spartan-3 IP for the CORE Generator can be
downloaded from the IP Center and added to the CORE Generator catalog.

Xilinx IP The CORE Generator works in conjunction with the Xilinx IP Center (www.xilinx.com/ipcenter).
Solutions and To make the most of this resource, Xilinx highly recommends that whenever starting a design,
one first does a quick search of the IP Center to see whether a ready-made core solution is
the IP Center already available.
A complete catalog of Xilinx cores and IP tools resides on the IP Center, including:
• LogiCORE Products
• AllianceCORE Products
• Reference Designs
• XPERTS Partner Consultants
• Design Reuse Tools

© 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other
trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature,
application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may
require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties
or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.

XAPP474 (v1.0) July 11, 2003 www.xilinx.com 1

1-800-255-7778
 R

Xilinx IP Solutions and the IP Center

LogiCORE Products
LogiCORE products are designed, sold, licensed, and supported by Xilinx. LogiCORE products
include a wide selection of generic, parameterized functions, such as muxes, adders,
multipliers, and memory cores, which are bundled with the Xilinx CORE Generator software at
no additional cost to licensed software customers. System-level cores, such as PCI, Reed-
Solomon, ADPCM, HDLC, POS-PHY, and Color Space Converters are also available as
optional, separately licensed products. The CORE Generator commonly is used to quickly
generate Spartan-3 block and distributed memories. A more detailed listing of available
Spartan-3 LogiCORE products is available in Table 1, page 3 and on the Xilinx IP Center
website (http://www.xilinx.com/ipcenter).
Types of IP currently offered by the Xilinx LogiCORE program include:
• Basic Elements: logic gates, registers, multiplexers, adders, multipliers
• Communications and Networking: ADPCM modules, HDLC controllers, ATM building
blocks, forward error correction modules, and POS-PHY Interfaces
• DSP and Video Image Processing: cores ranging from small building blocks (e.g., Time
Skew Buffers) to larger system-level functions (e.g., FIR Filters and FFTs)
• System Logic: accumulators, adders, subtracters, complementers, multipliers, integrators,
pipelined delay elements, single and dual-port distributed and block RAM, ROM, and
synchronous and asynchronous FIFOs
• Standard Bus Interfaces: PCI Interfaces

AllianceCORE Products
The AllianceCORE program is a cooperative effort between Xilinx and third-party IP developers
to provide additional system-level IP cores optimized for Xilinx FPGAs. To ensure a high level of
quality, AllianceCORE products are implemented and verified in a Xilinx device as part of the
certification process. Xilinx develops relationships with AllianceCORE partners who can
complement the Xilinx LogiCORE product offering. A large percentage of Xilinx AllianceCORE
partners focus on data and telecommunication applications, as well as processor and
processor peripheral designs.
AllianceCORE products include customizable cores that can be configured to exact needs, as
well as fixed netlist cores targeted toward specific applications. In many cases, partners can
provide cores customized to meet the specific design needs if the primary offerings do not fit
the requirements. Additionally, source code versions of the cores are often available from the
partners at additional cost for those who need maximum flexibility.

Reference Designs
Xilinx offers two types of design files: XAPP application notes developed by Xilinx and
reference designs developed through the Xilinx Reference Design Alliance Program. Both
types are extremely valuable to customers looking for guidance when designing systems.
Application notes developed by Xilinx usually include supporting design files. They are supplied
free of charge, without technical support or warranty.
Reference designs often can be used as starting points for implementing a broad spectrum of
functions in Xilinx programmable logic. Reference designs developed through the Xilinx
Reference Design Alliance Program are developed, owned, and controlled by the partners in
the program. The goal of the program is to form partnerships with other semiconductor
manufacturers and design houses so as to assist in the development of high-quality, multi-
component reference designs that incorporate Xilinx devices and demonstrate how they can
operate at the system level with other specialized and general-purpose semiconductors. The
reference designs in the Xilinx Reference Design Alliance Program are fully functional and
applicable to a wide variety of digital electronic systems, including those used for networking,
communications, video imaging, and DSP applications.

2 www.xilinx.com XAPP474 (v1.0) July 11, 2003

1-800-255-7778
 R

Spartan-3 IP Cores

XPERTS Partner Consultants

Xilinx established the XPERTS Program to provide customers with access to a worldwide
network of certified design consultants who are proficient with Xilinx FPGAs, software, and IP
core integration. All XPERTS members are certified and have extensive expertise and
experience with Xilinx technology in various vertical applications, such as communications and
networking, DSP, video and image processing, system I/O interfaces, and home networking.
XPERTS partners are an integral part of the Xilinx strategy to provide customers with cost-
efficient design solutions, while accelerating time to market.

Design Reuse Tools

To facilitate the archiving and sharing of IP created by different individuals and workgroups
within a company, Xilinx offers the IP Capture Tool. The IP Capture Tool helps to package
design modules created by individual engineers in a standardized format so that they can be
cataloged and distributed using the Xilinx CORE Generator. A core can take the form of
synthesizable VHDL or Verilog code, or a fixed function netlist. Once it is packaged by the IP
Capture Tool and installed into the CORE Generator, the captured core can be shared with
other designers within a company through an internal network.

Spartan-3 IP Table 1 provides a partial listing of cores available for Spartan-3 designs. For a complete
Cores catalog of Spartan-3 IP solutions, visit the Xilinx IP Center website at
http://www.xilinx.com/ipcenter and search for the latest Spartan-3 core solutions.

Table 1: Spartan-3 IP Cores Support

Vendor
Function IP Type Key Features Application Examples
Name

Basic Elements

Binary Counter Xilinx LogiCORE 2-256 bit output width

Binary Decoder Xilinx LogiCORE 2-256 bit output width

Bit Bus Gate Xilinx LogiCORE 1-256 bits wide

Bit Gate Xilinx LogiCORE 1-256 bits wide

Bit Multiplexer Xilinx LogiCORE 1-256 bits wide

BUFE-based Multiplexer Xilinx LogiCORE 1-256 bits wide

Slice

BUFT-based Multiplexer Xilinx LogiCORE 1-256 bits wide

Slice

Bus Gate Xilinx LogiCORE 1-256 bits wide

Bus Multiplexer Xilinx LogiCORE I/O widths up to 256 bits

Comparator Xilinx LogiCORE 1-256 bits wide

FD-based Parallel Register Xilinx LogiCORE 1-256 bits wide

FD-based Shift Register Xilinx LogiCORE 1-64 bits wide

LD-based Parallel Latch Xilinx LogiCORE 1-256 bits wide

RAM-based Shift Register Xilinx LogiCORE 1-256 bits wide, 1024 words deep

Communication & Networking

8b/10b Decoder Xilinx LogiCORE Industry standard 8b/10b Physical layer of Fibre Channel
encode/decode for serial data
transmission

XAPP474 (v1.0) July 11, 2003 www.xilinx.com 3

1-800-255-7778
 R

Spartan-3 IP Cores

Table 1: Spartan-3 IP Cores Support

Vendor
Function IP Type Key Features Application Examples
Name

8b/10b Encoder Xilinx LogiCORE Industry standard 8b/10b Physical layer of Fibre Channel
encode/decode for serial data
transmission

AES Standard Helion AllianceCORE Implements AES (Rijndael) to latest Security in wireless applications;
Encryptor/Decryptor Technology NIST FIPS PUB 197; Full dynamic 802.11 WLAN, 802.15 PAN, 802.16
Limited support for all AES key sizes (128, 192 MAN. Satellite communications,
and 256 bits); Medium speed/low gate Networked environments; Virtual
count version; Separate building blocks Private Networks (VPN), Storage Area
available for encryption and decryption Networks (SAN), Voice over IP (VoIP),
Securing program content, Securing
financial data

AES Tiny Helion AllianceCORE Implements AES (Rijndael) to latest Security in wireless applications;
Encryptor/Decryptor Technology NIST FIPS PUB 197; Full dynamic 802.11 WLAN, 802.15 PAN, 802.16
Limited support for all AES key sizes (128, 192 MAN. Satellite communications,
and 256 bits); Low speed/ultra-low gate Networked environments; Virtual
count version; The smallest full Private Networks (VPN), Storage Area
hardware AES solution available Networks (SAN), Voice over IP (VoIP),
anywhere, fully integrated encryptor Securing program content, Securing
and decryptor financial data

Convolutional Encoder Xilinx LogiCORE k from 3 to 9, puncturing from 2/3 to 3G base stations, broadcast, wireless
12/13 LAN, cable modem, xDSL, satellite,
microwave

DES3 Encryption CAST, Inc. AllianceCORE

Ethernet MAC, 10/100 Zuken, Inc. AllianceCORE IEEE802.3 1998 Edition Compliant; ISDN network controller, NIC, switch
10BASE, 100BASE MAC function; fabric interface
Half/Full-Duplex Operation; MII
interface

HDLC, Single Channel Memec Core AllianceCORE 16/32-bit frame seq, 8/16-bit address, X.25, Frame Relay, B/D-Channel
insert/delete, flag/zerop,
insert/detection

Interleaver/De-interleaver Xilinx LogiCORE Block & convolutional, width up to 256 Broadcast, wireless LAN, cable
bits, 256 branches modem, xDSL, satellite, microwave
nets, digital TV, CDMA2000

MD5 Message Digest CAST, Inc. AllianceCORE RFC 1321 compliant, suitable for data Electronic funds transfer,
Algorithm authentication applications, fully authenticated electronic data transfers,
synchronous design encrypted data storage

Reed Solomon Decoder Xilinx LogiCORE Standard or custom coding, 3-12 bit Broadcast, wireless LAN, cable
symbol width, up to 4095 symbols, modem, xDSL, satellite, microwave
error & erasure decoding nets, digital TV

Reed Solomon Encoder Xilinx LogiCORE Standard or custom coding, 3-12 bit Broadcast, wireless LAN, cable
width, up to 4095 symbols with 256 modem, xDSL, satellite, microwave
check symbols nets, digital TV

SPI-3 (POS-PHY L3) Link Xilinx LogiCORE OIF SPI-3 (POS-PHY L3) compliant. Line cards, iSCSI cards, gigabit
Layer Interface, 1-256 Fully HW interoperable with PMC- routers, and switches
Channels Sierra OC-48 framers.

SPI-4.2 Lite (POS-PHY L4) Xilinx LogiCORE Functionally compliant with SPI-4.2 SPA daughter cards sitting on top of
spec, but able to run at 1/4 data rate optical line cards
(2.5G vs. 10G). Optimized for low cost -
it requires less logic to implement so it
can run on a smaller, slower speed
grade device.

4 www.xilinx.com XAPP474 (v1.0) July 11, 2003

1-800-255-7778
 R

Spartan-3 IP Cores

Table 1: Spartan-3 IP Cores Support

Vendor
Function IP Type Key Features Application Examples
Name

Viterbi Decoder, General Xilinx LogiCORE Puncturing, serial & parallel 3G base stations, broadcast, wireless
Purpose architecture, dynamic rate change, LAN, cable modem, xDSL, satellite,
parameterized constraint length, microwave, CDMA2000
soft/hard decision with programmable
number of soft bits, dual rate decoder,
erasure pins for external puncturing,
compatible with standards such as DVB
ETS, 3GPP2, IEEE802.16, HiperLAN,
Intelsat IESS-308/309

Digital Signal Processing

CORDIC Xilinx LogiCORE Polar to rectangular, rectangular to Digital receivers

polar, sin & cos, sinh & cosh, atan &
atanh, square root

Direct Digital Synthesizer Xilinx LogiCORE 8-65K samples, 32-bit output precision,
(DDS) phase dithering/offset

Fast Fourier Transform Xilinx LogiCORE New core that supersedes the 64-256-
1024-point Complex FFT. Transform
sizes ranging from 16 to 16384 pts,
selectable data precision: 8, 12, 16, 20,
24 bits, selectable phase factor
precision: 8, 12, 16, 20, 24 bits,
supports unscaled fixed point, scaled
fixed point, block floating point, Block
RAM or Distributed RAM for data or
phase factor storage.

FIR Filter, Distributed Xilinx LogiCORE 32-bit input/coeff width, 1024 taps, 1-8
Arithmetic (DA) channels, polyphase, online coeff
reload

FIR Filter, MAC Xilinx LogiCORE Single rate, Polyphase Decimator, 3G base stations, wireless
Polyphase Interpolator communications, image filtering

LFSR, Linear Feedback Xilinx LogiCORE 168 input widths, SRL16/register

Shift Register implementation

Math Functions

Accumulator Xilinx LogiCORE 1-256 bit wide

Adder Subtracter Xilinx LogiCORE 1-256 bit wide

Multiply Accumulator (MAC) Xilinx LogiCORE Input width up to 32 bits, 65-bit

accumulator, truncation rounding

Multiply Generator Xilinx LogiCORE 64-bit input data width, constant,

reloadable or variable inputs,
parallel/sequential implementation

Sine Cosine Look-Up Table Xilinx LogiCORE 3-10 bits in, 4-32 bits out,
distributed/block ROM

Twos Complementer Xilinx LogiCORE Input width up to 256 bits

Memories & Storage Elements

Block Memory, Dual-Port Xilinx LogiCORE 1-256 bits, 2-13K words

Block Memory, Single-Port Xilinx LogiCORE 1-256 bits, 2-128K words

Content Addressable Xilinx LogiCORE 1-512 bits, 2-10K words, SRL16

Memory (CAM)

XAPP474 (v1.0) July 11, 2003 www.xilinx.com 5

1-800-255-7778
 R

Spartan-3 IP Cores

Table 1: Spartan-3 IP Cores Support

Vendor
Function IP Type Key Features Application Examples
Name

Distributed Memory Xilinx LogiCORE 1-1024 bits, 16-65536 words,

RAM/ROM/SRL16, optional output
regs and pipelining

FIFO, Asynchronous Xilinx LogiCORE 1-256 bits, 15-65535 words, DRAM or

BRAM, independent I/O clock domains

FIFO, Synchronous Xilinx LogiCORE 1-256 bits, 16-256 words,

distributed/block RAM

SDRAM Controller, Eureka AllianceCORE Networking, communication, video

Pipelined Technology system, image processing equipment,
medical, avionics and PC peripheral
equipment

Microprocessors, Controllers, & Peripherals

16450 UART with OPB Xilinx LogiCORE CoreConnect Bus (OPB), Evaluation Processor applications
interface Core (Available with EDK) or High
Value Core to be bought separately

16550 UART with OPB Xilinx LogiCORE CoreConnect Bus (OPB), Evaluation Processor applications
interface Core (Available with EDK) or High
Value Core to be bought separately

16-bit proprietary RISC Loarant AllianceCORE 44 opcodes, 64K word data, program, Control functions, State machines,
Processor Corporation Harvard architecture Coprocessor

Arbiter and Bus Structure Xilinx LogiCORE CoreConnect Bus (OPB), Infrastructure Processor applications
with OPB interface Core (includes device drivers).
Available with EDK

BRAM Controller with OPB Xilinx LogiCORE CoreConnect Bus (OPB), Memory Processor applications
interface Controller Core. Available with EDK

External Memory Controller Xilinx LogiCORE CoreConnect Bus (OPB), Memory Processor applications
(EMC) with OPB interface Controller Core. Available with EDK
(Includes support for Flash,
SRAM, ZBT, System ACE)

Generic compact UART Memec Core AllianceCORE UART and baud rate generator Serial data communication

GPIO with OPB interface Xilinx LogiCORE CoreConnect Bus (OPB). Available Processor applications
with EDK

I2C with OPB interface Xilinx LogiCORE CoreConnect Bus (OPB), Evaluation Networking, communications,
Core (Available with EDK) or High processor applications
Value Core to be bought separately

Interrupt Controller (IntC) Xilinx LogiCORE CoreConnect Bus (OPB), Peripheral Processor applications
with OPB interface Core (includes device drivers, RTOS
adaptation layers). Available with EDK

JTAG UART with OPB Xilinx LogiCORE CoreConnect Bus (OPB), Peripheral Processor applications
interface Core (includes device drivers, RTOS
adaptation layers). Available with EDK

MicroBlaze Soft RISC Xilinx LogiCORE 32-bit Soft Processor Core. Available Networking, communications
Processor with EDK

OPB2OPB Bridge (Lite) Xilinx LogiCORE CoreConnect Bus (OPB), Infrastructure Processor applications
Core (includes device drivers).
Available with EDK

OPB2PCI Full Bridge Xilinx LogiCORE CoreConnect Bus (OPB), Infrastructure Processor applications
(32/33) Core (includes device drivers).
Available with EDK

6 www.xilinx.com XAPP474 (v1.0) July 11, 2003

1-800-255-7778
 R

Spartan-3 IP Cores

Table 1: Spartan-3 IP Cores Support

Vendor
Function IP Type Key Features Application Examples
Name

PowerPC Bus Master Eureka AllianceCORE

Technology

PowerPC Bus Slave Eureka AllianceCORE

Technology

SDRAM Controller with Xilinx LogiCORE CoreConnect Bus (OPB), Memory Processor applications
OPB interface Controller Core. Available with EDK

SPI Master and Slave with Xilinx LogiCORE CoreConnect Bus (OPB), Peripheral Networking, communications,
OPB interface Core (includes device drivers, RTOS processor applications
adaptation layers). Available with EDK

Timebase/Watch Dog Timer Xilinx LogiCORE CoreConnect Bus (OPB), Peripheral Processor applications
(WDT) with OPB interface Core (includes device drivers, RTOS
adaptation layers). Available with EDK

Timer/Counter with OPB Xilinx LogiCORE CoreConnect Bus (OPB), Peripheral Processor applications
interface Core (includes device drivers, RTOS
adaptation layers). Available with EDK

UART Lite with OPB Xilinx LogiCORE CoreConnect Bus (OPB), Peripheral Processor applications
interface Core (includes device drivers, RTOS
adaptation layers). Available with EDK

Standard Bus Interfaces

CAN 2.0 B Compatible Xylon d.o.o. AllianceCORE In compliance with CAN 2.0A and CAN Standard CAN 2.0. A/B, simple
Network Controller 2.0B protocol specifications; Bit timing multiplex wiring systems, highly
requirements, hard synchronization integrated automotive or building
and resynchronization supported; management, communication protocol
Support CAN bus arbitration, automatic bridges/gateways
retransmission in error case and
arbitration lost, transmission abort

CAN Bus Controller 2.0B CAST, Inc. AllianceCORE Implementation of the Basic CAN Railway, Automotive, Industrial
specification; No generated Overload
Frames; Receiving and transmitting of
both identifiers (CAN specification
2.0B); Programmable data rate up to 1
Mbps; Programmable baud rate
prescaler (up to 1/30)

CAN with 32 mail boxes Robert Bosch AllianceCORE Supports CAN protocol version 2.0 part Automotive, Industrial Control,
GmbH A, B; Bit rates up to 1 MBit/s; Disable Telematics, Medical Engineering
Automatic Retransmission mode for
Time; Triggered CAN applications; 32
Message Objects; Each Message
Object has its own Identifier Mask;
Programmable FIFO mode; Maskable
interrupt

Controller Area Network Memec Core AllianceCORE

PCI32 Interface Design Kit Xilinx LogiCORE Includes PCI32 board, driver PC boards, CPCI, Embedded, high-
(DO-DI-PCI32-DKT) development kit, and customer performance video, Gb Ethernet
education 3-day training class for US &
Canada locations

PCI32 Interface, IP Only Xilinx LogiCORE v2.3 compliant, assured PCI timing, PC add-in boards, CPCI, Embedded
(DO-DI-PCI32-IP) 3.3V, 0 wait state, CPCI hot swap
friendly

PCI32 Single-Use License Xilinx LogiCORE v2.3 compliant, assured PCI timing, PC add-in boards, CPCI, Embedded
for Spartan (DO-DI-PCI32- 3.3V, 0 wait state, CPCI hot swap
SP) friendly

XAPP474 (v1.0) July 11, 2003 www.xilinx.com 7

1-800-255-7778
 R

Revision History

Table 1: Spartan-3 IP Cores Support

Vendor
Function IP Type Key Features Application Examples
Name

PCI64 & PCI32, IP Only Xilinx LogiCORE v2.3 compliant, assured PCI timing, PC boards, CPCI, Embedded, high
(DO-DI-PCI-AL) 3.3V, 0 wait state, CPCI hot swap performance video, Gb Ethernet
friendly, 32 bit

XAPP653: Virtex-II Xilinx Reference Design Application note describes how to

Pro/Spartan-3 3.3V PCI create compliant PCI 3.3V designs
Reference Design

Video & Image Processing

BURST_PLL Pinpoint AllianceCORE Locks to subcarrier with 1° of accuracy Video color subcarrier recovery for
Solutions, Inc. within 1 frame in video applications; color regeneration Any burst locked
Even higher accuracy can be sinusoidal wave regeneration system
guaranteed in specific configurations;
BURST_PLL is fully synchronous

JPEG Fast Codec CAST, Inc. AllianceCORE Baseline ISO/IEC 10918-1 JPEG Printers, Digital Cameras/Camcorders,
compliance; Fully programmable projection systems, Video conference
through standard JPEG stream marker & surveillance
segments; 4 stream defined Huffman
tables; 4 stream defined Quantization
tables

NTSC-COSEP Pinpoint AllianceCORE 10-bit NTSC input; 8-bit BT.656 output; LCD Panel Controllers, Set-top Box,
Solutions, Inc. Proprietary 2D adaptive comb filter; Digital TV / Converters, PC Desktop
Built-in colorbar test output mode; Video Systems, Video system design
Fixed 27MHz design; AGC feedback requiring NTSC input, video editing
interface for analog front end; External and production, Video test / verification
timing reference; Fully synchronous equipment, Video storage, Video
design teleconferencing

Revision The following table shows the revision history for this document.
History
Date Version Revision
07/11/03 1.0 Initial Xilinx release.

8 www.xilinx.com XAPP474 (v1.0) July 11, 2003

1-800-255-7778