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Filp Flop1

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19 views5 pages

Filp Flop1

Uploaded by

vishgade99999
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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DESIGN AND TEST OF AN S-R FLIP FLOP USING NAND/NOR GATES

AIM: - Design And Test Of An S-R Flip Flop Using NAND/NOR Gates
APPARATUS: - Circuit board, connecting wires, power supply etc.
CIRCUIT DIAGRAM:
PIN OUT DIGRAM
IC 7400 Quad 2 Input NAND gate IC 7410 Triple 3 Input NAND gate :

RS Flip-Flop:-

Symbol of RS Flip Flop Circuit diagram of RS Flip Flop


Truth Table of RS Flip Flop:-
Inputs Outputs Output
Remark
CLK S R QN ̅QN QN+1 ̅QN+1 Notation
0 1 0 1
0 X X QN No Change
1 0 1 0
1 0 1 0 1
0 0 QN No Change
1 0 1 0
0 1 0 1
1 0 1 0 Reset
1 0 0 1
0 1 1 0
1 1 0 1 Set
1 0 1 0
0 1 1 1
1 1 1
1 0 1 1 * Race condition

1
Theory:-
Definition: - Flip- flop is a sequential circuit which generally samples its inputs and
changes its outputs only at particular instants of time and continuously. Flip – flop is also
known as the basic digital memory circuit.
It has two stable states namely logic 1 and logic 0 state. We can design it either using
NOR gates or NAND gates. .
Applications of Flip- Flop
1. Counters.
2. Frequency Dividers.
3. Shift Registers.
4. Storage Registers.
5. Bounce elimination switch.
6. Data storage.
7. Data transfer.
8. Latch.
Triggering Methods:-
In the practically used flip flops , we use an additional input signal called clock signal.
Depending on which portion of the clock signal the flip flop responds to , we can classify
them into two types:-
1. Level triggered flip flops
2. Edge triggered flip flops
Level triggered flip flops
Definition: - the flip flop circuit which responds to change in their enable input (E) held at
active level which may be either HIGH or LOW level are called as level triggered flip-
flops. Thus these circuits do not respond at the rising or falling edges of clock. They only
respond to the steady HIGH or LOW levels of the clock signal.
Types:-
1. Positive level triggered:-
If the outputs of a flip-flop respond to the input changes, only when its clock inputs at
HIGH (1) level, then it is called as the positive level triggered flip- flop.
2. Negative level triggered:-
If the outputs of a flip-flop respond to the input changes, only when its clock inputs at
LOW (0) level, then it is called as the negative level triggered flip- flop.
Edge triggered flip flops:-
Definition: - The flip-flops which change their outputs only corresponding to either
positive (rising) or negative (falling0 edge of the clock input are called as edge triggered
flip-flop.
2
Types:-
1. Positive edges triggered flip-flop:-
Positive edge triggered flip flops will allow its outputs to change in response to its inputs
only at the instants corresponding to the rising edges of clock. Its outputs will not respond
to change in inputs at any other instant of time.
2. Negative edges triggered flip-flop:-
Negative edge triggered flip flops will respond only to the negative going edges (or
spikes) of the clock.
Types of Flip – Flop:-
RS Flip-Flop:-
This simple flip-flop is basically a one-bit memory bistable device that has two inputs, one
which will “SET” the device (meaning the output = “1”), and is labelled S and one which
will “RESET” the device (meaning the output = “0”), labelled R. Then the SR description
stands for “Set-Reset”.
It is mainly used to store data or information. Wherever operations, storage and
sequencing are required these signal circuits are used. They are also used for excising
control over the way the circuit has to function, like for changing the operation of a circuit
to a different state.
Limitation / Disadvantage of RS Flip-Flop:-
1. It has no Enable input.
2. It has a RACE condition.
3. It has no clock input.
4. It has only single output.

RESULT AND CONCLUSION:

3
VERIFICATION OF TRUTH TABLE OF J-K FLIP FLOP USING NAND/NOR GATES

AIM: - Verification Of Truth Table Of J-K Flip Flop Using Nand/Nor Gates
APPARATUS: - Circuit board, connecting wires, power supply etc.
CIRCUIT DIAGRAM:
PIN OUT DIGRAM
IC 7400 Quad 2 Input NAND gate IC 7410 Triple 3 Input NAND gate :

JK Flip Flop

Symbol of JK Flip Flop Circuit diagram of JK Flip Flop


Truth Table of JK Flip Flop:-
Inputs Outputs Output
Remark
CLK J K QN ̅QN QN+1 ̅QN+1 Notation
0 1 0 1
0 X X QN No Change
1 0 1 0
1 0 1 0 1
0 0 QN No Change
1 0 1 0
0 1 0 1
1 0 1 0 Reset
1 0 0 1
0 1 1 0
1 1 0 1 Set
1 0 1 0
0 1 1 0
1 1 1 ̅QN Toggle
1 0 0 1
4
Theory:-
JK Flip-Flop:-
The JK flip flop is basically a gated SR flip-flop with the addition of a clock input
circuitry that prevents the illegal or invalid output condition that can occur when both
inputs S and R are equal to logic level “1”.
JK Flip Flop is a flip flop which consists of a few logic gates in front of a D-flip flop. A
JK flip-flop is also called a universal flip-flop because it can be configured to work as
an SR flip-flop,.
Advantage:-
The J-K flip-flop is much faster. The J-K flip-flop does not have propagation delay
problems. The J-K flip-flop has a toggle state.
Disadvantages:-
JK flip-flop has a drawback of timing problem known as “RACE”. The condition of
RACE arises if the output Q changes its state before the timing pulse of the clock input
has time to go in OFF state. The timing pulse period (T) should be kept as short as
possible to avoid the problem of timing.

RESULT AND CONCLUSION:

Question:
1. Define race condition?
2. Define race around condition?
3. Define setup time, Hold time and propagation delay time of flip-flop?
4. Name flip flops used as basic building block for registers and counters?
5. Define asynchronous input of flip-flop and also name asynchronous input of flip-flop?
6. Explain concept of Clock?

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