21EC71

Model Question Paper-1/2 with effect from 2021(CBCS Scheme)

USN

7th Semester B.E. Degree Examination

ADVANCED VLSI
TIME: 03 Hours Max. Marks: 100

Note: 01. Answer any FIVE full questions, choosing at least ONE question from each
MODULE.
02.
*Bloom’s COs
Module -1 Taxonomy Marks
Level
Q.01 Differentiate between Full custom, Semi-custom, and
a L2 CO2 6M
Programmable ASICs. Explain their applications.
b Illustrate the design flow of ASIC with a suitable diagram. L2 CO1 7M
Explain the significance of Booth encoding in multipliers using
c L2 CO2 7M
an example.
OR
Q.02 a Discuss the importance of data path logic cells in CMOS design. L2 CO2 6M
Discuss the working principle of carry-skip, carry-select, carry-save,
b L2 CO2 7M
and Carry Bypass adders with necessary diagrams
What is the role of I/O cells in ASIC design? Explain with an
c L1 CO2 7M
example.
Module-2
Q. 03 What are the goals and objectives of floor planning? Describe the
a L1 CO3 7M
steps involved in power planning during floor planning.
b Explain the Min-cut placement algorithm with an example. L2 CO3 6M
Explain the channel definition process in floor planning and its
c L2 CO3 7M
importance.
OR
Q.04 What are the goals and objectives of global routing in physical design?
a L1 CO3 7M
Explain global routing methods with examples.
Explain the iterative placement improvement technique and its
b L2 CO3 6M
relevance in physical design.
Explain how partitioning and back annotation are used in floor
c L2 CO4 7M
planning to improve timing and reduce delays.
Module-3
Q. 05 Explain the verification process in VLSI design. Discuss the role of
a L2 CO5 6M
functional coverage in enhancing the verification process.
Discuss the role of constrained random stimulus in design
b L2 CO5 7M
verification.
Explain the use of associative arrays and queues in System
c L2 CO5 7M
Verilog with examples.
OR
Q. 06 Write and explain a SystemVerilog code snippet using associative
a L3 CO5 7M
arrays.
How are fixed arrays and dynamic arrays different in System
b L1 CO5 6M
Verilog? Provide examples.
Describe the purpose of typedef and user-defined structures in
c L2 CO5 7M
System Verilog.

Page 01 of 02
 21EC71
Module-4
Q. 07 Differentiate between tasks and functions in System Verilog.
a L2 CO5 7M
Provide suitable examples.
Describe the significance of separating the testbench and design
b L2 CO5 6M
in verification.
Write and explain a SystemVerilog code that integrates an interface
c L3 CO5 7M
with assertions to validate a basic logic circuit.
OR
Q. 08 Explain the purpose and structure of interface constructs in
a L2 CO5 7M
System Verilog.
Discuss stimulus timing and its importance in System Verilog
b L2 CO5 6M
testbenches.
Discuss the role of assertions in SystemVerilog. Provide examples of
c L2 CO5 7M
immediate and concurrent assertions.
Module-5
Q. 09 What is randomization in SystemVerilog? Explain how random
a L1 CO5 10M
number generators can be used for generating constrained inputs.
Illustrate the use of a cover group with a practical example. Explain
b L2 CO5 10M
how cross-coverage enhances the verification process.
OR
Q. 10 Explain the strategies for improving functional coverage during
a L2 CO5 6M
simulation.
Explain how automated bin creation in SystemVerilog enhances the
b L2 CO5 10M
efficiency and accuracy of functional coverage analysis.
c Explain coverage types with necessary example L2 CO5 4M

Page 02 of 02
 21EC71
Model Question Paper-1/2 with effect from 2021(CBCS Scheme)
USN

7th Semester B.E. Degree Examination

Subject Title Advanced VLSI
TIME: 03 Hours Max. Marks: 100

Note: 01. 02. Answer any FIVE full questions, choosing at least ONE question from each
MODULE.
03.
04.

*Bloom’s
Module -1 Taxonomy COs Marks
Level
Q.01 a With a neat diagram, explain ASIC design flow L2 CO1 7
b Explain Booth multiplier encoding by considering unsigned L2 CO1 5
number as one of the example
c Explain the following with relevant diagram L2 CO1 8
a. Standard Cell based ASIC
b. Gate array based ASIC
OR
Q.02 a Explain the working of a. Carry skip and b. Carry bypass adders L2 CO1 7
with necessary diagrams
b Define data path and explain any 8 data path elements with neat L2 CO1 8
diagram
c Explain I/O cells with neat diagram. L2 CO1 5
Module-2
Q. 03 a Explain about the following: Goals and objectives of 1.Floor L2 CO2 8
planning 2. Placement and 3. Routing &
CO3
b Explain the global routing methods in an ASIC physical design L2 CO2 7
&
CO3
c Explain the following in ASIC floor plan 1. Clock planning 2. L2 CO2 5
Power planning in brief &
CO3
OR
Q.04 a Explain the following placement algorithms: 1. Min-cut placement L2 CO2 8
2. Iterative placement improvement &
CO3
b Explain global routing between blocks with neat diagram L2 CO2 7
&
CO3
c Explain the concept of measurement of delay in floor planning L2 CO2 5
&
CO3
Module-3
Q. 05 a Explain the verification process of system verilog L2 CO5 7
b Explain the different types of array methods used in unpacked L2 CO5 8
arrays
c Write a short note on built in data types of system verilog with L2 CO5 5
examples

Page 01 of 02
 21EC71
OR
Q. 06 a Explain the factors in randomizing the stimulus to design L2 CO5 8
b Explain the various test bench components L2 CO5 7
c Explain the constants and strings in system verilog with examples L2 CO5 5
Module-4
Q. 07 a Explain tasks and void functions with examples L2 CO4 7
b Explain with examples the various system verilog assertions L2 CO4 8
c Explain the 1.Returning of array from a function 2. Passing an L2 CO4 5
array to a function in system verilog
OR
Q. 08 a Explain the routine arguments with necessary examples L2 CO4 8
b Explain the concept of separating the test bench and design in L2 CO4 7
system verilog with an example
c Write a short note on procedural statements in system verilog L2 CO4 5
Module-5
Q. 09 a Write about the common randomization problems in system L2 CO4 7
verilog
b List the various coverage types in system verilog and explain them L2 CO4 8
c Write a short note on measuring coverage statistics during L2 CO4 5
simulation
OR
Q. 10 a Explain about the various random number generators in system L2 CO4 8
verilog
b Which are the various functional coverage strategies? Explain them L2 CO4 7
in detail
c List the various random number functions and explain them in L2 CO4 5
brief.
*Bloom’s Taxonomy Level: Indicate as L1, L2, L3, L4, etc. It is also desirable to indicate the COs and POs to be
attained by every bit of questions.

Page 02 of 02