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Internal Registers of 8086

•The 8086 has four groups of the user accessible internal registers. They are the instruction pointer,
four data registers, four pointer and index register, four segment registers.
•The 8086 has a total of fourteen 16-bit registers including a 16 bit register called the status
register, with 9 of bits implemented for status and control flags.
•Most of the registers contain data/instruction offsets within 64 KB memory segment. There are
four different 64 KB segments for instructions, stack, data and extra data. To specify where in 1
MB of processor memory these 4 segments are located the processor uses four segment registers:
•Code segment (CS) is a 16-bit register containing address of 64 KB segment with processor
instructions. The processor uses CS segment for all accesses to instructions referenced by
instruction pointer (IP) register. CS register cannot be changed directly. The CS register is
automatically updated during far jump, far call and far return instructions.
•Stack segment (SS) is a 16-bit register containing address of 64KB segment with program stack.
By default, the processor assumes that all data referenced by the stack pointer (SP) and base
pointer (BP) registers is located in the stack segment. SS register can be changed directly using
POP instruction.
•Data segment (DS) is a 16-bit register containing address of 64KB segment with program data.
By default, the processor assumes that all data referenced by general registers (AX, BX, CX, DX)
and index register (SI, DI) is located in the data segment. DS register can be changed directly using
POP and LDS instructions.
•Accumulator register consists of two 8-bit registers AL and AH, which can be combined together
and used as a 16-bit register AX. AL in this case contains the low-order byte of the word, and AH
contains the high-order byte. Accumulator can be used for I/O operations and string manipulation.
•Base register consists of two 8-bit registers BL and BH, which can be combined together and
used as a 16-bit register BX. BL in this case contains the low-order byte of the word, and BH
contains the high-order byte. BX register usually contains a data pointer used for based, based
indexed or register indirect addressing.
•Count register consists of two 8-bit registers CL and CH, which can be combined together and
used as a 16-bit register CX. When combined, CL register contains the low-order byte of the word,
and CH contains the high-order byte. Count register can be used in Loop, shift/rotate instructions
and as a counter in string manipulation,.

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•Data register consists of two 8-bit registers DL and DH, which can be combined together and
used as a 16-bit register DX. When combined, DL register contains the low-order byte of the word,
and DH contains the high-order byte. Data register can be used as a port number in I/O operations.
In integer 32-bit multiply and divide instruction the DX register contains high-order word of the
initial or resulting number.
•The following registers are both general and index registers:
•Stack Pointer (SP) is a 16-bit register pointing to program stack.
•Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usually
used for based, based indexed or register indirect addressing.
•Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect
addressing, as well as a source data address in string manipulation instructions.
•Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register
indirect addressing, as well as a destination data address in string manipulation instructions.
Other registers:
•Instruction Pointer (IP) is a 16-bit register.
•Flags is a 16-bit register containing 9 one bit flags.
•Overflow Flag (OF) - set if the result is too large positive number, or is too small negative
number to fit into destination operand.
•Direction Flag (DF) - if set then string manipulation instructions will auto-decrement index
registers. If cleared then the index registers will be auto-incremented.
•Interrupt-enable Flag (IF) - setting this bit enables maskable interrupts.
•Single-step Flag (TF) - if set then single-step interrupt will occur after the next instruction.
•Sign Flag (SF) - set if the most significant bit of the result is set.
•Zero Flag (ZF) - set if the result is zero.
•Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits 0-3 in the AL register.
•Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of the result is even.
•Carry Flag (CF) - set if there was a carry from or borrow to the most significant bit during last
result calculation.
Addressing Modes
•Implied - the data value/data address is implicitly associated with the instruction.
•Register - references the data in a register or in a register pair.
•Immediate - the data is provided in the instruction.

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•Direct - the instruction operand specifies the memory address where data is located.
•Register indirect - instruction specifies a register containing an address, where data is located.
This addressing mode works with SI, DI, BX and BP registers.
•Based:- 8-bit or 16-bit instruction operand is added to the contents of a base register (BX or BP),
the resulting value is a pointer to location where data resides.
•Indexed:- 8-bit or 16-bit instruction operand is added to the contents of an index register (SI or
DI), the resulting value is a pointer to location where data resides
•Based Indexed:- the contents of a base register (BX or BP) is added to the contents of an index
register (SI or DI), the resulting value is a pointer to location where data resides.
•Based Indexed with displacement:- 8-bit or 16-bit instruction operand is added to the contents
of a base register (BX or BP) and index register (SI or DI), the resulting value is a pointer to
location where data resides.
Memory
•Program, data and stack memories occupy the same memory space. As the most of the processor
instructions use 16-bit pointers the processor can effectively address only 64 KB of memory.
•To access memory outside of 64 KB the CPU uses special segment registers to specify where the
code, stack and data 64 KB segments are positioned within 1 MB of memory (see the "Registers"
section below).
•16-bit pointers and data are stored as: address: low-order byte address+1: high-order byte
•Program memory - program can be located anywhere in memory. Jump and call instructions can
be used for short jumps within currently selected 64 KB code segment, as well as for far jumps
anywhere within 1 MB of memory.
•All conditional jump instructions can be used to jump within approximately +127 to -127 bytes
from current instruction.
•Data memory - the processor can access data in any one out of 4 available segments, which
limits the size of accessible memory to 256 KB (if all four segments point to different 64 KB
blocks).
•Accessing data from the Data, Code, Stack or Extra segments can be usually done by prefixing
instructions with the DS:, CS:, SS: or ES: (some registers and instructions by default may use the
ES or SS segments instead of DS segment).

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•Word data can be located at odd or even byte boundaries. The processor uses two memory
accesses to read 16-bit word located at odd byte boundaries. Reading word data from even byte
boundaries requires only one memory access.
•Stack memory can be placed anywhere in memory. The stack can be located at odd memory
addresses, but it is not recommended for performance reasons (see "Data Memory" above).
Reserved locations:
•0000h - 03FFh are reserved for interrupt vectors. Each interrupt vector is a 32-bit pointer in
format segment: offset.
•FFFF0h - FFFFFh - after RESET the processor always starts program execution at the FFFF0h
address.
Interrupts
The processor has the following interrupts:
•INTR is a maskable hardware interrupt. The interrupt can be enabled/disabled using STI/CLI
instructions or using more complicated method of updating the FLAGS register with the help of
the POPF instruction.
•When an interrupt occurs, the processor stores FLAGS register into stack, disables further
interrupts, fetches from the bus one byte representing interrupt type, and jumps to interrupt
processing routine address of which is stored in location 4 * <interrupt type>. Interrupt processing
routine should return with the IRET instruction.
•NMI is a non-maskable interrupt. Interrupt is processed in the same way as the INTR interrupt.
Interrupt type of the NMI is 2, i.e. the address of the NMI processing routine is stored in location
0008h. This interrupt has higher priority then the maskable interrupt.
•Software interrupts can be caused by:
•INT instruction - breakpoint interrupt. This is a type 3 interrupt.
•INT <interrupt number> instruction - any one interrupt from available 256 interrupts.
•INTO instruction - interrupt on overflow
•Single-step interrupt - generated if the TF flag is set. This is a type 1 interrupt. When the CPU
processes this interrupt it clears TF flag before calling the interrupt processing routine.
•Processor exceptions: Divide Error (Type 0), Unused Opcode (type 6) and Escape opcode (type
7).
•Software interrupt processing is the same as for the hardware interrupts.

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