2 555 TIMER The 555 timer IC was introduced in the year 1970 by Signetic Corporation and gave the name SE/NE 555 timer.
It is basically a monolithic timing circuit that produces
accurate and highly stable time delays or oscillations.
When compared to the applications of an op-amp in
the same areas, the 555IC is also equally reliable and is cheap in cost.
The SE 555 can be used for temperature ranges
between –55°C to 125°C. 3 4 5 555 Timer Block Diagram
6 7 8 9 Monostable Multivibrator Block Diagram
10 Monostable Multivibrator Circuit Diagram
11 12 • During Power-up pin 7,6 is grounded through the C1 & pin 2 is pulled up to VCC through R2 causing the o/p to be low. • On application of a negative trigger [low going pulse] to pin-2, comparator-2 o/p switches to high setting the F/F o/p. • The high F/F o/p turns off the discharge transistor releasing the short circuit across the C1. • C1 starts to charge towards VCC through R1. • When the capacitor voltage is more than 1/3VCC both comparator o/p’s are low & the F/F maintains the high o/p. • When the capacitor voltage increases beyond 2/3VCC Comparator-1 o/p switches to high resetting the F/F, & thereby turning on the discharge transistor causing the capacitor to discharge instantaneously. The o/p is switched low. • Monostable o/p continues to remain low until another trigger pulse is applied & then the process continues. Since the circuit has only one stable state [Output is low] it is known as Monostable Multi- vibrator. • The circuit is also called a “Pulse generator”, “Monoshot”, “Oneshot”. • Reset if applied during the timing cycle causes the o/p to immediately go Low. 13 14 We know that the voltage across the capacitor C rises exponentially. Hence
the equation for the capacitor voltage VC can be written as
18 19 • During Power-up pin 2,6 is grounded through the C1 causing the o/p to be High. • C1 starts to charge towards VCC through R1 & the forward-biased D1. • When the capacitor voltage is more than 1/3VCC both comparator o/ps are low & the F/F maintains the high o/p. • When the capacitor voltage reaches 2/3VCC Comparator-1s o/p switches to high resetting the F/F, & thereby turning on the discharge transistor. The output is switched to Low. • Once the Discharge transistor is ON, The C1 starts to discharge towards the ground through R2 and the forward-biased D2. • When the capacitor voltage falls slightly below 1/3VCC Comparator-2s o/p switches to high setting the F/F. • Output Switches high & the cycle continues. • Since the circuit has no stable state, it is known as Astable Multi-vibrator. • The circuit is also called a “Free-running Oscillator” • Reset if applied during the timing cycle causes the o/p to immediately go Low. 20 21 22 23 555 Timer Applications
▪ Voltage Controlled Frequency Shifter
▪ Frequency Divider
▪ Missing Pulse Detector
▪ PLL (Phase Locked Loop)
24 Voltage Controlled Frequency Shifter
A voltage-controlled oscillator (VCO) is an oscillator with
an output signal whose output can be varied over a range, which is controlled by the input DC voltage.
It is an oscillator whose output frequency is directly related
to the voltage at its input. The oscillation frequency varies from a few Hz to hundreds of GHz.
By varying the input DC voltage, the output frequency of
the signal produced is adjusted.
25 26 Pin 5 is the control voltage pin.
One end of the potentiometer is connected to +ve voltage & the other end is connected to gnd.
By varying the pot resistance, we can change the voltage i/p into this pin.
Voltage can reach a max. of +9V when the pot is turned to one end where it offers full resistance.
Voltage reaches a min. of 0V when the pot is turned to the other end where it offers 0Ω of resistance.
The C serves to clean up noise from the DC source so that the o/p square wave signal produced by the 555 timer isn't as noisy.
When the voltage is high, the frequency is low. As we decrease the voltage to the control voltage pin, the frequency increases.
Additionally, if we want to increase the frequency of the o/p signal, we can decrease either the resistor or capacitor in the RC n/w. 27 Frequency Divider
28 Missing Pulse Detector
29 30 PLL (Phase Locked Loop)
• PLL is an electronic circuit with a voltage or voltage-
driven oscillator that constantly adjusts to match the frequency of an i/p signal.
• PLLs are used to generate, stabilize, modulate,
demodulate, filter or recover a signal from a "noisy" communications channel where data has been interrupted.
• PLLs are widely used in wireless or radio frequency (RF)
applications, including Wi-Fi routers, broadcast radios, walkie-talkie radios, televisions & mobile phones.
31 • PLL block is a feedback control system that automatically adjusts the phase of a locally generated signal to match the phase of an i/p signal.
• PLLs operate by producing an oscillator frequency to match the
frequency of an i/p signal.
• In this locked condition, any slight change in the i/p signal first appears as a change in phase b/w the i/p signal & the oscillator frequency.
• This phase shift then acts as an error signal to change the
frequency of the local PLL oscillator to match the i/p signal.
• The locking-onto-a-phase relationship b/w the i/p signal & the
local oscillator accounts for the name phase-locked loop. 32 PLL (Phase Locked Loop)
33 34 35 36 37 DATA CONVERTERS
• Data conversion is the process of transforming data
from one format to another so that it is compatible with the target system, application, or storage method.
• Circuits that convert signals from one form to another
are known as Data Converters.
38 • Data Conversion is the process of changing or converting one form of data into another form.
• In processing and communication, there are only two types of data
forms i.e. analog and digital data.
• Real-world signals are analog signals with continuous time &
• Digital processors can only process digital signals which are discrete time and discrete amplitude.
• To interface digital processors with the analog world, data acquisition
and reconstruction circuits must be used:
• analog-to-digital converters (ADCs) to acquire and digitize the analog
signal at the front end, and digital-to-analog converters (DACs) to reproduce the analog signal at the back end.
• Digital data conversion system requires ADC and DAC.
39 40 Types of Data Converters • Analog to Digital Converter (ADC) • Digital to Analog Converter (DAC)
If we want to connect the o/p of an analog circuit as an i/p of a digital circuit,
then we have to place an interfacing circuit b/w them. This interfacing circuit that converts the analog signal into a digital signal is called an Analog to Digital Converter.
Similarly, if we want to connect the o/p of a digital circuit as an i/p of an analog
circuit, then we have to place an interfacing circuit b/w them. This interfacing circuit that converts the digital signal into an analog signal is called a Digital to Analog Converter.
41 Data Conversion Process
• The original analog signal is filtered by an LPF to remove any high-
frequency components that may cause an effect known as aliasing. • The signal is sampled and hold. • The Hold signal is quantized by the ADC to produce a N-bit digital signal. • DAC converts the N-bit digital signal back into an analog signal. • The o/p of the DAC is not as “smooth” as the original signal. • A LPF returns the analog signal back to its original form. 42 Digital to Analog Converter (DAC)
A Digital to Analog Converter (DAC) converts a digital input
signal into an analog output signal.
The digital signal is represented with a binary code, which is a
combination of bits 0 and 1.
43 • An N-bit digital word is mapped into a single analog voltage.
• Typically, the output of the DAC is a voltage that is some fraction of
a reference voltage (or current).
• where VOUT is the analog voltage output, VREF is the reference voltage, and F is the fraction defined by the input word, D, that is N bits wide.
• The number of input combinations represented by the input word D is
related to the number of bits in the word. 44 DAC Specifications
45 Types of DACs
1. Weighted Resistor DAC
2. R-2R Ladder DAC
A binary-weighted resistor DAC consists of a network of
resistors which are binary-weighted. Whereas the R-2R ladder DAC has a ladder network of resistors of values R and 2R.
46 1. Weighted Resistor DAC
47 Fig. 1. 4-bit weighted resistor DAC
48 49 50 2. R-2R Ladder DAC
The R-2R Ladder DAC overcomes the disadvantages of a
binary-weighted resistor DAC.
As the name suggests, R-2R Ladder DAC produces an
analog output, which is almost equal to the digital (binary) input by using an R-2R ladder network in the inverting adder circuit.
51 52 53 54 55 Analog to Digital Converter (ADC)
56 57 58 59 60 61 Linear Ramp-Type ADC A ramp-type analog-to-digital converter (also known as ramp- compare or time-base ADC)
It comprises five basic circuits:
a ramp generator, a counter, a comparator circuit, a clock pulse
generator, and a gate circuit, which are simultaneously operated to provide analog-to-digital conversion.
62 Two inputs are applied to the comparator. (1) analog input, and (2) linear ramp (sawtooth) voltage from the ramp generator.
The generator output is initiated
each time a start signal is applied.
The start signal also resets the
counter to zero and enables the gate circuit.
As long as the analog and ramp generator inputs to the comparator differ in magnitude, the clock pulse generator will be permitted to transmit pulses at a constant repetition rate through the gate into the counter.
When the two inputs to the comparator become equal, the comparator will generate a stop signal which disables the gate circuit and ends the comparison time interval.
The disabled gate circuit blocks the flow of pulses from the clock pulse generator to the counter. The number of pulses accumulated in the counter during the comparison time interval is proportional to the amplitude of the analog input voltage.
The counter indication is the desired digital representation of the input signal. 63 Dual Slope ADC
