Quantum Circuit Simulator based on FPGA

Yunpyo Hong Seokhun Jeon Sihyeong Park

Korea Electronics Technology Institute Korea Electronics Technology Institute Korea Electronics Technology Institute
2022 13th International Conference on Information and Communication Technology Convergence (ICTC) | 978-1-6654-9939-2/22/$31.00 ©2022 IEEE | DOI: 10.1109/ICTC55196.2022.9952408

SoC Platform Research Center SoC Platform Research Center SoC Platform Research Center
Seongnam-si, Korea Seongnam-si, Korea Seongnam-si, Korea
[email protected] [email protected] [email protected]

Byung-Soo Kim
Korea Electronics Technology Institute
SoC Platform Research Center
Seongnam-si, Korea
[email protected]

Abstract— The quantum computer is emerging technology (2) Our hardware can support simulation of any quantum
since it can resolve complex tasks such as factorization or search gate that represented by 2 x 2 matrix.
problem faster than classical computers. However, simulation of
the quantum computer is difficult because computational load (3) We implement various accelerating algorithm for
increases exponentially as the number of qubits used in the quantum simulation. The algorithm tries to avoid
circuit is increased. This paper proposes a hardware unnecessary multiplication and data transfer with
architecture for quantum circuit simulation. To implement external memory.
simulator smaller, our architecture operates based on a 1-input
The paper is organized as follows. In section 2, we
single gate regardless of the number of qubits used in the circuit
In addition, our architecture helps to reduce simulation time by
describes a basic theory of quantum and previous works for
skipping calculation and data transfer. The proposed quantum simulation. In section 3, we introduce our hardware
architecture is implemented on FPGA and the experimental architecture. Section 4 explains the experimental result.
results show that our architecture reduces 79.2% of the Finally, section 5 concludes the paper with the future research.
multiplication process when we simulate 20-qubit quantum
Fourier transform with a small hardware size. II. BACKGROUND
A. Basic of Quantum & Quantum Circuit
Keywords— quantum simulator, quantum circuit, quantum
computer, FPGA, QFT The main difference between conventional computer and
quantum computer is a qubit which is the atomic element of
I. INTRODUCTION the quantum computer. The entanglement and superposition
In the past years, researchers and big tech companies have are the key features of the qubit that quantum computer is
increased interest in quantum computers. This is because the superior than conventional computer. With these two feature,
quantum computer is expected to become the next game one qubit can store more information in comparison with one
changer like artificial intelligence through promising bit which can store only 0 or 1.
algorithms such as Grover’s algorithm[1] or Shor’s The state of one qubit can be expressed mathematically as
algorithm[2] that quantum computers have shown. equation (1) where α, β are complex number. These two
However, implementing real quantum computer is proved number represent the probability of measuring |0> and |1>
to be a challenging task because it requires near absolute zero each other.
temperature to control quantum computer. It makes the cost of
implementing quantum computer too expensive. Thus we 1 0
|  α|0  |1  α       (1)
cannot meet the demand of quantum computer for researching 0 1
quantum algorithm. For this reason, there is a field to study
To modify the state of qubit, a quantum gate is applied to
quantum simulation method using conventional computer. It
qubits. Their operations can be represented unitary matrix
mimics the characteristics of quantum in conventional
transformations by mathematically, so any gate can be
computer, thus it is used by many researchers who have
described by 2  2 matrix where N is the number of input
difficulty accessing quantum computers.
qubit for the gate. Fig. 1 is some example of Quantum gates
The simulation of quantum circuit requires tremendous and its matrix representations. Quantum circuit is made by
resource and simulation time because they grow exponentially series of gates and using this, we can solve the problem that
when the number of qubit increases. Therefore, simulation we want. Quantum circuit acts on quantum state represented
using FPGAs having inherent parallel behavior, is a good by 2  1 state vector. Each element in the state vector
choice to reduce simulation time. represent the probability of measuring qubits.
In this paper, we introduce quantum state vector simulator
using FPGA. The main contributions of this paper are
described below.
(1) We implement the quantum circuit simulator in
FPGA. Our small architecture can simulate large
qubit quantum circuit since it operates based on a 1-
input single gate. Fig. 1. Example of Quantum Gate

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 A. 1st stage
The 1st stage is state grouping. In this stage, we use the
characteristic that an element of output state vector which
applied by a single-qubit gate is only affected by two elements
of input state vector. A single-qubit gate is only applied one
qubit, thus it cannot modify the other qubit’s state. It means
the only difference between the input and output elements
indexes is the qubit index applied with the gate and the rest of
Fig. 2. Block Diagram of 4-Qubit QFT the input index is being equal to the output index. This stage
groups and sends these two-state indexes to the next stage.
B. Previous works Here is the example of this characteristic. In a 2-qubit
Many approaches have been conducted for quantum quantum circuit, when U gate is applied to a qubit0, output
circuit simulation using conventional computers. IBM has state can be represented as |Out> in Eq (3) where input state is
provided frameworks for quantum circuit, named qiskit[3], represented as |In> in Eq (2). In these equation, we can find
and google opened tutorial for image classification using that the element of output state for |00> uses only the element
TensorFlow Quantum(TFQ)[4]. Some researches in FPGA of input state for |00>(a) and |10>(c), the element of output
field studied simulation for specific algorithms. Zhang’s state for |01> uses only the element of input state for |01>(b),
work[5] implements simulator for Shor’s algorithm up to 17 and |11>(d). Thus, we can group |00> and |10> for one, and
qubits, Qian’s work[6] implements simulator for |01> and |11> for the other.
QFT(Quantum Fourier Transform). And Mahmud’s work[7]
implements 4-qubit QFT and Grover’s search algorithms on a |In> = a|00> + b|01> + c|10> + d|11> (2)
single FPGA node. About software algorithm side, Fatima’s
work[8] accelerates simulation using CPU by applying |   |0 ⊗ |0   |0 ⊗ |1 
different strategy depending on quantum gates.
C. QFT(Quantum Fourier Transform)  |1 ⊗ |0   |1 ⊗ |1 
The quantum Fourier transform (QFT) is the quantum   1   1
version of the discrete Fourier transform. It is part of many      0 ⊗ |0       0 ⊗ |1 

quantum algorithm such as Shor's algorithm[2], quantum
phase estimation. In Abellán’s work[9] uses QFT module for   0   0
adder using quantum. Fig. 2 is the example of quantum circuit      1 ⊗ |0       1 ⊗ |1 

for 4-qubit QFT.
 
III. PROPOSED ARCHITECTURE    ⊗ |0      ⊗ |1 
 
Fig 3. illustrates our block diagram of quantum circuit
simulator. The biggest problem in quantum simulation is that  
computational load increases exponentially when the number    ⊗ |0      ⊗ |1 
 
of qubit is increased. To alleviate this problem, we simulate
the circuit based on 2 x 2 gate regardless of the number of   
qubits that a circuit used. This technique makes our hardware   
smaller even though we support a big-size quantum circuit.       (3)
 
Our architecture simulates the gates in the circuit one by one.   
In addition, our architecture is focused on avoiding useless
computation. For this purpose, we divide the main block with B. 2nd stage
three stages. and we implement APB interface for setting In 2nd stage, we try to eliminate unnecessary data transfer
parameters such as gate data and AHB interface for from external memory. As shown in matrix representation in
communication with external memory. Fig. 1, a lot of gate contain 0 or 1 in their matrix, so we can
skip data transfer if element of output state isn’t changed from
that of input state. For example, assume U gate is Z or T gate
in Eq (3), the gate doesn’t change the |00> and |01> because
  1 and   0. So we doesn’t need to request data to
external memory.
The second scheme is skipping control gate. A control gate
is 2-input gate. The one input is for control qubit and the other
input is for target qubit. It transforms a state of target qubit
when control qubit is 1, the otherwise, it just bypass the gate.
It means that we can skip calculation by checking the state of
control qubit. Using this scheme, the half of output states can
be skipped both multiplication and data transfer from external
memory. In addition we can calculate 2-input gates using 2 x
Fig. 3. Block Diagram of Proposed Architecture 2 matrix by this scheme since transform is only applied to one
qubit.

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 C. 3rd stage TABLE II. FPGA RESOURCE UTILIZATION

In above stage, we try to skip useless data transfer as many Multiply

QFT[11] Our
Circuit Skip
as possible. The final stage is for multiplying element of input Ratio(%)
emulation (s) emulation (s)
state vector with gate. This stage receives grouped state from
the 1st stage, and load the elements of input state vector from 4-QFT 52.5 3.9  10 6.3  10
external memory.
6-QFT 62.5 1.2  10 5.2  10
In this stage, we also try to skip multiply operations. The
output state(Out) can be calculated using Eq (4-6).  and 8-QFT 68.1 - 3.4  10
 are grouped states from the 1st stage, and  ,  ,  and
 are quantum gate elements represented by matrix. In 12-QFT 74.0 - 1.1  10
matrix representation of quantum gate, there are kind of
number that doesn’t need to multiplication for processing such 16-QFT 77.2 - 2.7  10
as 0, ±1. So we can skip multiplier by checking values of
20-QFT 79.2 - 6.5  10
quantum gate.

   
        (4) In the future work, we will attempt to make our simulator
 
more faster. To do so, we will research new features for our
hardware scheme and invent a software framework for our
         (5)
hardware acceleration.
         (6) ACKNOWLEDGMENT
This work was supported by the Technology Innovation
IV. EXPERIMENTA RESULT Program (20000868, Development of AI 3D IC Fabrication
The proposed architecture was synthesized and emulated Process Technology using a FO Package) funded By the
in Xilinx’s Kintex UltraScale (XCKU115) FPGA platform at Ministry of Trade, Industry & Energy (MOTIE, Korea).
160MHz. To demonstrate our scheme, we simulated various
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