System-on-Chip (SoC) with Zynq:

● Definition of SoC:
● A single silicon chip integrating the functionality of an entire system.
● Replaces multiple physical chips used on a Printed Circuit Board (PCB).
● Traditional SoC (ASIC-based):
● Combines digital, analog, RF components, and mixed-signal blocks (e.g.,
ADCs, DACs).
● Handles all aspects of a digital system: processing, logic, interfacing, and
memory.
● Advantages of SoCs:
● Lower cost and smaller physical size.
● Faster and more secure data transfer between components.
● Higher overall system speed and better reliability.
● Lower power consumption.
● Disadvantages of ASIC-based SoCs:
● High development cost and time (suitable for high-volume markets only).
● Lack of flexibility and upgradeability.
● Poor choice for low or medium-volume markets.
● Need for a Flexible Solution:
● Fast time-to-market and adaptability required for many applications.
● FPGA-based SoCs provide reconfigurability, enabling upgrades and
flexibility.
● Zynq: The All-Programmable SoC (APSoC):
● Combines a Processing System (PS) with a Programmable Logic (PL)
section:
● PS: Dual-core ARM Cortex-A9 for software routines and operating
systems.
● PL: FPGA-equivalent for high-speed logic, arithmetic, and data flow
subsystems.
● Integrated memory, peripherals, and high-speed communication
interfaces.
● Key Benefits of Zynq:
● Hardware-software partitioning for optimized system design.
● Industry-standard interfaces link PL and PS for seamless integration.
● Ideal for implementing flexible and reconfigurable SoCs.

Simple Anatomy of an Embedded SoC:

● Basic Components of Digital Systems:
 ● Includes a processor, memory, peripherals, and buses for interconnection.
● Communication between components occurs via direct links or shared
buses with protocols.
● Processor as the Core:
● Runs the software system, typically a software stack:
● Top layer: Applications (often OS-based).
● Lower layer: Interfaces for hardware communication.
● Types of Peripherals:
● Coprocessors: Optimized for specific tasks to assist the main processor.
● Interface Cores: Handle external interactions (e.g., LEDs, switches,
codecs).
● Additional Memory: Extends system storage capacity.
● Peripherals as Modular Blocks:
● Designed, tested, and integrated as independent units.
● Can be reused across systems.
● Mapping to Zynq Architecture:
● Processing System (PS):
● Fixed architecture hosting the ARM Cortex-A9 processor and
system memory.
● Programmable Logic (PL):
● Fully flexible for creating custom or reusable peripherals.
● AXI Interfaces: Link PS and PL for communication.
● Software System in Zynq:
● Hosted on the processor within the PS.
● Organized in a hierarchical structure, starting with the OS and extending
to hardware interface layers.
● Key Advantage of Zynq:
● Combines the fixed PS for system operations with the flexible PL for
custom hardware designs.

Raising the Level of Abstraction in FPGA/Zynq Design

● Trend in Design Processes:
● Increasing abstraction reduces the need for explicit design input.
● Supports robust testing and accelerates the design process.
● Advances in High-Level Synthesis (HLS):
● Designers use higher-level specifications instead of low-level RTL
methods.
● Tools infer logic and optimize designs based on user-supplied directions.
● Advantages of HLS:
 ● Simplifies design creation with less detail required.
● Accelerates the development process.
● Vivado HLS Tool by Xilinx:
● A high-level synthesis tool for Xilinx devices.
● Produces reliable, repeatable designs.
● Will be discussed further in the book.
● Key Requirement:
● Trust in development tools to produce robust and optimized designs.

Design Reuse:
● Advantages of FPGA/Zynq for Embedded System Design:
● Structured Programmable Logic (PL) with well-defined performance
characteristics.
● Integration of hardware characteristics into software development tools.
● A stable, common development platform promotes design reuse.
● Intellectual Property (IP) Functional Blocks:
● Represent peripheral components in the system.
● Can be sourced from:
● Xilinx libraries (bundled with tools).
● Previous projects.
● Third parties or open-source repositories.
● These IPs are pre-tested and verified, reducing development effort.
● Benefits of Design Reuse:
● No need to redesign standard components, as they can be reused.
● Accelerates development and lowers costs by reusing existing IP blocks.
● Supports the SoC design philosophy: “Why reinvent the wheel?”
● Key Design Themes in SoC Development:
● Sources of IP:
● Xilinx-provided libraries.
● Self-generated custom IP.
● Third-party IP sources.
● IP Integration:
● Tools and methods to connect and interact with different IP blocks.
● Packaging IP:
● Use of IP-XACT format for sharing and reusing design elements.
● Focus of Relevant Chapters:
● Chapter 13: Mechanisms for generating and reusing IP.
● Chapter 18: Packaging IP for reuse in standard formats.
SoC Design Flow

Requirements and Specification

● Start with a Specification: Define system parameters, functionality, interfaces,

performance criteria, and target platform before design begins.
● Refinement Over Time: The specification evolves and becomes more detailed
during the project.

System Design

● Top-Down Approach:

○ Define system-level interfaces and parameters first.

○ Break into subsystems with their functions and interactions.
○ Decompose further into smaller components if needed.
● Hardware vs. Software Partitioning:

○ Software (PS): Handles general tasks, OS, and user interfaces.

○ Hardware (PL): Manages intensive tasks, parallel processing, and
specialized computations.
● Zynq Advantage:

○ Close coupling of PS and PL via high-speed, low-latency AXI links.

○ Leverages PS features (NEON, FPU) and PL resources (BlockRAMs,
DSP48E1 slices).
● Vivado IDE:

○ Acts as the central design tool.

○ Supports iterative hardware-software co-design using tools like System
Generator and Vivado HLS.

Hardware Development and Testing

● Hardware Design in Vivado:

○ Use IP Integrator to create block diagrams from prebuilt or custom IPs.

○ Connect blocks via AXI interfaces and configure the PS.
● Testing Tools:
 ○ Design Rule Checks (DRCs): Ensure connection integrity.
○ Standalone Testing: Validate custom and third-party IP blocks using
simulations.
○ Integrated Testing: Test hardware with running software and inspect
signals.
● Hardware in the Loop (HIL):

○ Run part of the system on real hardware and simulate the rest for
inspection.

Software Development and Testing

● Software Stack:

○ Board Support Package (BSP): Provides drivers and functions for

hardware interaction.
○ Operating System (OS): Runs on top of the BSP (Linux, RTOS, or
bare-metal applications).
○ Applications: User-level programs at the highest abstraction.
● SDK Environment:

○ Import hardware configurations from Vivado.

○ Develop BSPs and software applications.
○ Debug and test software with tools like XMD and GDB.
● Testing Process:

○ Use HIL to test software with hardware.

○ Test and debug the PS and PL in tandem (e.g., *.elf files for PS, *.bit files
for PL).

Key Iterative Process

1. Design hardware in Vivado and export it to SDK.

2. Develop software in SDK and test it on hardware.
3. Refine hardware/software based on testing and repeat.

Zynq-Specific Features

● Dual-Core Processing: Option to run different OS types on each core.

● Custom Hardware-Software Integration: Tailored BSP ensures efficient
operation.
 ● Flexible Programming Options: Use JTAG, Ethernet, or Vivado Simulator for
deployment and testing.

Overview of Zynq PS

● All Zynq devices feature a dual-core ARM Cortex-A9 processor as the PS:
● A hard processor optimized as a dedicated silicon element.
● Higher performance compared to soft processors like Xilinx MicroBlaze.
● Soft Processors in PL:
● MicroBlaze processors can be deployed in the PL to handle specific, less
demanding tasks.
● Enhances performance by offloading low-level tasks from ARM
processors.

Key Components of Zynq PS

● Application Processing Unit (APU):

● Dual ARM Cortex-A9 cores, each with:
● NEON Media Processing Engine (MPE): Supports SIMD (Single
Instruction Multiple Data).
● Floating Point Unit (FPU): Accelerates floating-point operations.
● Memory Management Unit (MMU): Handles virtual-to-physical
address translation.
● Level 1 Cache: 32KB each for instructions and data.
● Shared resources:
● Level 2 Cache (512KB): Shared by both cores.
● On-Chip Memory (256KB).
● Snoop Control Unit (SCU): Maintains cache coherency and
interfaces with PL via ACP.
● Peripheral Resources:
● Interfaces, cache memory, memory interconnects, and clock generation
circuitry.
● Timers and an interrupt controller included within the APU.

Processing Enhancements

● NEON Engine:
● SIMD processing for parallel data operations (e.g., image and signal
processing).
● Handles multiple input vectors simultaneously for efficient computation.
 ● Supports various data types: integers, single-precision floating point,
half-precision floating point.
● Floating Point Unit (FPU):
● Hardware acceleration for floating-point operations (single and double
precision).
● Compliant with IEEE 754 standard.

Programming and Software Development

● Xilinx Software Development Kit (SDK):

● Includes tools for ARM instruction development.
● Supports ARM, Thumb (16/32-bit), and Java bytecode instruction sets.
● NEON Programming:
● SIMD instructions can be explicitly used or inferred through structured C
code.
● Ideal for algorithms like FIR filters, FFTs, and video/image processing.

Performance Features

● ARM Cortex-A9 cores operate at up to 1 GHz, depending on the Zynq device.

● Cache and on-chip memory minimize latency, improving processor performance.

This architecture ensures flexibility, high performance, and support for complex tasks
across hardware and software domains.

Zynq Programmable Logic (PL) Overview - Key Points

● Main Components of PL:

○ Configurable Logic Block (CLB):

■ Consists of slices and connected via switch matrices.

■ CLBs contain LUTs (for logic functions), Flip-Flops (for sequential
logic), and routing for connections.
○ Slice:

■ Sub-unit within CLBs that implements combinatorial and sequential

logic.
■ Contains LUTs, Flip-Flops, and other logic resources.
○ Lookup Table (LUT):

■ Implements logic functions, RAM, ROM, or shift registers.

 ■ Can combine for larger logic functions or memories.
○ Flip-Flop (FF):

■ Implements 1-bit registers with reset functionality.

○ Switch Matrix:

■ Provides flexible routing between CLBs and other resources.

○ Carry Logic:

■ Propagates signals between slices for arithmetic operations.

○ Input/Output Blocks (IOBs):

■ Interface between logic resources and external circuitry.

■ Each IOB handles a 1-bit input or output.
● Special Resources:
○ Block RAM:

■ Used for dense memory requirements like RAM, ROM, or FIFO

buffers.
■ Can store up to 36KB of data and supports Error Correction
Coding (ECC).
■ More efficient than Distributed RAM for large data storage.
○ DSP48E1 Slices:

■ High-speed arithmetic resources for complex operations.

■ Ideal for tasks like Finite Impulse Response (FIR) filters, signal
processing, and communications.
■ Can perform SIMD operations, multiple arithmetic functions, and
logical operations.
■ Supports operations like addition, subtraction, multiplication,
and more.
● Designing with PL:
○ Use Block RAM and DSP48E1 slices for computationally demanding
tasks.
○ PL acceleration complements tasks in the PS by offloading specific
functions to DSP and RAM resources.
○ Achieves high performance and efficiency for parallel, deterministic
computations.
● Key Benefits of PL:
○ High-frequency operation and low power consumption.
 ○ Flexibility to implement complex, parallel algorithms directly in the FPGA
fabric.

This summary highlights the structure and functionality of the Programmable Logic in
Zynq devices, emphasizing key components like CLBs, Block RAM, and DSP48E1
slices for efficient computation and memory management.