3.

3V 128M-BIT
SERIAL FLASH MEMORY WITH
DUAL/QUAD SPI

For Industrial & Industrial Plus Grade

ChuangFeiXin-Technology
 GM25Q128A
1 GENERAL DESCRIPTIONS ..............................................................................................................................1

2 FEATURE............................................................................................................................................................1

3 PACKAGE TYPES AND PIN CONFIGURATIONS ............................................................................................2

3.1 Pin Configuration SOIC 208-mil ..................................................................................................................2

3.2 Pad Configuration WSON 6x5-mm/ 8x6-mm ..............................................................................................2
3.3 Pin Description SOIC 208-mil, WSON 6x5-mm / 8x6-mm ..........................................................................2
3.4 Pin Configuration SOIC 300-mil ..................................................................................................................3
3.5 Pin Description SOIC 300-mil ......................................................................................................................3
3.6 Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array) ........................................................................4
3.7 Ball Description TFBGA 8x6-mm .................................................................................................................4
3.8 Ball Configuration WLCSP ..........................................................................................................................5
3.9 Ball Description WLCSP24 ..........................................................................................................................5

4 PIN DESCRIPTIONS ..........................................................................................................................................6

4.1 Chip Select (/CS) .........................................................................................................................................6
4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) ...........................................................6
4.3 Write Protect (/WP) ......................................................................................................................................6
4.4 HOLD (/HOLD) ............................................................................................................................................6
4.5 Serial Clock (CLK) .......................................................................................................................................6

5 BLOCK DIAGRAM .............................................................................................................................................7

6 FUNCTIONAL DESCRIPTIONS .........................................................................................................................8

6.1 Standard SPI Instructions ............................................................................................................................8

6.2 Dual SPI Instructions ...................................................................................................................................8
6.3 Software Reset ............................................................................................................................................8
6.4 Write Protection ...........................................................................................................................................8
6.4.1 Write Protect Features............................................................................................................................................. 8

7 STATUS AND CONFIGURATION REGISTERS ............................................................................................. 10

7.1 Status Registers ....................................................................................................................................... 10

7.1.1 Erase/Write In Progress (BUSY) – Status Only ..................................................................................................... 10
7.1.2 Write Enable Latch (WEL) – Status Only............................................................................................................... 10
7.1.3 Block Protect Bits (BP2, BP1, BP0) – Volatile/Non-Volatile Writable ..................................................................... 10
7.1.4 Top/Bottom Block Protect (TB) – Volatile/Non-Volatile Writable ............................................................................ 11
7.1.5 Sector/Block Protect Bit (SEC) – Volatile/Non-Volatile Writable ............................................................................ 11
7.1.6 Complement Protect (CMP) – Volatile/Non-Volatile Writable................................................................................. 11
7.1.7 Status Register Protect (SRP1, SRP0) – Volatile/Non-Volatile Writable................................................................ 11
7.1.8 Erase/Program Suspend Status (SUS) – Status Only ........................................................................................... 12
7.1.9 Security Register Lock Bits (LB3, LB2, LB1) – Volatile/Non-Volatile OTP Writable ............................................... 12
7.1.10 Quad Enable (QE) – Volatile/Non-Volatile Writable ........................................................................................... 12
7.1.11 Output Driver Strength (DRV1, DRV0) – Volatile/Non-Volatile Writable ............................................................ 13
7.1.12 Reserved Bits – Non Functional ........................................................................................................................ 13
7.1.13 GM25Q128A Status Register Memory Protection (CMP = 0) ............................................................................ 14
7.1.14 GM25Q128A Status Register Memory Protection (CMP = 1) ............................................................................ 15
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 GM25Q128A
8 INSTRUCTIONS .............................................................................................................................................. 16

8.1 Device ID and Instruction Set Tables ....................................................................................................... 16

8.1.1 Identification .......................................................................................................................................................... 16
8.1.2 Instruction Set Table 1 (Standard SPI Instructions) (1) .......................................................................................... 16
8.1.3 Instruction Set Table 2 (Dual/Quad SPI Instructions)............................................................................................. 18
8.2 Instruction Descriptions ............................................................................................................................ 19
8.2.1 Write Enable (06h)................................................................................................................................................. 19
8.2.2 Write Enable for Volatile Status Register (50h) ..................................................................................................... 19
8.2.3 Write Disable (04h) ................................................................................................................................................ 20
8.2.4 Read Status Register-1 (05h), Status Register-2 (35h) & Status Register-3 (15h)................................................ 20
8.2.5 Write Status Register-1 (01h), Status Register-2 (31h) & Status Register-3 (11h) ................................................ 21
8.2.6 Read Data (03h) .................................................................................................................................................... 22
8.2.7 Fast Read (0Bh) .................................................................................................................................................... 23
8.2.8 Fast Read Dual Output (3Bh) ................................................................................................................................ 24
8.2.9 Fast Read Quad Output (6Bh)............................................................................................................................... 25
8.2.10 Fast Read Dual I/O (BBh) (1) ............................................................................................................................ 26
8.2.11 Fast Read Quad I/O (EBh) ................................................................................................................................ 28
8.2.12 Word Read Quad I/O (E7h) ............................................................................................................................... 30
8.2.13 Set Burst with Wrap (77h) ................................................................................................................................. 32
8.2.14 Page Program (02h) .......................................................................................................................................... 33
8.2.15 Quad Input Page Program (32h) ....................................................................................................................... 34
8.2.16 Sector Erase (20h) ............................................................................................................................................ 35
8.2.17 32KB Block Erase (52h) .................................................................................................................................... 36
8.2.18 64KB Block Erase (D8h) ................................................................................................................................... 37
8.2.19 Chip Erase (C7h / 60h)...................................................................................................................................... 38
8.2.20 Erase / Program Suspend (75h) ........................................................................................................................ 39
8.2.21 Erase / Program Resume (7Ah) ........................................................................................................................ 40
8.2.22 Power-down (B9h)............................................................................................................................................. 41
8.2.23 Release Power-down (ABh) .............................................................................................................................. 42
8.2.24 Read Manufacturer / Device ID (90h) ................................................................................................................ 43
8.2.25 Read JEDEC ID (9Fh) ....................................................................................................................................... 44
8.2.26 Read SFDP Register (5Ah) ............................................................................................................................... 45
8.2.27 Erase Security Registers (44h) ......................................................................................................................... 49
8.2.28 Program Security Registers (42h) ..................................................................................................................... 50
8.2.29 Read Security Registers (48h) .......................................................................................................................... 51
8.2.30 Enable Reset (66h) and Reset Device (99h) ..................................................................................................... 52

9 ELECTRICAL CHARACTERISTICS ............................................................................................................... 53

9.1 Absolute Maximum Ratings (1) ................................................................................................................ 53

9.2 Operating Ranges .................................................................................................................................... 53
9.3 Power-Up Power-Down Timing and Requirements .................................................................................. 54
9.4 DC Electrical Characteristics .................................................................................................................... 55
9.5 AC Measurement Conditions ................................................................................................................... 56
9.6 AC Electrical Characteristics .................................................................................................................... 57
9.7 Serial Output Timing ................................................................................................................................. 59

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 GM25Q128A
9.8 Serial Input Timing .................................................................................................................................... 59
9.9 /WP Timing ............................................................................................................................................... 59

10 PACKAGE SPECIFICATIONS..................................................................................................................... 60

10.1 8-Pin SOIC 208-mil (Package Code S) .................................................................................................... 60

10.2 16-Pin SOIC 300-mil (Package Code F) .................................................................................................. 61
10.3 8-Pad WSON 6x5-mm (Package Code P) ............................................................................................... 62
10.4 8-Pad WSON 8x6-mm (Package Code E) ............................................................................................... 63
10.5 24-Ball TFBGA 8x6-mm (Package Code B, 5x5-1 ball array) .................................................................. 64
10.6 24-Ball TFBGA 8x6-mm (Package Code C, 6x4 ball array) ..................................................................... 65
10.7 24-Ball WLCSP (Package Code Y) .......................................................................................................... 66

11 ORDERING INFORMATION ........................................................................................................................ 67

12 REVISION HISTORY ................................................................................................................................... 68

III
 GM25Q128A
1 GENERAL DESCRIPTIONS
The GM25Q128A (128M-bit) Serial Flash memory provides a storage solution for systems with limited space, pins
and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are
ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing voice, text and
data. The device operates on a single 2.7V to 3.6V power supply with current consumption as low as 3µA for power-
down. All devices are offered in space-saving packages.

The GM25Q128A array is organized into 65,536 programmable pages of 256-bytes each. Up to 256 bytes can be
programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128 (32KB block erase),
groups of 256 (64KB block erase) or the entire chip (chip erase). The GM25Q128A has 4,096 erasable sectors and
256 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data
and parameter storage. (See Figure 2.)

The GM25Q128A supports the standard Serial Peripheral Interface (SPI), Dual/Quad I/O SPI: Serial Clock, Chip
Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2 and I/O3. Single SPI clock frequencies of GM25Q128A of up to
104MHz are supported, and equivalent clock rates of 208MHz (104MHz x 2) for Dual I/O and 320MHz (80MHz x 4)
for Quad I/O when using the Fast Read Dual/Quad I/O are supported. These transfer rates can outperform standard
Asynchronous 8 and 16-bit Parallel Flash memories.

Additionally, the device supports JEDEC standard manufacturer and device ID and SFDP, and a 64-bit Unique
Serial Number and three 256-bytes Security Registers.

2 FEATURE
• New Family of SPI Flash Memories • Flexible Architecture with 4KB sectors
– GM25Q128A: 128M-bit / 16M-byte – Uniform Sector/Block Erase (4K/32K/64K-Byte)
– Standard SPI: CLK, /CS, DI, DO, /WP, /Hold – Program 1 to 256 byte per programmable page
– Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold – Erase/Program Suspend & Resume
– Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3 • Advanced Security Features
– Software Reset – Software and Hardware Write-Protect
• Highest Performance Serial Flash – Power Supply Lock-Down and OTP protection
– 104MHz Single SPI clocks – Top/Bottom, Complement array protection
– 160/320MHz equivalent Dual/Quad SPI – 64-Bit Unique ID for each device
– More than 100,000 erase/program cycles – Discoverable Parameters (SFDP) Register
– More than 20-year data retention – 3X256-Bytes Security Registers with OTP locks
• Efficient “Continuous Read” – Volatile & Non-volatile Status Register Bits
– Continuous Read with 8/16/32/64-Byte Wrap • Space Efficient Packaging
– As few as 8 clocks to address memory – 8-pin SOIC / VSOP 208-mil
• Low Power, Wide Temperature Range – 8-pin PDIP 300-mil
– Single 2.7V to 3.6V supply – 8-pad WSON 6x5-mm / 8x6-mm
– 4mA active current, <3μA Power-down (typ.) – Contact CFX for KGD and other options
– -40°C to +85°C operating range

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 GM25Q128A
3 PACKAGE TYPES AND PIN CONFIGURATIONS
3.1 Pin Configuration SOIC 208-mil

Figure 1a. GM25Q128A Pin Assignments, 8-pin SOIC 208-mil (Package Code S)

3.2 Pad Configuration WSON 6x5-mm/ 8x6-mm

Figure 1b. GM25Q128A Pad Assignments, 8-pad WSON 6x5-mm/ 8x6-mm (Package Code P/E)

3.3 Pin Description SOIC 208-mil, WSON 6x5-mm / 8x6-mm

PAD NO. PAD NAME I/O FUNCTION
1 /CS I Chip Select Input
2 DO (IO1) I/O Data Output (Data Input Output 1) (1)
3 /WP (IO2) I/O Write Protect Input (Data Input Output 2) (2)
4 GND Ground
5 DI (IO0) I/O Data Input (Data Input Output 0) (1)
6 CLK I Serial Clock Input
7 /HOLD (IO3) I/O Hold Input (Data Input Output 3) (2)
8 VCC Power Supply
Notes:
1. IO0 and IO1 are used for Standard and Dual SPI instructions.
2. IO0 – IO3 are used for Quad SPI instructions, /HOLD function is only available for Standard/Dual SPI.

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 GM25Q128A
3.4 Pin Configuration SOIC 300-mil

Figure 1c. GM25Q128A Pin Assignments, 16-pin SOIC 300-mil (Package Code F)

3.5 Pin Description SOIC 300-mil

PIN NO. PIN NAME I/O FUNCTION
1 /HOLD (IO3) I/O Hold or Input (Data Input Output 3) (2)
2 VCC Power Supply
3 N/C No Connect
4 N/C No Connect
5 N/C No Connect
6 N/C No Connect
7 /CS I Chip Select Input
8 DO (IO1) I/O Data Output (Data Input Output 1) (1)
9 /WP (IO2) I/O Write Protect Input (Data Input Output 2) (2)
10 GND Ground
11 N/C No Connect
12 N/C No Connect
13 N/C No Connect
14 N/C No Connect
15 DI (IO0) I/O Data Input (Data Input Output 0) (1)
16 CLK I Serial Clock Input
Notes:
1. IO0 and IO1 are used for Standard and Dual SPI instructions.
2. IO0 – IO3 are used for Quad SPI instructions, /HOLD function is only available for Standard/Dual SPI.

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 GM25Q128A
3.6 Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array)

Figure 1d. GM25Q128A Ball Assignments, 24-ball TFBGA 8x6-mm (Package Code B/C)

3.7 Ball Description TFBGA 8x6-mm

BALL NO. PIN NAME I/O FUNCTION
B2 CLK I Serial Clock Input
B3 GND Ground
B4 VCC Power Supply
C2 /CS I Chip Select Input
C4 /WP (IO2) I/O Write Protect Input (Data Input Output 2) (2)
D2 DO (IO1) I/O Data Output (Data Input Output 1) (1)
D3 DI (IO0) I/O Data Input (Data Input Output 0) (1)
D4 /HOLD (IO3) I/O Hold Input (Data Input Output 3) (2)
Multiple NC No Connect
Notes:
1. IO0 and IO1 are used for Standard and Dual SPI instructions
2. IO0 – IO3 are used for Quad SPI instructions, /HOLD function is only available for Standard/Dual SPI.

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 GM25Q128A
3.8 Ball Configuration WLCSP

Figure 1e. GM25Q128A Ball Assignments, 24-ball WLCSP (Package Code Y)

3.9 Ball Description WLCSP24

BALL NO. PIN NAME I/O FUNCTION
B2 VCC Power Supply
B3 /CS I Chip Select Input
C2 /HOLD (IO3) I/O Hold Input (Data Input Output 3) (2)
C3 DO (IO1) I/O Data Output (Data Input Output 1) (1)
D2 CLK I Serial Clock Input
D3 /WP (IO2) I/O Write Protect Input (Data Input Output 2) (2)
E2 DI (IO0) I/O Data Input (Data Input Output 0) (1)
E3 GND Ground
Notes:
1. IO0 and IO1 are used for Standard and Dual SPI instructions.
2. IO0 – IO3 are used for Quad SPI instructions, /HOLD function is only available for Standard/Dual SPI.

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 GM25Q128A
4 PIN DESCRIPTIONS
4.1 Chip Select (/CS)
The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is deselected
and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When deselected, the devices
power consumption will be at standby levels unless an internal erase, program or write status register cycle is in
progress. When /CS is brought low the device will be selected, power consumption will increase to active levels
and instructions can be written to and data read from the device. After power-up, /CS must transition from high to
low before a new instruction will be accepted. The /CS input must track the VCC supply level at power-up and
power-down (see Write Protection and Figure 36b). If needed a pull-up resister on the /CS pin can be used to
accomplish this.

4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)
The GM25Q128A supports standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions use the
unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising edge of the
Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read data or status from the
device on the falling edge of CLK.

Dual and Quad SPI instructions use the bidirectional IO pins to serially write instructions, addresses or data to the
device on the rising edge of CLK and read data or status from the device on the falling edge of CLK. Quad SPI
instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set. When QE=1, the /WP pin
becomes IO2 and the /HOLD pin becomes IO3.

4.3 Write Protect (/WP)

The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in conjunction with
the Status Register’s Block Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits and Status Register Protect (SRP)
bits, a portion as small as a 4KB sector or the entire memory array can be hardware protected. The /WP pin is
active low.

4.4 HOLD (/HOLD)

The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought low, while /CS
is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored (don’t care). When
/HOLD is brought high, device operation can resume. The /HOLD function can be useful when multiple devices are
sharing the same SPI signals. The /HOLD pin is active low. When the QE bit of Status Register-2 is set for Quad
I/O, the /HOLD pin function is not available since this pin is used for IO3. See Figure 1a-c for the pin configuration
of Quad I/O operation.

4.5 Serial Clock (CLK)

The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. (See SPI Operations)

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 GM25Q128A
5 BLOCK DIAGRAM

Figure 2. GM25Q128A Serial Flash Memory Block Diagram

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 GM25Q128A
6 FUNCTIONAL DESCRIPTIONS
6.1 Standard SPI Instructions
The GM25Q128A is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK), Chip
Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions use the DI input pin to
serially write instructions, addresses or data to the device on the rising edge of CLK. The DO output pin is used to
read data or status from the device on the falling edge of CLK.

SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3
concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not being transferred
to the Serial Flash. For Mode 0, the CLK signal is normally low on the falling and rising edges of /CS. For Mode 3,
the CLK signal is normally high on the falling and rising edges of /CS.

6.2 Dual SPI Instructions

The GM25Q128A supports Dual SPI operation when using instructions such as “Fast Read Dual Output (3Bh)” and
“Fast Read Dual I/O (BBh)”. These instructions allow data to be transferred to or from the device at two to three
times the rate of ordinary Serial Flash devices. The Dual SPI Read instructions are ideal for quickly downloading
code to RAM upon power-up (code-shadowing) or for executing non-speed-critical code directly from the SPI bus
(XIP). When using Dual SPI instructions, the DI and DO pins become bidirectional I/O pins: IO0 and IO1.

6.3 Software Reset

The GM25Q128A can be reset to the initial power-on state by a software Reset sequence. This sequence must
include two consecutive instructions: Enable Reset (66h) & Reset (99h). If the instruction sequence is successfully
accepted, the device will take approximately 30µS (tRST) to reset.

6.4 Write Protection

Applications that use non-volatile memory must take into consideration the possibility of noise and other adverse
system conditions that may compromise data integrity. To address this concern, the GM25Q128A provides several
means to protect the data from inadvertent writes.

6.4.1 Write Protect Features

• Device resets when VCC is below threshold
• Time delay write disable after Power-up
• Write enable/disable instructions and automatic write disable after erase or program
• Software and Hardware (/WP pin) write protection using Status Registers
• Additional Individual Block/Sector Locks for array protection
• Write Protection using Power-down instruction
• Lock Down write protection for Status Register until the next power-up

Upon power-up or at power-down, the GM25Q128A will maintain a reset condition while VCC is below the
threshold value of VWI, (See Power-up Timing and Voltage Levels and Figure 36a). While reset, all operations are
disabled and no instructions are recognized. During power-up and after the VCC voltage exceeds VWI, all program
and erase related instructions are further disabled for a time delay of tPUW. This includes the Write Enable, Page
Program, Sector Erase, Block Erase, Chip Erase and the Write Status Register instructions. Note that the chip
select pin (/CS) must track the VCC supply level at power-up until the VCC-min level and tVSL time delay is reached,
and it must also track the VCC supply level at power-down to prevent adverse command sequence. If needed a
pull-up resister on /CS can be used to accomplish this.

After power-up the device is automatically placed in a write-disabled state with the Status Register Write Enable

8
 GM25Q128A
Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector Erase, Block
Erase, Chip Erase or Write Status Register instruction will be accepted. After completing a program, erase or write
instruction the Write Enable Latch (WEL) is automatically cleared to a write disabled state of 0. Software controlled
write protection is facilitated using the Write Status Register instruction and setting the Status Register Protect
(SRP1, SRP0) and Block Protect (CMP, TB, BP[3:0]) bits. These settings allow a portion or the entire memory array
to be configured as read only. Used in conjunction with the Write Protect (/WP) pin, changes to the Status Register
can be enabled or disabled under hardware control. See Status Register section for further information. Additionally,
the Power-down instruction

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 GM25Q128A
7 STATUS AND CONFIGURATION REGISTERS
Three Status and Configuration Registers are provided for GM25Q128A. The Read Status Register-1/2/3
instructions can be used to provide status on the availability of the flash memory array, whether the device is write
enabled or disabled, the state of write protection, Quad SPI setting, Security Register lock status, Erase/Program
Suspend status, output driver strength, power-up. The Write Status Register instruction can be used to configure
the device write protection features, Quad SPI setting, Security Register OTP locks, and output driver strength.
Write access to the Status Register is controlled by the state of the non-volatile Status Register Protect bits (SRP0),
the Write Enable instruction, and during Standard/Dual SPI operations.

7.1 Status Registers

Figure 3a. Status Register-1

7.1.1 Erase/Write In Progress (BUSY) – Status Only

BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing a Page
Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register or Erase/Program
Security Register instruction. During this time the device will ignore further instructions except for the Read Status
Register and Erase/Program Suspend instruction (see tW, tPP, tSE, tBE, and tCE in AC Characteristics). When the
program, erase or write status/security register instruction has completed, the BUSY bit will be cleared to a 0 state
indicating the device is ready for further instructions.

7.1.2 Write Enable Latch (WEL) – Status Only

Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a Write Enable
Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write disable state occurs upon
power-up or after any of the following instructions: Write Disable, Page Program, Quad Page Program, Sector Erase,
Block Erase, Chip Erase, Write Status Register, Erase Security Register and Program Security Register.

7.1.3 Block Protect Bits (BP2, BP1, BP0) – Volatile/Non-Volatile Writable

The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3, and S2) that
provide Write Protection control and status. Block Protect bits can be set using the Write Status Register Instruction
(see tW in AC characteristics). All, none or a portion of the memory array can be protected from Program and Erase
instructions (see Status Register Memory Protection table). The factory default setting for the Block Protection Bits
is 0, none of the array protected.
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 GM25Q128A
7.1.4 Top/Bottom Block Protect (TB) – Volatile/Non-Volatile Writable
The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the Top (TB=0)
or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The factory default
setting is TB=0. The TB bit can be set with the Write Status Register Instruction depending on the state of the SRP1,
SRP0 and WEL bits.

7.1.5 Sector/Block Protect Bit (SEC) – Volatile/Non-Volatile Writable

The non-volatile Sector/Block Protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP0) protect either 4KB
Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array as shown in the
Status Register Memory Protection table. The default setting is SEC=0.

7.1.6 Complement Protect (CMP) – Volatile/Non-Volatile Writable

The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register (S14). It is used in
conjunction with SEC, TB, BP2, BP1 and BP0 bits to provide more flexibility for the array protection. Once CMP is
set to 1, previous array protection set by SEC, TB, BP2, BP1 and BP0 will be reversed. For instance, when CMP=0,
a top 64KB block can be protected while the rest of the array is not; when CMP=1, the top 64KB block will become
unprotected while the rest of the array become read-only. Please refer to the Status Register Memory Protection
table for details. The default setting is CMP=0.

7.1.7 Status Register Protect (SRP1, SRP0) – Volatile/Non-Volatile Writable

Three Status and Configuration Registers are provided for GM25Q128A. The Read Status Register-1/2/3
instructions can be used to provide status on the availability of the flash memory array, whether the device is write
enabled or disabled, the state of write protection, Quad SPI setting, Security Register lock status, Erase/Program
Suspend status, and output driver strength, The Write Status Register instruction can be used to configure the
device write protection features, Quad SPI setting, Security Register OTP locks, output driver. Write access to the
Status Register is controlled by the state of the non-volatile Status Register Protect bits (SRP1, SRP0), the Write
Enable instruction, and during Standard/Dual SPI operations, the /WP pin.

SRP1 SRP0 /WP Status Register Description

Software /WP pin has no control. The Status register can be written
0 0 X
Protection to after a Write Enable instruction, WEL=1. [Factory Default]
Hardware When /WP pin is low the Status Register locked and cannot
0 1 0
Protected be written to.
Hardware When /WP pin is high the Status register is unlocked and
0 1 1
Unprotected can be written to after a Write Enable instruction, WEL=1.
Power Supply Status Register is protected and cannot be written to again
1 0 X
Lock-Down until the next power-down, power-up cycle (1)
One Time Status Register is permanently protected and cannot be
1 1 X
Program (2) written to.
Notes:
1. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state.

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 GM25Q128A

Figure 3b. Status Register-2

7.1.8 Erase/Program Suspend Status (SUS) – Status Only

The Suspend Status bit is a read only bit in the status register (S15) that is set to 1 after executing an Erase/Program
Suspend (75h) instruction. The SUS status bit is cleared to 0 by Erase/Program Resume 7Ah) instruction as well
as a power-down, power-up cycle.

7.1.9 Security Register Lock Bits (LB3, LB2, LB1) – Non-Volatile OTP Writable
The Security Register Lock Bits (LB3, LB2, LB1, LB0) are non-volatile One Time Program (OTP) bits in Status
Register (S13, S12, S11, S10) that provide the write protect control and status to the Security Registers. The default
state of LB3-1 is 0, Security Registers are unlocked. The default state of LB0 is 1. LB3-1 can be set to 1 individually
using the Write Status Register instruction. LB3-1 are One Time Programmable (OTP), once it’s set to 1, the
corresponding 256-Byte Security Register will become read only permanently.LB0 value should be considered don't
care for read. This bit is set to 1. Security register 0 contains the Serial Flash Discoverable Parameters and is
always programmed and locked by CFX.

7.1.10 Quad Enable (QE) – Volatile/Non-Volatile Writable

The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that enables Quad SPI operation.
When the QE bit is set to a 0 state, the /HOLD are enabled, the device operates in Standard/Dual SPI modes. When
the QE bit is set to a 1 state, the Quad IO2 and IO3 pins re enabled, and /HOLD function is disabled, the device
operates in Standard/Dual/Quad SPI modes.

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 GM25Q128A

Figure 3c. Status Register-3

7.1.11 Output Driver Strength (DRV1, DRV0) – Volatile/Non-Volatile Writable

The DRV1 & DRV0 bits are used to determine the output driver strength for the Read operations.
DRV1, DRV0 Driver Strength
0, 0 100%
0, 1 75%
1, 0 50%(default)
1, 1 25%

7.1.12 Reserved Bits – Non Functional

There are a few reserved Status Register bits that may be read out as a “0” or “1”. It is recommended to ignore the
values of those bits. During a “Write Status Register” instruction, the Reserved Bits can be written as “0”, but there
will not be any effects.

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 GM25Q128A
7.1.13 GM25Q128A Status Register Memory Protection (CMP = 0)

STATUS REGISTER (1) GM25Q128A (128M-BIT) MEMORY PROTECTION (3)

PROTECTED PROTECTED PROTECTED PROTECTED

SEC TB BP2 BP1 BP0
BLOCK(S) ADDRESSES DENSITY PORTION (2)

X X 0 0 0 NONE NONE NONE NONE

0 0 0 0 1 252 thru 255 FC0000h – FFFFFFh 256KB Upper 1/64
0 0 0 1 0 248 thru 255 F80000h – FFFFFFh 512KB Upper 1/32
0 0 0 1 1 240 thru 255 F00000h – FFFFFFh 1MB Upper 1/16
0 0 1 0 0 224 thru 255 E00000h – FFFFFFh 2MB Upper 1/8
0 0 1 0 1 192 thru 255 C00000h – FFFFFFh 4MB Upper 1/4
0 0 1 1 0 128 thru 255 800000h – FFFFFFh 8MB Upper 1/2
0 1 0 0 1 0 thru 3 000000h – 03FFFFh 256KB Lower 1/64
0 1 0 1 0 0 thru 7 000000h – 07FFFFh 512KB Lower 1/32
0 1 0 1 1 0 thru 15 000000h – 0FFFFFh 1MB Lower 1/16
0 1 1 0 0 0 thru 31 000000h – 1FFFFFh 2MB Lower 1/8
0 1 1 0 1 0 thru 63 000000h – 3FFFFFh 4MB Lower 1/4
0 1 1 1 0 0 thru 127 000000h – 7FFFFFh 8MB Lower 1/2
X X 1 1 1 0 thru 255 000000h – FFFFFFh 16MB ALL
1 0 0 0 1 255 FFF000h – FFFFFFh 4KB U - 1/4096
1 0 0 1 0 255 FFE000h – FFFFFFh 8KB U - 1/2048
1 0 0 1 1 255 FFC000h – FFFFFFh 16KB U - 1/1024
1 0 1 0 X 255 FF8000h – FFFFFFh 32KB U - 1/512
1 1 0 0 1 0 000000h – 000FFFh 4KB L - 1/4096
1 1 0 1 0 0 000000h – 001FFFh 8KB L - 1/2048
1 1 0 1 1 0 000000h – 003FFFh 16KB L - 1/1024
1 1 1 0 X 0 000000h – 007FFFh 32KB L - 1/512
Notes:
1. X = don’t care
2. L = Lower; U = Upper
3. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored.

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 GM25Q128A
7.1.14 GM25Q128A Status Register Memory Protection (CMP = 1)

STATUS REGISTER (1) GM25Q128A (128M-BIT) MEMORY PROTECTION (3)

PROTECTED PROTECTED PROTECTED PROTECTED
SEC TB BP2 BP1 BP0
BLOCK(S) ADDRESSES DENSITY PORTION (2)
X X 0 0 0 0 thru 255 000000h - FFFFFFh 16MB ALL
0 0 0 0 1 0 thru 251 000000h - FBFFFFh 16,128KB Lower 63/64
0 0 0 1 0 0 thru 247 000000h – F7FFFFh 15,872KB Lower 31/32
0 0 0 1 1 0 thru 239 000000h - EFFFFFh 15MB Lower 15/16
0 0 1 0 0 0 thru 223 000000h - DFFFFFh 14MB Lower 7/8
0 0 1 0 1 0 thru 191 000000h - BFFFFFh 12MB Lower 3/4
0 0 1 1 0 0 thru 127 000000h - 7FFFFFh 8MB Lower 1/2 (4)
0 1 0 0 1 4 thru 255 040000h - FFFFFFh 16,128KB Upper 63/64
0 1 0 1 0 8 thru 255 080000h - FFFFFFh 15,872KB Upper 31/32
0 1 0 1 1 16 thru 255 100000h - FFFFFFh 15MB Upper 15/16
0 1 1 0 0 32 thru 255 200000h - FFFFFFh 14MB Upper 7/8
0 1 1 0 1 64 thru 255 400000h - FFFFFFh 12MB Upper 3/4
0 1 1 1 0 128 thru 255 800000h - FFFFFFh 8MB Upper 1/2 (4)
X X 1 1 1 NONE NONE NONE NONE
1 0 0 0 1 0 thru 255 000000h – FFEFFFh 16,380KB L - 4095/4096
1 0 0 1 0 0 thru 255 000000h – FFDFFFh 16,376KB L - 2047/2048
1 0 0 1 1 0 thru 255 000000h – FFBFFFh 16,368KB L - 1023/1024
1 0 1 0 X 0 thru 255 000000h – FF7FFFh 16,352KB L - 511/512
1 1 0 0 1 0 thru 255 001000h – FFFFFFh 16,380KB U - 4095/4096
1 1 0 1 0 0 thru 255 002000h – FFFFFFh 16,376KB U - 2047/2048
1 1 0 1 1 0 thru 255 004000h – FFFFFFh 16,368KB U -1023/1024
1 1 1 0 X 0 thru 255 008000h – FFFFFFh 16,352KB U - 511/512
Notes:
1. X = don’t care
2. L = Lower; U = Upper
3. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored.

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 GM25Q128A
8 INSTRUCTIONS
The Standard/Dual/Quad SPI instruction set of the GM25Q128A consists of 37 basic instructions that are fully
controlled through the SPI bus (see Instruction Set Table1-2). Instructions are initiated with the falling edge of Chip
Select (/CS). The first byte of data clocked into the DI input provides the instruction code. Data on the DI input is
sampled on the rising edge of clock with most significant bit (MSB) first.

Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data bytes,
dummy bytes (don’t care), and in some cases, a combination. Instructions are completed with the rising edge of
edge /CS. Clock relative timing diagrams for each instruction are included in Figures 4 through 35. All read
instructions can be completed after any clocked bit. However, all instructions that Write, Program or Erase must
complete on a byte boundary (/CS driven high after a full 8-bits have been clocked) otherwise the instruction will be
ignored. This feature further protects the device from inadvertent writes. Additionally, while the memory is being
programmed or erased, or when the Status Register is being written, all instructions except for Read Status Register
will be ignored until the program or erase cycle has completed.

8.1 Device ID and Instruction Set Tables

8.1.1 Identification
(MF7 - MF0)
Chuangfeixin Serial Flash 1Ch

Device ID (ID7 - ID0) (ID15 - ID0)

Instruction 90h 9Fh
GM25Q128A 17h 4018h

8.1.2 Instruction Set Table 1 (Standard SPI Instructions) (1)

Data Input Output Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7

Number of Clock (1-1-1) 8 8 8 8 8 8 8

Write Enable 06h

Volatile SR Write Enable 50h

Write Disable 04h

Release Power-down ABh

Manufacturer/Device ID 90h Dummy Dummy 00h (MF7-MF0) (ID7-ID0)

JEDEC ID 9Fh (MF7-MF0) (ID15-ID8) (ID7-ID0)

Read Unique ID 5Ah 00h 00h A7-A0 Dummy D7-D0 …

Read Data 03h A23-A16 A15-A8 A7-A0 (D7-D0)

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 GM25Q128A
Fast Read 0Bh A23-A16 A15-A8 A7-A0 Dummy (D7-D0)

Page Program 02h A23-A16 A15-A8 A7-A0 D7-D0 D7-D0 (3)

Sector Erase (4KB) 20h A23-A16 A15-A8 A7-A0

Block Erase (32KB) 52h A23-A16 A15-A8 A7-A0

Block Erase (64KB) D8h A23-A16 A15-A8 A7-A0

Chip Erase C7h/60h

Read Status Register-1 05h (S7-S0) (2)

Write Status Register-1(4) 01h (S7-S0) (4)

Read Status Register-2 35h (S15-S8) (2)

Write Status Register-2 31h (S15-S8)

Read Status Register-3 15h (S23-S16) (2)

Write Status Register-3 11h (S23-S16)

Read SFDP Register 5Ah 00 00 A7-A0 Dummy (D7-D0)

Erase Security Register (5) 44h A23-A16 A15-A8 A7-A0

Program Security Register (5) 42h A23-A16 A15-A8 A7-A0 D7-D0 D7-D0(3)

Read Security Register (5) 48h A23-A16 A15-A8 A7-A0 Dummy (D7-D0)

Erase / Program Suspend 75h

Erase / Program Resume 7Ah

Power-down B9h

Enable Reset 66h

Reset Device 99h

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 GM25Q128A
8.1.3 Instruction Set Table 2 (Dual/Quad SPI Instructions)
Data Input Output Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 Byte 8 Byte 9

Number of Clock (1-1-2) 8 8 8 8 4 4 4 4 4

(7)
Fast Read Dual Output 3Bh A23-A16 A15-A8 A7-A0 Dummy Dummy (D7-D0)

Number of Clock (1-2-2) 8 4 4 4 4 4 4 4 4

Fast Read Dual I/O BBh A23-A16 (6) A15-A8 (6) A7-A0 (6) Dummy (11) (D7-D0) (7)

Number of Clock (1-1-4) 8 8 8 8 2 2 2 2 2

Quad Input Page Program 32h A23-A16 A15-A8 A7-A0 (D7-D0) (9) (D7-D0) (3) …

Fast Read Quad Output 6Bh A23-A16 A15-A8 A7-A0 Dummy Dummy Dummy Dummy (D7-D0) (10)

Number of Clock (1-4-4) 8 2 (8) 2 (8) 2 (8) 2 2 2 2 2

Fast Read Quad I/O EBh A23-A16 A15-A8 A7-A0 Dummy (11) Dummy Dummy (D7-D0)

Word Read Quad I/O E7h A23-A16 A15-A8 A7-A0 Dummy (11) Dummy (D7-D0)

Set Burst with Wrap 77h Dummy Dummy Dummy W8-W0

Notes:
1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data output from the device on
either 1, 2 or 4 IO pins.
2. The Status Register contents and Device ID will repeat continuously until /CS terminates the instruction.
3. At least one byte of data input is required for Page Program, Quad Page Program and Program Security Registers, up to 256 bytes of
data input. If more than 256 bytes of data are sent to the device, the addressing will wrap to the beginning of the page and overwrite
previously sent data.
4. Write Status Register-1 (01h) can also be used to program Status Register-1&2, see section 8.2.5.
5. Security Register Address:
Security Register 1: A23-16 = 00h; A15-8 = 10h; A7-0 = byte address
Security Register 2: A23-16 = 00h; A15-8 = 20h; A7-0 = byte address
Security Register 3: A23-16 = 00h; A15-8 = 30h; A7-0 = byte address
6. Dual SPI address input format:
IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0
IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1
7. Dual SPI data output format:
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
8. Quad SPI address input format: Set Burst with Wrap input format:
IO0 = A20, A16, A12, A8 , A4 , A0, M4, M0 IO0 = x, x, x, x, x, x, W4, x
IO1 = A21, A17, A13, A9 , A5 , A1, M5, M1 IO1 = x, x, x, x, x, x, W5, x
IO2 = A22, A18, A14, A10, A6, A2, M6, M2 IO2 = x, x, x, x, x, x, W6, x
IO3 = A23, A19, A15, A11, A7, A3, M7, M3 IO3 = x, x, x, x, x, x, x , x
9. Quad SPI data input/output format:
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3, …..)
10. Fast Read Quad I/O data output format:
IO0 = (x, x, x, x, D4, D0, D4, D0)
IO1 = (x, x, x, x, D5, D1, D5, D1)
IO2 = (x, x, x, x, D6, D2, D6, D2)
IO3 = (x, x, x, x, D7, D3, D7, D3)
11. The first dummy is M7-M0 should be set to Fxh

18
 GM25Q128A
8.2 Instruction Descriptions

8.2.1 Write Enable (06h)

The Write Enable instruction (Figure 4) sets the Write Enable Latch (WEL) bit in the Status Register to a 1. The
WEL bit must be set prior to every Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase,
Write Status Register and Erase/Program Security Registers instruction. The Write Enable instruction is entered by
driving /CS low, shifting the instruction code “06h” into the Data Input (DI) pin on the rising edge of CLK, and then
driving /CS high.

Figure 4. Write Enable Instruction for SPI Mode

8.2.2 Write Enable for Volatile Status Register (50h)

The non-volatile Status Register bits described in section 7.1 can also be written to as volatile bits. This gives more
flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical
non-volatile bit write cycles or affecting the endurance of the Status Register nonvolatile bits. To write the volatile
values into the Status Register bits, the Write Enable for Volatile Status Register (50h) instruction must be issued
prior to a Write Status Register (01h) instruction. Write Enable for Volatile Status Register instruction (Figure 5) will
not set the Write Enable Latch (WEL) bit, it is only valid for the Write Status Register instruction to change the
volatile Status Register bit values.

Figure 5. Write Enable for Volatile Status Register Instruction for SPI Mode

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 GM25Q128A
8.2.3 Write Disable (04h)
The Write Disable instruction (Figure 6) resets the Write Enable Latch (WEL) bit in the Status Register to a 0. The
Write Disable instruction is entered by driving /CS low, shifting the instruction code “04h” into the DI pin and then
driving /CS high. Note that the WEL bit is automatically reset after Power-up and upon completion of the Write
Status Register, Erase/Program Security Registers, Page Program, Quad Page Program, Sector Erase, Block
Erase, Chip Erase and Reset instructions.

Figure 6. Write Disable Instruction for SPI Mode

8.2.4 Read Status Register-1 (05h), Status Register-2 (35h) & Status Register-3 (15h)
The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is entered by
driving /CS low and shifting the instruction code “05h” for Status Register-1, “35h” for Status Register-2 or “15h” for
Status Register-3 into the DI pin on the rising edge of CLK. The status register bits are then shifted out on the DO
pin at the falling edge of CLK with most significant bit (MSB) first as shown in Figure 7. Refer to section 7.1 for
Status Register descriptions.

The Read Status Register instruction may be used at any time, even while a Program, Erase or Write Status
Register cycle is in progress. This allows the BUSY status bit to be checked to determine when the cycle is complete
and if the device can accept another instruction. The Status Register can be read continuously, as shown in Figure
8. The instruction is completed by driving /CS high.

Figure 7 Read Status Register -1/2/3 Instruction (SPI Mode)

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 GM25Q128A
8.2.5 Write Status Register-1 (01h), Status Register-2 (31h) & Status Register-3 (11h)
The Write Status Register instruction allows the Status Registers to be written. The writable Status Register bits
include: SRP0, SEC, TB, BP[2:0] in Status Register-1; CMP, LB[3:1], QE, SRP1 in Status Register-2; DRV1, DRV0
in Status Register-3. All other Status Register bit locations are read only and will not be affected by the Write Status
Register instruction. LB[3:1] are non-volatile OTP bits, once it is set to 1, it cannot be cleared to 0.

To write non-volatile Status Register bits, a standard Write Enable (06h) instruction must previously have been
executed for the device to accept the Write Status Register instruction (Status Register bit WEL must equal 1).
Once write enabled, the instruction is entered by driving /CS low, sending the instruction code “01h/31h/11h”, and
then writing the status register data byte as illustrated in Figure 8.

To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) instruction must have been
executed prior to the Write Status Register instruction (Status Register bit WEL remains 0). However, SRP0 and
LB[3:1] cannot be changed from “1” to “0” because of the OTP protection for these bits. Upon power off or the
execution of a Software Reset, the volatile Status Register bit values will be lost, and the non-volatile Status Register
bit values will be restored.

During non-volatile Status Register write operation (06h combined with 01h/31h/11h), after /CS is driven high, the
self-timed Write Status Register cycle will commence for a time duration of tW (See AC Characteristics). While the
Write Status Register cycle is in progress, the Read Status Register instruction may still be accessed to check the
status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register cycle and a 0 when the cycle is finished
and ready to accept other instructions again. After the Write Status Register cycle has finished, the Write Enable
Latch (WEL) bit in the Status Register will be cleared to 0.

During volatile Status Register write operation (50h combined with 01h/31h/11h), after /CS is driven high, the Status
Register bits will be refreshed to the new values within the time period of tSHSL2 (See AC Characteristics). BUSY
bit will remain 0 during the Status Register bit refresh period.

Refer to section 7.1 for Status Register descriptions.

Figure 8. Write Status Register-1/2/3 Instruction

Notes:
1. After any one of the three Status Registers has been written, software reset instruction (66h and 99h) or power down is needed to reload
the non-volatile bits of three Status Register.

21
 GM25Q128A
8.2.6 Read Data (03h)
The Read Data instruction allows one or more data bytes to be sequentially read from the memory. The instruction
is initiated by driving the /CS pin low and then shifting the instruction code “03h” followed by a 24-bit address (A23-
A0) into the DI pin. The code and address bits are latched on the rising edge of the CLK pin. After the address is
received, the data byte of the addressed memory location will be shifted out on the DO pin at the falling edge of
CLK with most significant bit (MSB) first. The address is automatically incremented to the next higher address after
each byte of data is shifted out allowing for a continuous stream of data. This means that the entire memory can be
accessed with a single instruction as long as the clock continues. The instruction is completed by driving /CS high.

The Read Data instruction sequence is shown in Figure 10. If a Read Data instruction is issued while an Erase,
Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any effects on the current
cycle. The Read Data instruction allows clock rates from D.C. to a maximum of fR (see AC Electrical Characteristics).

The Read Data (03h) instruction is only supported in Standard SPI mode.

Figure 10. Read Data Instruction

22
 GM25Q128A
8.2.7 Fast Read (0Bh)
The Fast Read instruction is similar to the Read Data instruction except that it can operate at the highest possible
frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight “dummy” clocks after the
24-bit address as shown in Figure 11. The dummy clocks allow the devices internal circuits additional time for setting
up the initial address. During the dummy clocks the data value on the DO pin is a “don’t care”.

Figure 11. Fast Read Instruction

23
 GM25Q128A
8.2.8 Fast Read Dual Output (3Bh)
The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except that data
is output on two pins; IO0 and IO1. This allows data to be transferred at twice the rate of standard SPI devices. The
Fast Read Dual Output instruction is ideal for quickly downloading code from Flash to RAM upon power-up or for
applications that cache code-segments to RAM for execution.

Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the highest possible
frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight “dummy” clocks after the
24-bit address as shown in Figure 12. The dummy clocks allow the devices internal circuits additional time for setting
up the initial address. The input data during the dummy clocks is “don’t care”. However, the IO0 pin should be high-
impedance prior to the falling edge of the first data out clock.

Figure 12. Fast Read Dual Output Instruction (SPI Mode only)

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 GM25Q128A
8.2.9 Fast Read Quad Output (6Bh)
The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh) instruction except that
data is output on four pins, IO0, IO1, IO2, and IO3. The Quad Enable (QE) bit in Status Register-2 must be set to 1
before the device will accept the Fast Read Quad Output Instruction. The Fast Read Quad Output Instruction allows
data to be transferred at four times the rate of standard SPI devices.

The Fast Read Quad Output instruction can operate at the highest possible frequency of FR (see AC Electrical
Characteristics). This is accomplished by adding eight “dummy” clocks after the 24-bit address as shown in Figure
13. The dummy clocks allow the devices internal circuits additional time for setting up the initial address. The input
data during the dummy clocks is “don’t care”. However, the IO pins should be high-impedance prior to the falling
edge of the first data out clock.

Figure 13. Fast Read Quad Output Instruction (SPI Mode only)

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 GM25Q128A
8.2.10 Fast Read Dual I/O (BBh) (1)
The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO pins, IO0
and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input the Address bits
(A23-0) two bits per clock. This reduced instruction overhead may allow for code execution (XIP) directly from the
Dual SPI in some applications.

Fast Read Dual I/O with “Continuous Read Mode”

The Fast Read Dual I/O instruction can further reduce instruction overhead through setting the “Continuous Read
Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 14a. The upper nibble of the (M7-4)
controls the length of the next Fast Read Dual I/O instruction through the inclusion or exclusion of the first byte
instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should be high-
impedance prior to the falling edge of the first data out clock.

If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Dual I/O instruction (after /CS is raised
and then lowered) does not require the BBh instruction code, as shown in Figure 14b. This reduces the instruction
sequence by eight clocks and allows the Read address to be immediately entered after /CS is asserted low. If the
“Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after /CS is raised and then lowered)
requires the first byte instruction code, thus returning to normal operation. It is recommended to input FFFFh on
IO0 for the next instruction (16 clocks), to ensure M4 = 1 and return the device to normal operation.

Figure 14a. Fast Read Dual I/O Instruction (Initial instruction or previous M5-4 ≠10, SPI Mode only)

26
 GM25Q128A

Figure 14b. Fast Read Dual I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode only)

Notes:
1. During Fast Read Dual I/O instruction (BB), the A1 and A0 of input address (A23-A0) cannot be set to '1' simultaneously.

27
 GM25Q128A
8.2.11 Fast Read Quad I/O (EBh)
The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except that address
and data bits are input and output through four pins IO0, IO1, IO2 and IO3 and four Dummy clocks are required in
SPI mode prior to the data output. The Quad I/O dramatically reduces instruction overhead allowing faster random
access for code execution (XIP) directly from the Quad SPI. The Quad Enable bit (QE) of Status Register-2 must
be set to enable the Fast Read Quad I/O Instruction.

Fast Read Quad I/O with “Continuous Read Mode

The Fast Read Quad I/O instruction can further reduce instruction overhead through setting the “Continuous Read
Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 15a. The upper nibble of the (M7-4)
controls the length of the next Fast Read Quad I/O instruction through the inclusion or exclusion of the first byte
instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should be high-
impedance prior to the falling edge of the first data out clock.

If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS is raised
and then lowered) does not require the EBh instruction code, as shown in Figure 15b. This reduces the instruction
sequence by eight clocks and allows the Read address to be immediately entered after /CS is asserted low. If the
“Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after /CS is raised and then lowered)
requires the first byte instruction code, thus returning to normal operation. It is recommended to input FFh on IO0
for the next instruction (8 clocks), to ensure M4 = 1 and return the device to normal operation.

Figure 15a. Fast Read Quad I/O Instruction (Initial instruction or previous M5-4≠10, SPI Mode)

28
 GM25Q128A

Figure 15b. Fast Read Quad I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode)

Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Fast Read Quad I/O instruction can also be used to access a specific portion within a page by issuing a “Set
Burst with Wrap” (77h) command prior to EBh. The “Set Burst with Wrap” (77h) command can either enable or
disable the “Wrap Around” feature for the following EBh commands. When “Wrap Around” is enabled, the data being
accessed can be limited to either an 8, 16, 32 or 64-byte section of a 256-byte page. The output data starts at the
initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64-byte section, the
output will wrap around to the beginning boundary automatically until /CS is pulled high to terminate the command.

The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the
cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands.

The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to enable or
disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around section within a
page. Refer to section 8.2.13 for detail descriptions.

29
 GM25Q128A
8.2.12 Word Read Quad I/O (E7h)
The Word Read Quad I/O (E7h) instruction is similar to the Fast Read Quad I/O (EBh) instruction except that the
lowest Address bit (A0) must equal 0 and only two Dummy clocks are required prior to the data output. The Quad
I/O dramatically reduces instruction overhead allowing faster random access for code execution (XIP) directly from
the Quad SPI. The Quad Enable bit (QE) of Status Register-2 must be set to enable the Word Read Quad I/O
Instruction.

Word Read Quad I/O with “Continuous Read Mode”

The Word Read Quad I/O instruction can further reduce instruction overhead through setting the “Continuous Read
Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 17a. The upper nibble of the (M7-4)
controls the length of the next Fast Read Quad I/O instruction through the inclusion or exclusion of the first byte
instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should be high-
impedance prior to the falling edge of the first data out clock.

If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS is raised
and then lowered) does not require the E7h instruction code, as shown in Figure 17b. This reduces the instruction
sequence by eight clocks and allows the Read address to be immediately entered after /CS is asserted low. If the
“Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after /CS is raised and then lowered)
requires the first byte instruction code, thus returning to normal operation. It is recommended to input FFh on IO0
for the next instruction (8 clocks), to ensure M4 = 1 and return the device to normal operation.

Figure 17a. Word Read Quad I/O Instruction (Initial instruction or previous M5-4 ≠ 10, SPI Mode only)

30
 GM25Q128A

Figure 17b. Word Read Quad I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode only)

Word Read Quad I/O with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Word Read Quad I/O instruction can also be used to access a specific portion within a page by issuing a “Set
Burst with Wrap” (77h) command prior to E7h. The “Set Burst with Wrap” (77h) command can either enable or
disable the “Wrap Around” feature for the following E7h commands. When “Wrap Around” is enabled, the data being
accessed can be limited to either an 8, 16, 32 or 64- byte section of a 256-byte page. The output data starts at the
initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64-byte section, the
output will wrap around to the beginning boundary automatically until /CS is pulled high to terminate the command.

The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the
cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands.

The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to enable or
disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around section within a
page. See 8.2.13 for detail descriptions.

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 GM25Q128A
8.2.13 Set Burst with Wrap (77h)
In Standard SPI mode, the Set Burst with Wrap (77h) instruction is used in conjunction with “Fast Read Quad I/O”
instruction to access a fixed length of 8/16/32/64-byte section within a 256-byte page. Certain applications can
benefit from this feature and improve the overall system code execution performance.

Similar to a Quad I/O instruction, the Set Burst with Wrap instruction is initiated by driving the /CS pin low and then
shifting the instruction code “77h” followed by 24 dummy bits and 8 “Wrap Bits”, W7-0. The instruction sequence is
shown in Figure 18. Wrap bit W7 and the lower nibble W3-0 are not used.

W4 = 0 W4 =1 (DEFAULT)
W6, W5
Wrap Around Wrap Length Wrap Around Wrap Length
0 0 Yes 8-byte No N/A
0 1 Yes 16-byte No N/A
1 0 Yes 32-byte No N/A
1 1 Yes 64-byte No N/A

Once W6-4 is set by a Set Burst with Wrap instruction, all the following “Fast Read Quad I/O” instruction will use
the W6-4 setting to access the 8/16/32/64-byte section within any page. To exit the “Wrap Around” function and
return to normal read operation, another Set Burst with Wrap instruction should be issued to set W4 = 1. The default
value of W4 upon power on or after a software reset is 1.

Figure 18. Set Burst with Wrap Instruction

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 GM25Q128A
8.2.14 Page Program (02h)
The Page Program instruction allows from one byte to 256 bytes (a page) of data to be programmed at previously
erased (FFh) memory locations. A Write Enable instruction must be executed before the device will accept the Page
Program Instruction (Status Register bit WEL= 1). The instruction is initiated by driving the /CS pin low then shifting
the instruction code “02h” followed by a 24-bit address (A23-A0) and at least one data byte, into the DI pin. The /CS
pin must be held low for the entire length of the instruction while data is being sent to the device. The Page Program
instruction sequence is shown in Figure 19.

If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits) should
be set to 0. If the last address byte is not zero, and the number of clocks exceeds the remaining page length, the
addressing will wrap to the beginning of the page. In some cases, less than 256 bytes (a partial page) can be
programmed without having any effect on other bytes within the same page. One condition to perform a partial page
program is that the number of clocks cannot exceed the remaining page length. If more than 256 bytes are sent to
the device the addressing will wrap to the beginning of the page and overwrite previously sent data.

As with the write and erase instructions, the /CS pin must be driven high after the eighth bit of the last byte has
been latched. If this is not done the Page Program instruction will not be executed. After /CS is driven high, the self-
timed Page Program instruction will commence for a time duration of tpp (See AC Characteristics). While the Page
Program cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of
the BUSY bit. The BUSY bit is a 1 during the Page Program cycle and becomes a 0 when the cycle is finished and
the device is ready to accept other instructions again. After the Page Program cycle has finished the Write Enable
Latch (WEL) bit in the Status Register is cleared to 0. The Page Program instruction will not be executed if the
addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits or the Individual
Block/Sector Locks.

Figure 19. Page Program Instruction

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 GM25Q128A
8.2.15 Quad Input Page Program (32h)
The Quad Page Program instruction allows up to 256 bytes of data to be programmed at previously erased (FFh)
memory locations using four pins: IO0, IO1, IO2, and IO3. The Quad Page Program can improve performance for
PROM Programmer and applications that have slow clock speeds <5MHz. Systems with faster clock speed will not
realize much benefit for the Quad Page Program instruction since the inherent page program time is much greater
than the time it take to clock-in the data.

To use Quad Page Program the Quad Enable (QE) bit in Status Register-2 must be set to 1. A Write Enable
instruction must be executed before the device will accept the Quad Page Program instruction (Status Register-1,
WEL=1). The instruction is initiated by driving the /CS pin low then shifting the instruction code “32h” followed by a
24-bit address (A23-A0) and at least one data byte, into the IO pins. The /CS pin must be held low for the entire
length of the instruction while data is being sent to the device. All other functions of Quad Page Program are identical
to standard Page Program. The Quad Page Program instruction sequence is shown in Figure 20.

Figure 20. Quad Input Page Program Instruction

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 GM25Q128A
8.2.16 Sector Erase (20h)
The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state of all 1s (FFh).
A Write Enable instruction must be executed before the device will accept the Sector Erase nstruction (Status
Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction
code “20h” followed a 24-bit sector address (A23-A0). The Sector Erase instruction sequence is shown in Figure
21.

The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Sector
Erase instruction will not be executed. After /CS is driven high, the self-timed Sector Erase instruction will commence
for a time duration of tSE (See AC Characteristics). While the Sector Erase cycle is in progress, the Read Status
Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the
Sector Erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions
again. After the Sector Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared
to 0. The Sector Erase instruction will not be executed if the addressed page is protected by the Block Protect (CMP,
SEC, TB, BP2, BP1, and BP0) bits or the Individual Block/Sector Locks.

Figure 21. Sector Erase Instruction

35
 GM25Q128A
8.2.17 32KB Block Erase (52h)
The Block Erase instruction sets all memory within a specified block (32K-bytes) to the erased state of all 1s (FFh).
A Write Enable instruction must be executed before the device will accept the Block Erase Instruction (Status
Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction
code “52h” followed a 24-bit block address (A23-A0). The Block Erase instruction sequence is shown in Figure 22.

The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Block
Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase instruction will commence
for a time duration of tBE1 (See AC Characteristics). While the Block Erase cycle is in progress, the Read Status
Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the
Block Erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions
again. After the Block Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared
to 0. The Block Erase instruction will not be executed if the addressed page is protected by the Block Protect (CMP,
SEC, TB, BP2, BP1, and BP0) its or the Individual Block/Sector Locks.

Figure 22. 32KB Block Erase Instruction

36
 GM25Q128A
8.2.18 64KB Block Erase (D8h)
The Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state of all 1s (FFh).
A Write Enable instruction must be executed before the device will accept the Block Erase Instruction (Status
Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction
code “D8h” followed a 24-bit block address (A23-A0). The Block Erase instruction sequence is shown in Figure 23.

The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Block
Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase instruction will commence
for a time duration of tBE (See AC Characteristics). While the Block Erase cycle is in progress, the Read Status
Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the
Block Erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions
again. After the Block Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared
to 0. The Block Erase instruction will not be executed if the addressed page is protected by the Block Protect (CMP,
SEC, TB, BP2, BP1, and BP0) its or the Individual Block/Sector Locks.

Figure 23. 64KB Block Erase Instruction

37
 GM25Q128A
8.2.19 Chip Erase (C7h / 60h)
The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write Enable
instruction must be executed before the device will accept the Chip Erase Instruction (Status Register bit WEL must
equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “C7h” or “60h”. The
Chip Erase instruction sequence is shown in Figure 24.

The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase instruction
will not be executed. After /CS is driven high, the self-timed Chip Erase instruction will commence for a time duration
of tCE (See AC Characteristics). While the Chip Erase cycle is in progress, the Read Status Register instruction
may still be accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Chip Erase cycle and
becomes a 0 when finished and the device is ready to accept other instructions again. After the Chip Erase cycle
has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Chip Erase instruction will
not be executed if any memory region is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits
or the Individual Block/Sector Locks.

Figure 24. Chip Erase Instruction Sequence Diagram

38
 GM25Q128A
8.2.20 Erase / Program Suspend (75h)
The Erase/Program Suspend instruction “75h”, allows the system to interrupt a Sector or Block Erase operation or
a Page Program operation and then read from or program/erase data to, any other sectors or blocks. The
Erase/Program Suspend instruction sequence is shown in Figure 25.

The Write Status Register instruction (01h) and Erase instructions (20h, 52h, D8h, C7h, 60h, 44h) are not allowed
during Erase Suspend. Erase Suspend is valid only during the Sector or Block erase operation. If written during the
Chip Erase operation, the Erase Suspend instruction is ignored. The Write Status Register instruction (01h) and
Program instructions (02h, 32h, 42h) are not allowed during Program Suspend. Program Suspend is valid only
during the Page Program or Quad Page Program operation.

The Erase/Program Suspend instruction “75h” will be accepted by the device only if the SUS bit in the Status
Register equals to 0 and the BUSY bit equals to 1 while a Sector or Block Erase or a Page Program operation is
on-going. If the SUS bit equals to 1 or the BUSY bit equals to 0, the Suspend instruction will be ignored by the
device. A maximum of time of “tSUS” (See AC Characteristics) is required to suspend the erase or program operation.
The BUSY bit in the Status Register will be cleared from 1 to 0 within “tSUS” and the SUS bit in the Status Register
will be set from 0 to 1 immediately after Erase/Program Suspend. For a previously resumed Erase/Program
operation, it is also required that the Suspend instruction “75h” is not issued earlier than a minimum of time of “tSUS”
following the preceding Resume instruction “7Ah”.

Unexpected power off during the Erase/Program suspend state will reset the device and release the suspend state.
SUS bit in the Status Register will also reset to 0. The data within the page, sector or block that was being suspended
may become corrupted. It is recommended for the user to implement system design techniques against the
accidental power interruption and preserve data integrity during erase/program suspend state.

Figure 25. Erase/Program Suspend Instruction

39
 GM25Q128A
8.2.21 Erase / Program Resume (7Ah)
The Erase/Program Resume instruction “7Ah” must be written to resume the Sector or Block Erase operation or the
Page Program operation after an Erase/Program Suspend. The Resume instruction “7Ah” will be accepted by the
device only if the SUS bit in the Status Register equals to 1 and the BUSY bit equals to 0. After issued the SUS bit
will be cleared from 1 to 0 immediately, the BUSY bit will be set from 0 to 1 within 200ns and the Sector or Block
will complete the erase operation or the page will complete the program operation. If the SUS bit equals to 0 or the
BUSY bit equals to 1, the Resume instruction “7Ah” will be ignored by the device. The Erase/Program Resume
instruction sequence is shown in Figure 26.

Resume instruction is ignored if the previous Erase/Program Suspend operation was interrupted by unexpected
power off. It is also required that a subsequent Erase/Program Suspend instruction not to be issued within a
minimum of time of “tSUS” following a previous Resume instruction.

Figure 26. Erase/Program Resume Instruction

40
 GM25Q128A
8.2.22 Power-down (B9h)
Although the standby current during normal operation is relatively low, standby current can be further reduced with
the Power-down instruction. The lower power consumption makes the Power-down instruction especially useful for
battery powered applications (See ICC1 and ICC2 in AC Characteristics). The instruction is initiated by driving the
/CS pin low and shifting the instruction code “B9h” as shown in Figure 27.

The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Power-down instruction
will not be executed. After /CS is driven high, the power-down state will entered within the time duration of tDP (See
AC Characteristics). While in the power-down state only the Release Power-down / Device ID (ABh) instruction,
which restores the device to normal operation, will be recognized. All other instructions are ignored. This includes
the Read Status Register instruction, which is always available during normal operation. Ignoring all but one
instruction makes the Power Down state a useful condition for securing maximum write protection. The device
always powers-up in the normal operation with the standby current of ICC1.

Figure 27. Deep Power-down Instruction

41
 GM25Q128A
8.2.23 Release Power-down (ABh)
The Release from Power-down instruction is a multi-purpose instruction. It can be used to release the device from
the power-down state.

To release the device from the power-down state, the instruction is issued by driving the /CS pin low, shifting the
instruction code “ABh” and driving /CS high as shown in Figure 28. Release from power-down will take the time
duration of tRES1 (See AC Characteristics) before the device will resume normal operation and other instructions
are accepted. The /CS pin must remain high during the tRES1 time duration.

Figure 28. Release Power-down Instruction

42
 GM25Q128A
8.2.24 Read Manufacturer / Device ID (90h)
The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down / Device ID
instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID.

The Read Manufacturer/Device ID instruction is very similar to the Release from Power-down / Device ID instruction.
The instruction is initiated by driving the /CS pin low and shifting the instruction code “90h” followed by a 24-bit
address (A23-A0) of 000000h. After which, the Manufacturer ID for Chuangfeixin and the Device ID are shifted out
on the falling edge of CLK with most significant bit (MSB) first as show in Figure 29. The Device ID values for the
GM25Q128A are listed in Manufacturer and Device Identification table. The instruction is completed by driving /CS
high.

Figure 29. Read Manufacturer / Device ID Instruction

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 GM25Q128A
8.2.25 Read JEDEC ID (9Fh)
For compatibility reasons, the GM25Q128A provides several instructions to electronically determine the identity of
the device. The Read JEDEC ID instruction is compatible with the JEDEC standard for SPI compatible serial
memories that was adopted in 2003. The instruction is initiated by driving the /CS pin low and shifting the instruction
code “9Fh”. The JEDEC assigned Manufacturer ID byte for Chuangfeixin two Device ID bytes, Memory Type (ID15-
ID8) and Capacity (ID7-ID0) are then shifted out on the falling edge of CLK with most significant bit (MSB) first as
shown in Figure 30. For memory type and capacity values refer to Manufacturer and Device Identification table.

Figure 30. Read JEDEC ID Instruction

44
 GM25Q128A

8.2.26 Read SFDP Register (5Ah)

The GM25Q128A features a 256-Byte Serial Flash Discoverable Parameter (SFDP) register that contains
information about device configurations, available instructions and other features. The SFDP parameters are stored
in one or more Parameter Identification (PID) tables. Currently only one PID table is specified, but more may be
added in the future. The Read SFDP Register instruction is compatible with the SFDP standard initially established
in 2010 for PC and other applications, as well as the JEDEC standard JESD216-serials that is published in 2011.
Most Chuangfeixin SPI Flash Memories support the SFDP feature as specified in the applicable datasheet.

The Read SFDP instruction is initiated by driving the /CS pin low and shifting the instruction code “5Ah” followed by
a 24-bit address (A23-A0) (1) into the DI pin. Eight “dummy” clocks are also required before the SFDP register
contents are shifted out on the falling edge of the 40th CLK with most significant bit (MSB) first as shown in Figure
31. For SFDP register values and descriptions, please refer to the Chuangfeixin SFDP Definition Table.

Notes:
1. A23-A8 = 0; A7-A0 are used to define the starting byte address for the 256-Byte SFDP Register.

Figure 31. Read SFDP Register Instruction Sequence Diagram

45
 GM25Q128A
Table 8.2.26a. SFDP Headers Definition Table
SFDP
SFDP Byte
DWORD Data Description
Address
Name
"S" ASCII. This is the entry point for Read SFDP (5Ah) command i.e. location zero within
00h 53h
53h SFDP space
SFDP
01h Header 1st 46h "F" ASCII
02h DWORD 44h "D" ASCII
03h 50h "P" ASCII
04h 00h SFDP Minor Revision
SFDP
05h 01h SFDP Major Revision
Header 2nd
06h 01h Number of Parameters Headers (zero based, 01h = 2 parameters)
DWORD
07h FFh Unused
08h 00h Parameter ID LSB (00h = JEDEC SFDP Basic SPI Flash Parameter)
09h Parameter 08h Parameter Minor Revision(08h=JESD216D)
Header 0
Parameter Major Revision (01h = The original major revision - all SFDP software is
0Ah 1st 01h
compatible with this major revision.
DWORD
0Bh 09h Parameter Table Length (in double words = Dwords = 4-byte units) 09h = 9 Dwords
Parameter Table Pointer Byte 0 (Dwords = 4-byte aligned)
0Ch 80h
Parameter JEDEC Basic SPI Flash parameter byte offset = 80h
Header 0
0Dh 00h Parameter Table Pointer Byte 1
2nd
0Eh DWORD 00h Parameter Table Pointer Byte 2
0Fh FFh Parameter ID MSB (FFh = JEDEC defined Parameter)
10h 1Ch Parameter ID LSB (CFX Vendor Specific ID parameter) 1C
Parameter
11h Header 1 00h Parameter Minor Revision
12h 1st 01h Parameter Major Revision
DWORD
13h 02h Parameter Table Length (in double words = Dwords = 4-byte units) 02h = 2 Dwords
14h F8h Parameter Table Pointer Byte 0 (Dwords = 4-byte aligned)
Parameter
15h Header 1 00h Parameter Table Pointer Byte 1
16h 2nd 00h Parameter Table Pointer Byte 2
DWORD
17h 0Ch Parameter ID MSB (0Ch = JEDEC JEP106B Bank Number 12)

46
 GM25Q128A
Table 8.2.26b. JEDEC Basic Flash Parameter Definition Table
SFDP
SFDP Byte
DWORD Data Description
Address
Name

Start of SFDP JEDEC parameter

Bits 7:5 = unused = 111b
Bits 4:3 = 05h is volatile status register write instruction and status register is default
80h E5h
non-volatile= 00b
Bit 2 = Program Buffer > 64Bytes = 1
Bits 1:0 = Uniform 4KB erase is supported throughout the device = 01b

81h JEDEC 20h Bits 15:8 = Uniform 4KB erase instruction = 20h
Basic Flash
Parameter Bit 23 = Unused = 1b
Dword-1 Bit 22 = Supports QOR (1-1-4) Read, Yes = 1b
Bit 21 = Supports QIO (1-4-4) Read, Yes =1b
82h F1h Bit 20 = Supports DIO (1-2-2) Read, Yes = 1b
Bit 19 = Supports DDR, Yes = 1b, No = 0b
Bits 18:17 = Number of Address Bytes, 3 or 4 = 01b
Bit 16 = Supports Fast Read SIO and DIO Yes = 1b

83h FFh Bits 31:24 = Unused = FFh

84h FFh
JEDEC
85h Basic Flash FFh Density in bits, zero based,
86h Parameter FFh 128Mb = 07FFFFFFh;256Mb = 0FFFFFFFh;512Mb = 1FFFFFFFh
Dword-2
87h 07h
Bits 7:5 = number of QIO Mode cycles = 010b
88h 44h
Bits 4:0 = number of Fast Read QIO Dummy cycles = 00100b for default latency code
JEDEC
89h Basic Flash EBh Fast Read QIO instruction code
Parameter Bits 23:21 = number of Quad Out Mode cycles = 000b
8Ah Dword-3 08h
Bits 20:16 = number of Quad Out Dummy cycles = 01000b for default latency code
8Bh 6Bh Quad Out instruction code
Bits 7:5 = number of Dual Out Mode cycles = 000b
8Ch 08h
Bits 4:0 = number of Dual Out Dummy cycles = 01000b for default latency code
JEDEC
8Dh Basic Flash 3Bh Dual Out instruction code
Parameter Bits 23:21 = number of Dual I/O Mode cycles = 010b
8Eh Dword-4 40h
Bits 20:16 = number of Dual I/O Dummy cycles = 00000b for not support
8Fh BBh Dual I/O instruction code

Bits 7:5 RFU (Reserved for Future Use) = 111b

Bit 4 = QPI (4-4-4) not supported = 0b
90h EEh
JEDEC Bits 3:1 RFU = 111b
Basic Flash Bit 0 = Dual All (2-2-2) not supported = 0b
Parameter
91h Dword-5 FFh Bits 15:8 = RFU = FFh
92h FFh Bits 23:16 = RFU = FFh
93h FFh Bits 31:24 = RFU = FFh

47
 GM25Q128A
Continued – next page JEDEC Basic Flash Parameter Definition Table (cont’d)
94h FFh Bits 7:0 = RFU = FFh
95h JEDEC FFh Bits 15:8 = RFU = FFh
Basic Flash
Bits 23:21 = number of Dual All Mode cycles not supported = 000b
96h Parameter 00h
Bits 20:16 = number of Dual All Dummy cycles not supported = 00000b
Dword-6
97h FFh Bits 23:16 = RFU = FFh
98h FFh Bits 7:0 = RFU = FFh
99h JEDEC FFh Bits 15:8 = RFU = FFh
Basic Flash Bits 23:21 = number of QPI Mode cycles not supported = 000b
9Ah Parameter 00h Bits 20:16 = number of QPI Dummy cycles not supported = 00000b for default latency
Dword-7 code

9Bh FFh QPI Fast Read instruction code not supported

9Ch 0Ch Sector type 1 size 2^N Bytes = 4KB = 0Ch (for Uniform 4KB)
JEDEC
9Dh Basic Flash 20h Sector type 1 instruction
9Eh Parameter 0Fh Sector type 2 size 2^N Bytes = 32KB = 0Fh (for Uniform 32KB)
Dword-8
9Fh 52h Sector type 2 instruction
A0h 10h Sector type 3 size 2^N Bytes = 64KB = 10h (for Uniform 64KB)
JEDEC
A1h Basic Flash D8h Sector type 3 instruction
A2h Parameter 00h Sector type 4 size 2^N Bytes = not supported = 00h
Dword-9
A3h FFh Sector type 4 instruction = not supported = FFh

Table 8.2.26c. Vendor specific Definition Table

SFDP
SFDP Byte
DWORD Data Description
Address
Name
F8h 01h
Unique Id
F9h XXh
Parameter
FAh XXh
Dword-1
FBh XXh
Unique Id
FCh XXh
Unique Id
FDh XXh
Parameter
FEh XXh
Dword-2
FFh F6h

48
 GM25Q128A
8.2.27 Erase Security Registers (44h)
The GM25Q128A offers three 256-byte Security Registers which can be erased and programmed individually.
These registers may be used by the system manufacturers to store security and other important information
separately from the main memory array.

The Erase Security Register instruction is similar to the Sector Erase instruction. A Write Enable instruction must
be executed before the device will accept the Erase Security Register Instruction (Status Register bit WEL must
equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “44h” followed by a
24-bit address (A23-A0) to erase one of the three security registers.

ADDRESS A23-16 A15-12 A11-8 A7-0

Security Register #1 00h 0100 0000 Don’t Care
Security Register #2 00h 1000 0000 Don’t Care
Security Register #3 00h 1100 0000 Don’t Care

The Erase Security Register instruction sequence is shown in Figure 32. The /CS pin must be driven high after the
eighth bit of the last byte has been latched. If this is not done the instruction will not be executed. After /CS is driven
high, the self-timed Erase Security Register operation will commence for a time duration of tSE (See AC
Characteristics). While the Erase Security Register cycle is in progress, the Read Status Register instruction may
still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the erase cycle and becomes
a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Erase Security
Register cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Security
Register Lock Bits (LB3-1) in the Status Register-2 can be used to OTP protect the security registers. Once a lock
bit is set to 1, the corresponding security register will be permanently locked, Erase Security Register instruction to
that register will be ignored (Refer to section 7.1.9 for detail descriptions).

Figure 32. Erase Security Registers Instruction

49
 GM25Q128A
8.2.28 Program Security Registers (42h)
The Program Security Register instruction is similar to the Page Program instruction. It allows from one byte to 256
bytes of security register data to be programmed at previously erased (FFh) memory locations. A Write Enable
instruction must be executed before the device will accept the Program Security Register Instruction (Status
Register bit WEL= 1). The instruction is initiated by driving the /CS pin low then shifting the instruction code “42h”
followed by a 24-bit address (A23-A0) and at least one data byte, into the DI pin. The /CS pin must be held low for
the entire length of the instruction while data is being sent to the device.

ADDRESS A23-16 A15-12 A11-8 A7-0

Security Register #1 00h 0100 0000 Byte Address
Security Register #2 00h 1000 0000 Byte Address
Security Register #3 00h 1100 0000 Byte Address

The Program Security Register instruction sequence is shown in Figure 33. The Security Register Lock Bits (LB3-
1) in the Status Register-2 can be used to OTP protect the security registers. Once a lock bit is set to 1, the
corresponding security register will be permanently locked, Program Security Register instruction to that register
will be ignored (See 7.1.9 for detail descriptions).

Figure 33. Program Security Registers Instruction

50
 GM25Q128A
8.2.29 Read Security Registers (48h)
The Read Security Register instruction is similar to the Fast Read instruction and allows one or more data bytes to
be sequentially read from one of the four security registers. The instruction is initiated by driving the /CS pin low
and then shifting the instruction code “48h” followed by a 24-bit address (A23-A0) and eight “dummy” clocks into
the DI pin. The code and address bits are latched on the rising edge of the CLK pin. After the address is received,
the data byte of the addressed memory location will be shifted out on the DO pin at the falling edge of CLK with
most significant bit (MSB) first. The byte address is automatically incremented to the next byte address after each
byte of data is shifted out. Once the byte address reaches the last byte of the register (byte address FFh), it will
reset to address 00h, the first byte of the register, and continue to increment. The instruction is completed by driving
/CS high. The Read Security Register instruction sequence is shown in Figure 34. If a Read Security Register
instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and
will not have any effects on the current cycle. The Read Security Register instruction allows clock rates from D.C.
to a maximum of FR (see AC Electrical Characteristics)

ADDRESS A23-16 A15-12 A11-8 A7-0

Security Register #1 00h 0100 0000 Byte Address
Security Register #2 00h 1000 0000 Byte Address
Security Register #3 00h 1100 0000 Byte Address

Figure 34. Read Security Registers Instruction

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 GM25Q128A
8.2.30 Enable Reset (66h) and Reset Device (99h)
Because of the small package and the limitation on the number of pins, the GM25Q128A provide a software Reset
instruction instead of a dedicated RESET pin. Once the Reset instruction is accepted, any on-going internal
operations will be terminated and the device will return to its default power-on state and lose all the current volatile
settings, such as Volatile Status Register bits, Write Enable Latch (WEL) status, Program/Erase Suspend status,
Read parameter setting (P7-P0), and Wrap Bit setting (W6-W4).

“Enable Reset (66h)” and “Reset (99h)” instructions can be issued in SPI. To avoid accidental reset, both instructions
must be issued in sequence. Any other commands other than “Reset (99h)” after the “Enable Reset (66h)” command
will disable the “Reset Enable” state. A new sequence of “Enable Reset (66h)” and “Reset (99h)” is needed to reset
the device. Once the Reset command is accepted by the device, the device will take approximately tRST=30us to
reset. During this period, no command will be accepted.

Data corruption may happen if there is an on-going or suspended internal Erase or Program operation when Reset
command sequence is accepted by the device. It is recommended to check the BUSY bit and the SUS bit in Status
Register before issuing the Reset command sequence.

Figure 35. Enable Reset and Reset Instruction Sequence

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 GM25Q128A
9 ELECTRICAL CHARACTERISTICS
9.1 Absolute Maximum Ratings (1)
PARAMETERS SYMBOL CONDITIONS RANGE UNIT
Supply Voltage VCC –0.6 to 4.6 V
Voltage Applied to Any Pin VIO Relative to Ground –0.6 to VCC+0.4 V
<20nS Transient
Transient Voltage on any Pin VIOT –2.0V to VCC+2.0V V
Relative to Ground
Storage Temperature TSTG –65 to +150 °C
Lead Temperature TLEAD See Note (2) °C
Electrostatic Discharge Voltage VESD Human Body Model (3) –2000 to +2000 V
Notes:
1. This device has been designed and tested for the specified operation ranges. Proper operation outside of these levels is not guaranteed.
Exposure to absolute maximum ratings may affect device reliability. Exposure beyond absolute maximum ratings may cause permanent
damage.
2. Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly and the European directive on
restrictions on hazardous substances (RoHS) 2002/95/EU.
3. JEDEC Std JESD22-A114A (C1=100pF, R1=1500 ohms, R2=500 ohms).

9.2 Operating Ranges

SPEC
PARAMETER SYMBOL CONDITIONS UNIT
MIN MAX
Supply Voltage (1) VCC Industrial and Industrial Plus Temp 2.7 3.6 V
Ambient Temperature, Industrial –40 +85 °C
TA
Operating Industrial Plus –40 +105 °C
Note:
1. VCC voltage during Read can operate across the min and max range but should not exceed ±10% of the programming (erase/write)
voltage.

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 GM25Q128A
9.3 Power-Up Power-Down Timing and Requirements
SPEC
PARAMETER SYMBOL UNIT
MIN MAX
VCC (min) to /CS Low tVSL (1) 20 µs
Time Delay Before Write Instruction tPUW (1)
5 ms
Write Inhibit Threshold Voltage VWI (1) 1 2 V
Note:
1. These parameters are characterized only.
2. Normal precautions must be taken for supply rail decoupling to stabilize the VCC supply at the device. Each device in a system should
have the VCC rail decoupled by a suitable capacitor close to the package supply connection (this capacitor is generally of the order of
20µf, 0.1µf and 0.01µf in parallel).
3. CS# must track Vcc during power up, if it is not available, CS# ahead of Vcc power up timing sequence is recommended.

Figure 36a. Power-up Timing and Voltage Levels

Figure 36b. Power-up, Power-Down Requirement

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 GM25Q128A
9.4 DC Electrical Characteristics
SPEC
PARAMETER SYMBOL CONDITIONS UNIT
MIN TYP MAX
Input Capacitance CIN (1) VIN = 0V (1) 6 pF
Output Capacitance COUT (1) VOUT = 0V (1) 8 pF
Input Leakage ILI ±2 µA
I/O Leakage ILO ±2 µA
/CS = VCC,
Standby Current ICC1 15 25 µA
VIN = GND or VCC
/CS = VCC,
Power-down Current ICC2 3 5 µA
VIN = GND or VCC
Current Read Data / Dual C = 0.1 VCC / 0.9 VCC
(2)
ICC3 10 15 mA
/Quad 50MHz DO = Open
Current Read Data / Dual C = 0.1 VCC / 0.9 VCC
ICC3 13 18 mA
/Quad 70MHz (2) DO = Open
Current Read Data / Dual C = 0.1 VCC / 0.9 VCC
ICC3 25 28 mA
/Quad 104MHz (2) DO = Open
Current Write Status
ICC4 /CS = VCC 12 15 mA
Register
Current Page Program ICC5 /CS = VCC 35 40 mA
Current Sector/Block
ICC6 /CS = VCC 28 35 mA
Erase
Current Chip Erase ICC7 /CS = VCC 28 30 mA
Input Low Voltage VIL –0.5 VCC x 0.2 V
Input High Voltage VIH VCC x 0.8 VCC + 0.4 V
Output Low Voltage VOL IOL = 100 µA 0.2 V
Output High Voltage VOH IOH = –100 µA VCC – 0.2 V

Notes
1. Tested on sample basis and specified through design and characterization data. TA = 25° C, VCC = 3.3V.
2. Checker Board Pattern.

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 GM25Q128A
9.5 AC Measurement Conditions
SPEC
PARAMETER SYMBOL UNIT
MIN MAX
Load Capacitance CL 30 pF
Input Rise and Fall Times T R , TF 2.4 ns
Input Pulse Voltages VIN 0.2 VCC to 0.8 VCC V
Input Timing Reference Voltages IN 0.5 VCC V
Output Timing Reference Voltages OUT 0.5 VCC V

Note:
1. Output Hi-Z is defined as the point where data out is no longer driven.

Figure 37. AC Measurement I/O Waveform

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 GM25Q128A
9.6 AC Electrical Characteristics
SPEC
DESCRIPTION SYMBOL ALT UNIT
MIN TYP MAX
Clock frequency for Fast Read(0Bh), Dual Output(3Bh),
FR1 fC1 D.C 104 MHz
Dual I/O(BBh)
Clock frequency for Quad Output(6Bh), Quad I/O(EBh),
FR2 fC2 D.C 80 MHz
Quad I/O Word Fast Read (E7h)
Clock frequency for Read Data(03h), Read Status
fR D.C 55 MHz
Register(05h/35h/15h), Read Identification(9Fh)
Clock frequency for all Identifications, except Read Data FC D.C 104 MHz
Clock High, Low Time for all instructions except for tCLH, tCLL
45% PC ns
Read Data (03h) (1)

Clock High, Low Time tCRLH,

45% PC ns
for Read Data (03h) instruction tCRLL (1)
Clock Rise Time peak to peak tCLCH (2) 0.1 V/ns
Clock Fall Time peak to peak tCHCL (2) 0.1 V/ns
/CS Active Setup Time relative to CLK tSLCH tCSS 3 ns
/CS Not Active Hold Time relative to CLK tCHSL 3 ns
Data In Setup Time tDVCH tDSU 3.5 ns
Data In Hold Time tCHDX tDH 2 ns
/CS Active Hold Time relative to CLK tCHSH 3 ns
/CS Not Active Setup Time relative to CLK tSHCH 3 ns
/CS Deselect Time (for Read) tSHSL1 tCSH 10 ns
/CS Deselect Time (for Erase or Program or Write) tSHSL2 tCSH 50 ns
Output Disable Time tSHQZ (2) tDIS 7 ns
Clock Low to Output Valid tCLQV tV 8 ns
Output Hold Time tCLQX tHO 1.5 ns
Note：
1. Serial clock Frequency for Qual Read Instructions fc2>40Mhz only support 2.9V ~ 3.6V，when operating temperature<0o C.

57
 GM25Q128A
Continued – next page AC Electrical Characteristics (cont’d)

SPEC
DESCRIPTION SYMBOL ALT UNIT
MIN TYP MAX

Write Protect Setup Time Before /CS Low tWHSL (3) 20 ns

Write Protect Hold Time After /CS High tSHWL (3) 100 ns

/CS High to Power-down Mode tDP (2) 3 µs

/CS High to Standby Mode without ID Read tRES1 (2) 3 µs

/CS High to Standby Mode with ID Read tRES2 (2) 1.8 µs

/CS High to next Instruction after Suspend tSUS (2) 20 µs

/CS High to next Instruction after Reset tRST (2) 30 µs

/RESET pin Low period to reset the device tRESET (2) 1 µs

Write Status Register Time tW 10 15 ms

Page Program Time tPP 0.8 3 ms

Sector Erase Time (4KB) tSE 80 400 ms

Block Erase Time (32KB) tBE1 150 1,600 ms

Block Erase Time (64KB) tBE2 250 2,000 ms

Chip Erase Time tCE 65 120 s

Notes:
1. Clock high or Clock low must be more than or equal to 45%Pc. Pc = 1/fc(max).
2. Value guaranteed by design and/or characterization, not 100% tested in production.
3. Only applicable as a constraint for a Write Status Register instruction when SRP=1.
4. Quad Read are available at VIH>=0.9Vcc &VIL<=0.1Vcc

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 GM25Q128A
9.7 Serial Output Timing

9.8 Serial Input Timing

9.9 /WP Timing

59
 GM25Q128A
10 PACKAGE SPECIFICATIONS
10.1 8-Pin SOIC 208-mil (Package Code S)

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 GM25Q128A
10.2 16-Pin SOIC 300-mil (Package Code F)

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 GM25Q128A
10.3 8-Pad WSON 6x5-mm (Package Code P)

Note:
1. The metal pad area on the bottom center of the package is not connected to any internal electrical signals. It can be left floating or
connected to the device ground (GND pin). Avoid placement of exposed PCB vias under the pad.

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 GM25Q128A
10.4 8-Pad WSON 8x6-mm (Package Code E)

Note:
1. The metal pad area on the bottom center of the package is not connected to any internal electrical signals. It can be left floating or
connected to the device ground (GND pin). Avoid placement of exposed PCB vias under the pad.

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 GM25Q128A
10.5 24-Ball TFBGA 8x6-mm (Package Code B, 5x5-1 ball array)

64
 GM25Q128A
10.6 24-Ball TFBGA 8x6-mm (Package Code C, 6x4 ball array)

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 GM25Q128A
10.7 24-Ball WLCSP (Package Code Y)

Notes:
1. Dimension b is measured at the maximum solder bump diameter, parallel to primary datum C.
2. Dimension D/D2/D3 and E/E2/E3; please contact Chuangfeixin for details.

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 GM25Q128A
11 ORDERING INFORMATION

GM25Q128 AX XX X
Packing Type:
T or no Mark: Tube
Y: Tray
R: Tape & Reel

Green Code:
G: Pb Free & Halogen Free Green Package

Temperature Range:
I: Industrial ( -40℃ to 85℃)

Packing Type:
S = 8-pin SOIC 208-mil F = 16-pin SOIC 300-mil
P = WSON8 6x5-mm E = WSON8 8x6-mm
B = TFBGA 8x6-mm (5x5-1 ball array)
C = TFBGA 8x6-mm (6x4 ball array)
Y = 24-ball WLCSP

Generation:
A or No Mark: A Version

Density:
128: 128Mb
64: 64Mb
32: 32Mb
16: 16Mb

Series:
Q: 2.7~3.6V 104MHz, Uniform Sector, Quad I/O

Product Family:
25: SPI Interface Flash

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 GM25Q128A

12 REVISION HISTORY
Document Title: GM25Q128A 128 Mbit 2.7V to 3.6V, SPI Flash
Memory Document Number: 000-00000
Orig. of Submission
Rev. ECN No. Description of Change
Change Date
1.00 2019/10/21 Initial Document Release.
Modified the power supply voltage from 2.7V ~ 3.6V to 3.0V ~ 3.6V.
Removed Quad mode related instructions including 6BH, EBH, Continuous Read
Wrap read, Word Read.
Removed obtain Device ID function by ABH command.
1.1 2020/01/15
Update Hardware protect is not supported in this Version, pls Contact CFX.
Update OTP Lock Bits limitation in this version, pls contact CFX.
Update Suspend Resume limitation in this version, pls contact CFX.
Update Read Maximum Frequency.
Add Quad mode related instructions including 6BH, EBH, Continuous Read, Wrap
1.2 2020/02/11 read and Word Read.
Update Quad Read Maximum Frequency and it's applicable condition.
1.3 2020/07/13 Update Clock Low to Output Valid.
Update Hardware protect is supported.
Update OTP Lock Bits function limitation is removed.
CF2020
1.4 2020/09/04 Update Suspend Resume function limitation is removed.
090401
Update Quad mode applicable condition.
Update erase/program cycling times.
Modified the power supply voltage from 3.0V ~ 3.6V to 2.7V ~ 3.6V.
1.5 2020/09/23 Update Read Maximum Frequency
Update Memory Protection limitation in this version, pls contact CFX.
CF2021
1.6 2021/01/06 Add SFDP table.
012601
Update erase/program cycling times.
Modified the power supply voltage from 2.7V ~ 3.6V to 3.0V ~ 3.6V.
CF2021 Update Quad Read applicable condition.
1.7 2021/04/26
042601 Update Status Register limitation in this version, pls contact CFX.
Update Fast Read Dual I/O (BB) limitation in this version, pls contact CFX.
Update Page Program Time.
CF2021
1.8 2021/07/23 Update Package Figure
072301
CF2021
1.9 2021/08/05 Update Package Figure
080501
CF2021
2.0 2021/09/23 Update LB0~LB3 type and SR2 Figure
092301
CF2022
2.1 2022/02/22 Update erase/program cycles to 100,000
022201
CF2022
2.2 2022/03/16 Modified the power supply voltage from 3.0V ~ 3.6V to 2.7V ~ 3.6V
031601
CF2022
2.3 2022/07/20 Update Memory Protection limitation in this version.
072001
CF2022
2.4 2022/11/10 Update Hardware reset（/RESET PIN） is not supported
111001

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