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VLSI Exp - 1

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KOTTI NIKHITHA
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8 views7 pages

VLSI Exp - 1

Uploaded by

KOTTI NIKHITHA
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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VLSI LABORATORY (EC39004)

Experiment-1
Drupada Rongali (21EC10057)

Kotti Nikhitha(21EC10041)

Objective-1:
Design 8:1 MUX using 2:1 MUXs in both behavioural and structural styles. Demonstrate through
test bench waveforms and verify the results.

Circuit Diagrams:
• Structural Style:
8:1 MUX CODE:

TESTBENCH CODE:
RESULTS:

• Behavioural Style:
8:1 MUX CODE:

TESTBENCH CODE:

RESULTS:

Objective-2:
Implement a 4-bit ripple carry adder using 4 1-bit full adders. Do exhaustive testing through
test bench for all the possible input combinations.

Circuit Diagrams:

1-Bit Full adder :


CODE :
TESTBENCH CODE:

RESULTS:

4-Bit Ripple Carry Adder:


CODE:
TESTBENCH CODE:

RESULTS:

DISCUSSION&CONCLUSION:

1. Introduction to 8:1 MUX Design:


- In this laboratory experiment, our primary objective was to design an 8:1 multiplexer (MUX) using
both behavioural and structural styles in Verilog.
- The 2:1 MUX served as the foundational component, initially implemented in the behavioural
style. This approach focused on describing functionality without revealing internal structure, utilizing
logical gates to achieve the desired multiplexing behaviour.

2. Behavioural Design of 2:1 MUX:


- The behavioural 2:1 MUX module was designed to take two input signals (in1 and in2), a
selection signal (sel), and produce the output signal (out).
- Employing logical gates (AND, OR, and NOT), this approach provided an abstract representation
of the MUX's behaviour, emphasizing functionality over internal structure.

3. Structural Implementation of 8:1 MUX:


- Moving from behavioural to structural design, the 8:1 MUX was created by cascading four
instances of the 2:1 MUX. This hierarchical structure interconnected the outputs of the first four
MUXs into the inputs of the next layer until the final 8:1 MUX was formed.
- The structural style explicitly defined the interconnection of lower-level components, promoting
modularity and reusability in the design.

4. Testing and Verification:


- A comprehensive testbench was developed to verify the correctness of both behavioral and
structural implementations.
- Thorough testing ensured that the 8:1 MUX design was robust and reliable, covering various
input scenarios to validate its functionality under different conditions.

5. Introduction to 4-bit Ripple Carry Adder Design:


- In a subsequent phase of the lab, we implemented and tested a 4-bit ripple carry adder using four
1-bit full adders.
- The design followed a modular approach, with each full adder contributing to the addition of a
corresponding bit in the operands.

6. 1-bit Full Adder Module Design:


- The 1-bit full adder module (adder) was implemented using XOR, AND, and OR gates, adhering
to standard full adder logic.
- Inputs ('a,' 'b,' and 'c') represented the two bits to be added and the carry from the previous stage,
while outputs ('s' and 'cout') represented the sum and carry-out, respectively.

7. 4-bit Ripple Carry Adder Module Design:


- The 4-bit ripple carry adder module (ripple) utilized four instances of the 1-bit adder, with each
handling one bit of the operands.
- The carry-out from each stage was propagated to the next, creating a ripple effect. This modular
design simplified the overall structure, promoting reusability and ease of testing.

8. Testing and Reliability:


- Exhaustive testing was conducted to ensure the reliability of the 4-bit ripple carry adder across all
possible input scenarios.
- The modular design facilitated independent testing of each 1-bit adder, contributing to a thorough
and reliable overall testing approach.

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