Rectifiers, Filters and Regulator

Transistor Configurations and

Op AMP

Dr. Supreet Singh

Basic Block Diagram of Regulated
power Supply
Wave forms at various points in a
Regulated power supply
 Rectification
• Rectification is a process of converting the
alternating quantity (voltage or current) into a
corresponding direct quantity(voltage or
current).

• The input to a rectifier is AC whereas its

output is unidirectional or DC.
 Rectifiers
• Rectifier is an electronic device which is used
for converting an alternating quantity (Voltage
or current) into unidirectional i.e. DC quantity
(Voltage or current).
• Block diagram of Rectifier:
 Need of Rectification
• Every electronic circuit such as amplifiers,
needs a DC power source for its operation.
• This DC voltage has to be obtained from AC
supply.
• For this the AC supply has to be reduced ()
Stepped down first using a Step down
transformer and then converted to dc by using
rectifier.
Types of Rectifier
Half Wave Rectifier
Full Wave Rectifier (Center Tapped
Transformer)
Full Wave Rectifier (Bridge)
For more detail contact us
 Operational amplifier
• Operational amplifier, or simply OpAmp refers to an integrated
circuit that is employed in wide variety of applications (including
voltage amplifiers)
Noninverting input ii io

vid vo

vo  Ad (vi1  vi 2) Avo vi
vi1 vi 2 Inverting input
vi1 vi 2

• OpAmp is a differential amplifier having both inverting and non-

inverting terminals
• What makes an ideal OpAmp
 infinite input impedance
 Infinite open-loop gain for differential signal
 zero gain for common-mode signal
 zero output impedance
 Infinite bandwidth
Summing point constraint
• In a negative feedback configuration, the
feedback network returns a fraction fo the output
to the inverting input terminal, forcing the
differential input voltage toward zero. Thus, the
input current is also zero.
• We refer to the fact that differential input voltage
and the input current are forced to zero as the
summing point constraint
• Steps to analyze ideal OpAmp-based amplifier
circuits
 Verify that negative feedback is present
 Assume summing point constraints
 Apply Kirchhoff’s law or Ohm’s law
Some useful amplifier circuits
• Inverting amplifier
R2
R1 Av  vout / vin   R2 / R1
Z in  R1
vout Rl Z out  0
vin

• Noninverting amplifier
R2
R1 Av  vout / vin  1  R2 / R1
Z in  
vin vout Rl Z out  0

• Voltage follower if R2  0 and R1 open circuit (unity gain)

Amplifier design using OpAmp
• Resistance value of resistor used in
amplifiers are preferred in the range of
(1K,1M)ohm (this may change depending
on the IC technology). Small resistance
might induce too large current and large
resistance consumes too much chip area.
OpAmp non-idealities I
• Nonideal properties in the linear range of operation
 Finite input and output impedance
 Finite gain and bandwidth limitation
 Generally, the open-loop gain of OpAmp as a function of frequency
is
A0ol
Aol ( f )  , A0ol is open  loop gain at DC,
1  j ( f / f bol )
f bol is open  loop break frequency , also called do min at pole

 Closed-loop gain versus frequency for non-inverting amplifier

A0cl A0ol R1
Acl ( f ) , A0cl  , f bcl  f bol (1  A0ol ),  
1  j ( f / f bcl ) 1  A0ol R1  R2

 Gain-bandwidth product:
f t  A0cl f bcl  A0ol f bol , where f t is called unity  gain frequency
 Closed-loop bandwidth for both non-inverting and inverting
amplifier
ft A f
f bcl   0ol bol
1  R2 / R1 1  R2 / R1
OpAmp non-idealities II
• Output voltage swing: real OpAmp has a maximum and minimum
limit on the output voltages
 OpAmp transfer characteristic is nonlinear, which causes
clipping at output voltage if input signal goes out of linear range
 The range of output voltages before clipping occurs depends on
the type of OpAmp, the load resistance and power supply
voltage.
• Output current limit: real OpAmp has a maximum limit on the output
current to the load
 The output would become clipped if a small-valued load
resistance drew a current outside the limit
• Slew Rate (SR) limit: real OpAmp has a maximum rate of change of
the output voltage magnitude
dv
 limit dto  SR
 SR can cause the output of real OpAmp very different from an
ideal one if input signal frequency is too high
 Full Power bandwidth: the range of frequencies for which the
OpAmp can produce an undistorted sinusoidal output with peak
amplitude equal to the maximum allowed voltage output
SR
f FP 
2 vo max
 Slew Rate

 Linear RC Step Response: the slope of the step response is

proportional to the final value of the output, that is, if we
apply a larger input step, the output rises more rapidly.
 If Vin doubles, the output signal doubles at every point,
therefore a twofold increase in the slope.
 But the problem in real OpAmp is that this slope can not
exceed a certain limit.
Copyright © Mcgraw Hill Company
OpAmp non-idealities III
• DC imperfections: bias current, offset current and offset voltage
 bias current I B : the average of the dc currents flow into the noninverting
terminal I B  and inverting terminal I B  , I B  1 / 2( I B  I B )
 offset current: the half of difference of the two currents, I off  1 / 2( I B  I B )
 offset voltage: the DC voltage needed to model the fact that the output is
not zero with input zero, Voff
• The three DC imperfections can be modeled using DC current and voltage
sources
I B IB
Voff
Ideal
I B I off / 2

IB

• The effects of DC imperfections on both inverting and noninverting amplifier

is to add a DC voltage to the output. It can be analyzed by considering the
extra DC sources assuming an otherwise ideal OpAmp
• It is possible to cancel the bias current effects. For the inverting amplifier, we
can add a resistor R  R1 // R2 to the non-inverting terminal
 DC offset of an differential pair

 When Vin=0, Vout is NOT 0 due to mismatch of transistors in real circuit

design.
 It is more meaningful to specify input-referred offset voltage, defined as
Vos,in=Vos,out / A.
 Offset voltage may causes a DC shift of later stages, also causes limited
precision in signal comparison.
Copyright © Mcgraw Hill Company
 Behavioral modeling of OpAmp
 Behavioral models is preferred to include as many non-idealities of
OpAmp as possible.
 They are used to replace actual physical OpAmp for analysis and fast
simulation.
Important amplifier circuits I
• Inverting amplifer • Noninverting amplifier

Av   R2 / R1 Av  1  R2 / R1
Z in  R1 Z in  
Z out  0 Z out  0

• AC-coupled inverting amplifier • AC-coupled noninverting amplifier

Av  1  R2 / R1
Av   R2 / R1
Z in  Rbias
Z in  R1
Z out  0
Z out  0

• Bootstrap AC-coupled voltage

• Summing amplifier follower
Av   R f / R A / B Av  1
Z in  
Z in1  RA for v A
Z out  0
Z in 2  RB for vB
Z out  0

Graphs from Prentice Hall

 Important amplifier circuits II
• Differential amplifier • Howland voltage-to-current
converter for grounded load
Z in  R3  R4 for v1
Z out  0

G m  1 / R2
Z in  R1 R2 /( R2  RL )
Z out  
• Instrumentation qualify Diff Amp
• Current-to-voltage amplifier
Z in   Rm   R f
Z out  0 Z in  0
Z out  0

• Voltage-to-current converter • Current amplifier

G m  io / vin  1 / R f Avi  (1  R2 / R1 )

Z in   Z in  0
Z out   Z out  

Graphs from Prentice Hall

Important amplifier circuits III
• Integrator circuit: produces an • Differentiator circuit: produces
output voltage proportional to an output proportional to the
the running time integral of the time derivative of the input
input signal voltage

Graphs from Prentice Hall

 Bipolar Junction transistor

Holes and electrons Three terminal device

determine device characteristics
Control of two terminal currents
How can we make a BJT from a pn diode?
• Take pn diode
V • Remember reverse bias
I
characteristics
• Reverse saturation current: I0
p n

I0 V
How can we make a BJT from a pn diode?
• Take pn diode
V • Remember reverse bias
I
characteristics
e- • Reverse saturation current: I0
p n Caused by minority carriers
h+ swept across the junction

I • np and pn low

I0 small

I0 V
Thus:
A forward biased p+n diode is a good hole injector
A reverse biased np diode is a good minority carrier collector
V
V I0
I
dpn
h+ e-
p+ n n p
e- L h+ x
p
If W large → holes
W recombine
Excess hole
concentration reduces
exponentially in W to
some small value.
 Carrier flow in BJTs
E B C
IE p+ n p IC
holes
e- gain, reverse bias
IB

holes
IE
IC
ICB0
I’B I”B
Recombination
e- loss, forward bias e- loss

IB = I’B + I”B – ICB0

IB
 Control by base current : ideal case.
Based upon space charge neutrality
Electrostatically neutral
Base region
IE = Ip
h+ tt transit time
t t < tp
e-
tp recombine with
Wb << Lp
Based on the given timescales, holes can pass through the narrow base
before a supplied electron recombines with one hole: ic/ib = tp/tt
The electron supply from the base contact controls the forward bias to
ensure charge neutrality!
 How good is the transistor?

• Wish list:
E IEp B C
IC
• IEp>>IEn
or g = IEp/(IEn + IEp) ≈ 1
g: emitter injection efficiency
Injection of carriers

equilibrium
• IC ≈ IEp
e- VBE>0 or B= IC/IEp ≈ 1
IEn B: base transport factor
h + W b < Lp x or a= IC/IE ≈ 1
a: current transfer ratio
• IB ≈ IEn + (1-B) IEp
No amplification! thus b= IC/IB = a/(1-a)
b: current amplification factor
Amplification!
ICB0 ignored
 Review 1 – BJT basics
IC
Forward active mode (ON)
IE

VBC
V VV
EB IE IC BC

p+ B
n E p
E C

W < Lp
Forward biased p+n
junction is a hole injector Reverse biased np junction is
a hole collector
 Review 1 – BJT basics
IC
Forward active mode (ON)
IE

VBC
V V
EB IE IB=I’B+I”B I C VBC

p+ B
n E p
E C

W < Lp
Forward biased p+n
junction is a hole injector Reverse biased np junction is
a hole collector
 Review 2
Amplification?

IB = I’B + I”B – ICB0

Recombination only case: I’B, ICB0 negligible

ic/ib = tp/tt Carriers supplied by the base current stay much

longer in the base: tp than the carriers supplied
b = tp/tt
by the emitter and travelling through the base: tt.
But in more realistic case: I’B is not negligible

b = IC/IB With IB electrons supplied by base = I’B = In

IC holes collected by the collector = Ip
 Currents?

• In order to calculate currents in pn junctions, knowledge of

the variation of the minority carrier concentration is
required in each layer.
• The current flowing through the base will be determined by
the excess carrier distribution in the base region.
• Simple to calculate when the short diode approximation is
used: this means linear variations of the minority carrier
distributions in all regions of the transistor. (recombination
neglected)
• Complex when recombination in the base is also taken into
account: then exponential based minority carrier
concentration in base.
 Narrow base: no recombination: Ip
→ minority carrier density gradient in the base

DpE = pn0(e eVEB/kT – 1) ≈ pn0 e eVEB/kT dp(x)

DpC = pn0(e –e|VBC|/kT – 1) ≈ -pn0
DpE
Linear variation of excess carrier concentration:
dp( x)  Ax  B
DpE  DpC DpE DpC
A 
 Wb Wb
0 Wb x
B  DpE  DpC  DpE
 x 
dp( x)  DpE 1  

 W b
Note: no recombination
 Collector current: Ip
ddp( x)
Diffusion current: I p  eADp
dx
ddp( x) DpE

dx Wb  eVEB 
 
 kT 
Dp E eADp pn0 e
Hole current: I p  eADp 
Wb Wb

Collector current I C  I p No recombination, thus all injected

holes across the BE junction are
collected.

Base current??
 Emitter current
The emitter current is the total current flowing through the
base emitter contact since IE=IC+IB (current continuity)

 eVEB 
 Dn n p0 D p pn0   
Emitter current: I E  I n  I p  eA  e

 kT 

 xe WB 

IC I p D p pn0 xe
Current gain: b   
I B I n Dn n p0Wb
 Non-ideal effects in BJTs
• Base width modulation
V VVBC
BE IE IC

p+ Bn p
E C
Original base width
Depletion width
Effective base width changes with VBC
Metallurgic junction
 Conclusions

• Characteristics of bipolar transistors are based on

diffusion of minority carriers in the base.
• Diffusion is based on excess carrier concentrations:
– dp(x)
• The base of the BJT is very small:
– dp(x) = C1 ex/Lp + C2 e-x/Lp
• Base width modulation changes output impedance of
BJT.
Transistor switching

Ic

t
p-type material
n-type material

iC

iB RL ib higher
iC
RS ECC
ECC /RL
ib
es iE On

es
-vCE
ECC
t Off
 iC

iC
ic=biB

RL -vCE

iB

ECC
RS
es

Es
t
iE
-Es
 iC

ic=biB
iC

RL -vCE

ECC

RS
es

Es
t iE

-Es
 iC
ic≠biB
iC

RL -vCE

ECC

RS
es Ic= ECC /RL

Es
t iE

-Es
 Switching cycle
iB
IB IB≈Es/RS
Switch to ON
iC
Switch OFF
iB RL
-IB
ECC dp
RS
QB DpE
t2
es iE DpE
Es
Qs ts
-Es t DpE
t1 DpC
iC
ECC /RL t1 ts t2 t’s 0
-pn x
tsd t0
iC Wb
IC IC≈ECC/RL
-vCE
ECC
 Charge in base (linear)
• Cut-off • Saturation
– VEB<0 & VBC<0 – VEB>0 & VBC≥0
– DpE=-pn & DpC=-pn – DpE = pn (eeVEB/kT – 1)
– DpC = 0 (VBC=0)

dp dp
DpE VBC>0
DpE
DpC
-pn x x
Wb Wb
 Currents - review.
forward active mode

dc(x)
IE = IpEB + InEB

IC = IpBC + InBC DpE

IC ≈ IpBC
DnE
IE = IB + IC
IB = IE - IC x
-Xe -LpE DpC Xc
DnC LpC
IB = InEB+ IpEB - IpBC 0 Wb < LnB

Term due to recombination

 Switching cycle - review
Common emitter cicuit iB Switch to ON
IB IB≈Es/RS
iC With IB>ICmax/b

iB RL Over-saturation
-IB
ECC dp
RS
QB DpE
t2
es iE DpE
Es
Qs ts
-Es t DpE
t1 DpC
Load line technique t1 ts t2 -pno 0
t0 x
iC
ECC /RL iC Wb
IC ICmax≈ECC/RL pno << DpE

ECC -vCE
 Switching cycle - review
Common emitter cicuit iB Switch OFF
IB
iC

iB RL
-IB≈-Es/RS
ECC dp
RS
QB DpE
t2
es iE DpE
Es
Qs t’s
-Es t
DpC
t3
Load line technique t2 t’s t3 t4 -pno 0
t4 x
iC tsd
ECC /RL iC Wb
IC IC≈ECC/RL

-vCE
ECC
ON switching OFF=0→ON

RL
C
p
e(t) RS vbc ECC
B n
veb
p
t E
iC

dpnB(x) ICsat
E I B C
B QB
IB
IB IBtp

IB Qsat

IB

0 WB x tsat t tsat t
t<0 dQB (t ) QB (t )
i (t )   t<tsat
t≥0 veb= 0→ON≈0.7V tp QB (t ) I Bt p    t 
1  exp  
dt iC (t )  
 tt t t   t p 
E-p B-n
   t  t≥tsat
QB  I Bt p 1  exp  
  t 
 p  iC (t ) 
ECC
 I Csat
& RL
x WB
RS +E>>0.7V
QB   e A dn
x 0
pB ( x)dx
E
IB 
RS
 Driving off
Time to turn the BJT OFF is determined by:
1) The degree of over-saturation (BC junction)
2) The off-switching of the emitter-base diode
ib CASE 1: OFF=IB=0 ib CASE 2: OFF=-IB
0N (saturation)→OFF 0N (saturation)→OFF
IB IB

-IB t
t Qb
Qb IB t p
IB t p
Qs
Qs = I C t t t
-IB tp
tsd t tsd
iC iC
IC IC

t
t
OFF switching 0N (saturation)→OFF - CASE 1: OFF=IB=0

RL
C
p
e(t) RS vbc ECC
B n
veb
p
t E
iC tsd
dpnB(x) ICsat
E t<0
IB B C
QB
t≥0 IB=0
IBtp tsd
tsd Qsat

0 WB x tsd t tsd t
t<0 dQB (t ) QB (t )
i (t )   t<tsd
veb= 0.7V (ON)→0V dt tp
 ECC
E-p B-n iC (t )   I Csat
 t  RL
QB (t )  I Bt p exp  
t 
 p t≥tsd
& QB (t ) I Bt p  t 
iC (t )   exp  
x WB tt tt t 
RS  p
 e A dn pB ( x)dx
E=0V QB 
E x 0
IB  0
RS
 0N (saturation)→OFF - CASE 2: OFF=-IB

RL
C
p
e(t) RS vbc ECC
B n
veb
p
t E
iC
tsd
dpnB(x) ICsat
E t<0
IB B C
QB
t≥0 -IB
IBtp tsd
tsd Qsat

0 WB x tsd t tsd t
t<0
veb= 0.7V (ON)→-E

E-p B-n dQB (t ) QB (t )

i (t )  
dt tp t<tsd
 ECC
iC (t )   I Csat
  t   RL
QB (t )  I Bt p 2 exp    1
RS -E  t  
 p  t≥tsd
E QB (t ) I Bt p   t  
IB  & iC (t )   2 exp    1
RS x WB tt t t   t p  
QB   e A dn
x 0
pB ( x)dx
0N (saturation)→OFF - CASE 1: OFF=IB=0 0N (saturation)→OFF - CASE 1: OFF=-IB

iC
iC tsd t<tsd tsd t<tsd
E
iC (t )  CC  I Csat ECC
ICsat RL ICsat iC (t )   I Csat
RL

t≥tsd t≥tsd
QB (t ) I Bt p  t 
iC (t )   exp   QB (t ) I Bt p   t  
tt tt t  iC (t )   2 exp    1
 p tt t t   t p  

tsd t tsd t

STORAGE DELAY TIME: tsd

ECC I Bt p   t sd  ECC I Bt p   t  
iC (t sd )  I Csat   exp   iC (t sd )  I Csat   2 exp  sd   1
tt  t  tt  
RL  p  RL   tp  
 I Bt p   
t sd  t p ln    
t  I Bt p 
 Csat t 
I t sd  t p ln
  1 1 I Bt p  
 I Csatt t    
  2 2 I Csatt t  

shorter delay
 Transients
Turn-on: off to saturation
iC
IC IC≈ECC/RL

t
ts
 Time to saturation
QB
ON switching OFF=0→ON
IBtp
   t 
RL Qsat QB  I Bt p 1  exp 
  t p 
C  
p
e(t) RS vbc ECC
B n tsat t
veb
p
t E iC
ECC
ICsat iC (t )   I Csat
t≥tsat RL
t<tsat
QB (t ) I Bt p    t 
iC (t )   1  exp  
tt tt   t p 

tsat t

I Bt p    t 
t=tsat iC (t sat )  1  exp sat   I Csat
t t   t p 
 