?syllabus COD
?syllabus COD
Prerequisite EC1002-1
Course Objectives:
2. Learn arithmetic unit and perform fixed point and floating-point addition, subtraction, multiplication
and division in binary 2’s complement number system
3. Understand the basic processing unit in terms of control unit, execution of instructions, write control
sequences for instructions. Learn the instruction and thread level parallelism.
4. Explore the design of hierarchical memory system including cache memories and virtual memory.
Compare the performance.
5. Discuss serial and parallel communication with I/O devices and standard I/O interfaces available.
UNIT-I
15 Hours
Functional units, Basic Operational Concepts, Performance, Instructions execution and straight-line
sequencing, Branching, condition codes.
ARITHMETIC OPERATIONS:
Multiplication of Positive Numbers, Signed Operand Multiplication, Integer Division, IEEE standard for
Floating-point Numbers.
UNIT-II
15 Hours
INPUT/OUTPUT ORGANIZATION:
Accessing I/O Devices, Interrupts –Interrupt Hardware, Enabling and Disabling Interrupts, Exceptions,
Handling Multiple Devices, Controlling Device Requests, Buses, Direct Memory Access, PCI Bus and
USB(Basics only).
UNIT-III
10 Hours
MEMORY SYSTEMS:
Memory System: Basic Concepts, Semiconductor RAM Memories, Read Only Memories, Speed, Size, and
Cost, Cache Memories –Mapping Functions, FIFO and LRU replacement policies, Performance
Considerations, Virtual Memories.
2. Learn arithmetic unit and perform fixed point and floating-point addition, subtraction,
multiplication and division in binary 2’s complement number system
3. Understand the fine grain details of basic processing unit in terms of control unit, execution of
instructions and learn the scope for instruction and thread level parallelism. Implementation of
instructions for single and multiple bus configuration.
4. Explain different ways of communication with I/O devices and standard I/O interfaces.
5. Demonstrate the computer architecture concepts in the design of hierarchical memory system
including cache memories and virtual memory.
↓ Course Outcomes 1 2
IS2101-1.1 3 1 1 1 1 3
IS2101-1.2 3 2 1 1 1 1 3
IS2101-1.3 3 2 1 1 1 1 1 3
IS2101-1.4 3 1 1 1 1 1 3
IS2101-1.5 3 2 2 1 1 1 1 3
TEXTBOOK:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer Organization”, 5th Edition, TMH, 2011.
REFERENCE BOOKS:
1. William Stallings, “Computer Organization & Architecture”, 7th Edition, PHI, 2006.
2. Vincent P. Heuring & Harry F. Jordan, “Computer Systems Design and Architecture”, 2nd Edition,
Pearson Education, 2004.
3. David A. Patterson, John L. Hennessy, “Computer Organization and Design”, 4th Edition Elsevier, 2012.
5. John L. Hennessey and David A. Patterson, “Computer Architecture, A Quantitative Approach”, 6th
Edition, Elsevier, 2017
6. Shameem Akhter and Jason Roberts, “Multicore programming- Increasing performance through
software multithreading”, Intel press, 2006
1. https://dcs.abu.edu.ng/staff/sani-ahmad-hassan/course materials/COSC303_LEC.pdf
2. http://www.cse.iitm.ac.in/~vplab/courses/comp_org/
3. http://www.ddegjust.ac.in/studymaterial/msc-cs/ms-07.pdf
4. http://nsec.sjtu.edu.cn/data/MK.Computer.Organization.and.Design.4th.Edition.Oc t.2011.pdf