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Mos transistor:

• Enhancement mode transistors

• Depletion mode transistors

Mos circuit symbols:

Terminals of MOS Transistor: G – Gate ; S – Source ;D – Drain ; B – Substrate or Body

N-Channel MOSFET:

N-Transistor Operation – Cutoff:

 Vgs << Vt : Transistor OFF

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  Majority carrier in channel (holes)

 No current from source to drain

N Transistor Operation – Subthreshold:

 0 < Vgs < Vt : Depletion region

 Electric field repels majority carriers (holes)

 Depletion region forms - no carriers in channel

 No current flows (except for leakage current)

N Transistor Operation – ON:

 Vgs > Vt , VDS=0: Transistor ON

 Electric field attracts minority carriers (electrons)

 Inversion region forms in channel

 Depletion region insulates channel from substrate

 Current can now flow from drain to source!

N Transistor Operation – Linear:

 Vgs > Vt , VDS <VGS -VT : Linear (Active) mode

 Combined electric fields shift channel and depletion region

 Current flow dependent on VGS, VDS

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N Transistor Operation – Saturation:

 Vgs > Vt , VDS >VGS -VT : Saturated mode

 Channel “pinched off”

 Current still flows due to electron drift

 Current flow dependent on VGS

P Transistor Operation:

 Opposite of N-Transistor

 Vgs >> Vt : Transistor OFF

Majority carrier in channel (electrons)

No current from source to drain

 0 > Vgs > Vt : Depletion region

Electric field repels majority carriers (electrons)

Depletion region forms - no carriers in channel

No current flows (except for leakage current)

 Vgs < Vt , VDS=0: Transistor ON

Electric field attracts minority carriers (holes)

Inversion region forms in channel

Depletion layer insulates channel from substrate

Current can now flow from source to drain!

P Transistor Modes of Operation:

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  Vgs <Vt , VDS >VGS -VT : Linear (Active) mode

 Combined electric fields shift channel and depletion region

 Current flow dependent on VGS, VDS

 Vgs < Vt , VDS <VGS -VT : Saturation mode

 Channel “pinched off”

 Current still flows due to hole drift

 Current flow dependent on VGS

I-V Characteristics of MOS Transistors:

nMOS Fabrication:

 The fabrication processes used for nMOS are relevant to CMOS and Bi-CMOS which may be
viewed as involving additional fabrication steps.

1. Processing is carried out on a thin wafer cut from a single crystal of silicon of high purity into
which the required p-impurities are introduced as the crystal is grown.

Such wafers are typically 4" to 8" in diameter and 0.4 mm thick and are doped with, say, boron to
impurity concentrations of 1015/cm3 to 1016/cm3, giving resistivity in the approximate range 25
Ohm/cm to 2 Ohm/cm.

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2 . A layer of silicon dioxide (SiO2), typically 1 mm thick, is grown all over the surface of the wafer to
protect the surface, act as a barrier to dopants during processing, and provide a generally insulating
substrate onto which other layers may be deposited and patterned.

3. The surface is now covered with a photoresist which is deposited onto the wafer and spun to
achieve an even distribution of the required thickness.

4. The photoresist layer is then exposed to ultraviolet light through a mask which defined those
regions into which diffusion is to take place together with transistor channels,

Assume, for example, that those areas exposed to ultraviolet radiation are polymerized
(hardened), but that the areas required for diffusion are shielded by the mask and remain
unaffected.

5 . These areas are subsequently readily etched away together with the underlying silicon dioxide
so that the wafer surface is exposed in the window defined by the mask.

6. The remaining photoresist is removed and a thin layer of SiO2 (0.1mm typical) is grown over the
entire chip surface and then polysilicon is deposited on top of this to form the gate structure.

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 * The polysilicon layer consists of heavily doped polysilicon deposited by

chemical vapour deposition (CVD).

* In the fabrication of fine pattern devices, precise control of thickness,

impurity concentration, and resistivity is necessary.

7. Further photoresist coating and masking allows the poly-silicon to be patterned

(as shown in Step 6), and then the thin oxide is removed to expose areas into which n-type
impurities are to be diffused to form the source and drain as shown.

Diffusion is achieved by heating the wafer to a high temperature and passing a gas
containing the desired n-type impurity (for example, phosphorus) over the surface as indicated in
Figure . Note that the poly-silicon with underlying thin oxide and the thick oxide act as masks during
diffusion - the process is self-aligning.

8. Thick oxide (SiO2) is grown over all again and is then masked with photoresist and etched to
expose selected areas of the polysilicon gate and the drain and source areas where connections (i.e.
contact cuts) are to be made.

9. The whole chip then has metal (aluminium) deposited over its surface to a thickness typically of
1 mm. This metal layer is then masked and etched to form the required interconnection pattern.

The process revolves around the formation or deposition and patterning of three layers,
separated by silicon dioxide insulation.

The layers are:

1. Diffusion within the substrate,

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 2. Poly-silicon on oxide on the substrate, and

3. Metal insulated again by oxide.

Formation of Depletion mode devices:

The Depletion mode device is formed by introducing a masked ion – implantation for the step b/n
step 5 step 6 for channel establishment .

Some extra process steps are necessary such as

 Over-glassing of whole wafer, except where the contacts are required.

Summary of an nMOS process:

• Processing takes place on a p-doped silicon crystal wafer on which is grown a ‘thick’

layer of SiO2.

• Mask 1 - Pattern SiO2 to expose the silicon surface in areas where paths in the diffusion layer or
source, drain or gate areas of transistors are required. Deposit thin oxide over all. For this reason,
this mask is often known as the ‘thinox’ mask but some texts refer to it as the diffusion mask.

• Mask 2 - Pattern the ion implantation within the thinox region where depletion mode

devices are to be produced - self-aligning.

• Mask 3 - Deposit polysilicon over all (1.5mm thick typically), then pattern using Mask

Using the same mask, remove thin oxide layer where it is not covered by polysilicon.

• Diffuse n+ regions into areas where thin oxide has been removed. Transistor drains and sources
are thus self-aligning with respect to the gate structure.

• Mask 4 - Grow thick oxide over all and then etch for contact cuts.

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• Mask 5 - Deposit metal and pattern with this mask.

• Mask 6 - This mask is required for the overglassing process step, and is called the passivation
mask.

Introduction to cmos Fabrication:

There are a number of approaches to CMOS fabrication, including the p-well, the n-well, the
twin-tub, and the silicon-on-insulator processes.

The p-well and n-well processes are widely used in practice (the n-well process was an easy
retrofit to existing nMOS lines).

Complementary MOS fabrication :

• CMOS Technology depends on using both N-Type and P-Type devices on the same chip.

• The two main technologies to do this task are:

– P-Well (Will discuss the process steps involved with this technology)

• The substrate is N-Type. The P-Channel device is built directly on the

substrate, while the N-channel device is built into a P-Type well within the
parent N-Type substrate.

– N-Well

• The substrate is P-Type. The N-channel device is built directly on the

substrate, while the P-channel device is built into a N-type well within the
parent P-Type substrate.

• Two more advanced technologies to do this task are:

Becoming more popular for sub-micron geometries where device performance and density
must be pushed beyond the limits of the conventional p & n-well CMOS processes.

– Twin Tub

• Both an N-Well and a P-Well are manufactured on a lightly doped N-type

substrate.

– Silicon-on-Insulator (SOI) CMOS Process

• SOI allows the creation of independent, completely isolated nMOS and

pMOS transistors virtually side-by-side on an insulating substrate.

p-well process:

The basic processing steps are of the same nature as those used for nMOS.

In primitive terms, the structure consists of an n-type substrate in which p-devices may be
formed by suitable masking and diffusion and, in order to accommodate n-type devices, a deep p-
well is diffused into the n-type substrate as shown.

This diffusion must be carried out with special care since the p-well doping concentration
and depth will affect the threshold voltages as well as the breakdown voltages of the ntransistors.

To achieve low threshold voltages (0.6 to 1.0V), we need either deep well diffusion or high
well resistivity. However, deep wells require larger spacing between the n- and p-type transistors
and wires, because of lateral diffusion, and therefore require a larger chip area.

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P-well on N-substrate :

Steps :

• N-type substrate

• Oxidation, and mask (MASK 1) to create P-well (4-5m deep)

• P-well doping

P-well acts as substrate for nMOS devices.

The two areas are electrically isolated using thick field oxide (and often

isolation implants [not shown here])

Poly-silicon Gate Formation :

Steps :

• Remove p-well definition oxide

• Grow thick field oxide

• Pattern (MASK 2) to expose nMOS and pMOS active regions

• Grow thin layer of SiO2 (~0.1m) gate oxide, over the entire chip surface

• Deposit polysilicon on top of gate oxide to form gate structure

• Pattern poly on gate oxide (MASK 3)

nMOS P+ Source/Drain difusion – self-aligned to Poly gate :

 Implant P+ nMOS S/D regions (MASK 4)

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pMOS N+ Source/Drain difusion – self-aligned to Poly gate :

Implant N+ pMOS S/D regions (MASK 5 – often the inverse of MASK 4)

pMOS N+ Source/Drain difusion, contact holes & metallisation :

Oxide and pattern for contact holes (MASK 6)

Deposit metal and pattern (MASK 7)

Passivation oxide and pattern bonding pads (MASK 8)

P-well acts as substrate for nMOS devices.

Two separate substrates : requires two separate substrate connections

Definition of substrate connection areas can be included in MASK 4/MASK5

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CMOS N-well process :

An N-well process is also widely used.

N-well CMOS circuits are also superior to p-well because of the lower substrate bias effects
on transistor threshold voltage and inherently lower parasitic capacitances associated with source
and drain regions.

Main steps in a typical n-well Process:

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Advantages:

The n-channel devices are used to form logic elements that provides :

1. High Speed &

2. High Density.

Latch-up problem can be reduced by using a low resistance epitaxial P-type substrate as a
starting material, which acts as a very low resistance ground-plane to collect substrate currents.

Disadvantages:

In conventional p & n-well CMOS process, the doping density of the well region is typically higher
than the substrate , which results in un-balanced drain Parasitics.

The Twin-tub process avoids this Problem.

Twin-Tub (Twin-Well) CMOS Process

This technology provides the basis for separate optimization of the nMOS and pMOS
transistors, thus making it possible for threshold voltage, body effect and the channel
transconductance of both types of transistors to be tuned independently.

Generally, the starting material is a n+ or p+ substrate, with a lightly doped epitaxial layer on
top. This epitaxial layer provides the actual substrate on which the n-well and the p-well are formed.

Since two independent doping steps are performed for the creation of the well regions, the
dopant concentrations can be carefully optimized to produce the desired device characteristics. The
Twin-Tub process is shown below.

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 In the conventional p & n-well CMOS process, the doping density of the well region is
typically about one order of magnitude higher than the substrate, which, among other effects,
results in unbalanced drain parasitics.

*The twin-tub process avoids this problem.

Silicon-on-Insulator (SOI) CMOS Process :

Rather than using silicon as the substrate material, technologists have used an insulating
substrate to improve process characteristics such as :

1. speed and

2. latch-up susceptibility.

The SOI CMOS technology allows the creation of independent, completely isolated nMOS
and pMOS transistors virtually side-by-side on an insulating substrate.

A cross-section of nMOS and pMOS devices using SOI process is shown below:

1. The SOI CMOS process is considerably more costly than the standard p & n-well CMOS
process.

2. Yet the improvements of device performance and the absence of latch-up problems can
justify its use, especially for deep-sub-micron devices.

Advantages:

The main advantages of this technology are:

1. The higher integration density (because of the absence of well regions),

2. complete avoidance of the latch-up problem,

3. lower parasitic capacitances compared to the conventional p & n-well or twin-tub

CMOS processes.

Bi-CMOS Technology:

Combines Bipolar and CMOS transistors in a single integrated circuit

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 By retaining benefits of bipolar and CMOS, BiCMOS is able to achieve VLSI circuits with
speed-power-density performance previously unattainable with either technology individually.

Characteristics of CMOS Technology:

 Lower static power dissipation

 Higher noise margins

 Higher packing density – lower manufacturing cost per device

 High yield with large integrated complex functions

 High input impedance (low drive current)

 Scalable threshold voltage

 High delay sensitivity to load (fan-out limitations)

 Low output drive current (issue when driving large capacitive loads)

 Low transconductance , where transconductance , gm  Vin

 Bi-directional capability (drain & source are interchangeable)

 A near ideal switching device

Characteristics of Bipolar Technology:

 Higher switching speed

 Higher current drive per unit area, higher gain

 Generally better noise performance and better high frequency characteristics

 Improved I/O speed (particularly significant with the growing importance of package
limitations in high speed systems).

 high power dissipation

 lower input impedance (high drive current)

 low voltage swing logic

 low packing density

 low delay sensitivity to load

 high gm (gm  Vin)

 high unity gain band width (ft) at low currents

 essentially unidirectional

Performance Gap b/n CMOS and Bi-polar :

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Combined advantages in BiCMOS Technology:

• BiCMOS technology some way combines the virtues of both CMOS and Bipolar technologies

• Design uses CMOS gates along with bipolar stage where driving of high capacitance loads is
required

• Resulting benefits of BiCMOS technology over solely CMOS or solely bipolar :

• Improved speed over purely-CMOS technology

• Lower power dissipation than purely-bipolar technology (simplifying packaging

and board requirements)

• Latchup immunity (Discussed later in course)

Advantages of Bi-CMOS :

 A known deficiency of MOS technology is its limited load driving capabilities (due to
limited current sourcing and sinking abilities of pMOS and nMOS transistors.

 Bipolar transistors have

 higher gain

 better noise characteristics

 better high frequency characteristics

 BiCMOS gates can be an efficient way of speeding up VLSI circuits.

 CMOS fabrication process can be extended for BiCMOS

 Example Applications

 CMOS - Logic

 BiCMOS - I/O and driver circuits

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 The production of npn Bipolar transistor with good performance char’s can be achieved, by
extending the standard n-well processing to include futher masks to add two additional layers.

1. the p+ base layer and

2. The n+ sub-collector .

Further advantages of BiCMOS Technology:

 High impedance CMOS transistors may be used for the input circuitry while the remaining
stages and output drivers are realised using bipolar transistors.

 In general, BiCMOS devices offer many advantages where high load current sinking and
sourcing is required. The high current gain of the NPN transistor greatly improves the output
drive capability of a conventional CMOS device.

 MOS speed depends on device parameters such as saturation current and capacitance.
These in turn depend on oxide thickness, substrate doping and channel length.

 Compared to CMOS, BiCMOS’s reduced dependence on capacitive load and the multiple
circuit and I/Os configurations possible greatly enhance design flexibility and can lead to
reduced cycle time (i.e., faster circuits).

 Bi-CMOS is inherently robust with respect to temperature and process variations, resulting
in less variability in final electrical parameters, resulting in higher yield.

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  Large circuits can impose severe performance penalties due to simultaneously switching
noise, internal clock skews and high nodal capacitances in critical paths – Bi-CMOS has
demonstrated superiority over CMOS in all of these factors.

 BiCMOS can take advantage of any advances in CMOS and/or bipolar technology, greatly
accelerating the learning curve normally associated with new technologies.

Disadvantages with BiCMOS technology:

 Main disadvantage : greater process complexity compared to CMOS

 Results in a 1.25 -> 1.4 times increase in die costs over conventional CMOS.

 Taking into account packaging costs, the total manufacturing costs of supplying a BiCMOS
chip ranges from 1.1-> 1.3 times that of CMOS.

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