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Cycle Test 3 Set 1

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19 views5 pages

Cycle Test 3 Set 1

Uploaded by

nithya
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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SRM INSTITUTE OF SCIENCE AND TECHNOLOGY

RAMAPURAM CAMPUS
DEPARTMENT OF EEE
18EEC203J - DIGITAL SYSTEM DESIGN
CYCLE TEST 3
YEAR/SEM - II/ III DATE:
Maximum marks – 50 DURATION: MIN

PART A (50*1 =50)


Answer All the MCQs

1. Table that is not a part of asynchronous analysis procedure is


a. Transition table b.State table
b. Flow Table d. Excitation Table

2. In asynchronous circuit the changes occur with the change of


a. Input b. Output c. Time d. Clock pulse

3. The present state and next states of asynchronous circuit are also called
a. Secondary variable b. Primary variable c. Excitation variable d. Short term memory

4. The race in which the state table depends on order is called


a. Critical b. Identical c. Non critical d. Defined

5. The complexity of asynchronous sequential circuit is involved in the timing problem of


a. Input b. Output c. Clock pulses d. Feedback path

6. Internal states and input values together are called


a. Full state b. Total state c. Internal stated. Output state

7. Memory elements in asynchronous circuits are


a. Unclocked flip flops b. Clocked flip-flops c. Clock pulses d. Latches

8. A ------------ is a semiconductor memory device used to store information, which is permanent in


nature
a. ROM b. RAM c. K map d. Table

9. The ROM is a
a. Magnetic circuit b. Sequential circuit c. Static circuit d. Combinational circuit

10. Which is not a removable drive?


a. Super disk b. Jaz c. Hard disk d. Drive

11. Since, Rom has the capability to read only the information, then also it has been designed, why?
a. For controlling purpose b. For booting purpose c. For loading purpose d. For erasing purpose

12. VLSI chip utilizes


a. CMOS b. BJT c. NMOS d. All the Above
13. Why antifuses are implemented in a PLD?
a. To protect from high voltage b. To increase memory
b. As a switching device d. To implement the programmes

14. How many 1024*1 RAM chips are required to construct a 1024*8 memory system
a. 2 b. 4 c. 6 d. 8

15. For programmable logic functions, which type of PLD is used?


a. CPLD b. PAL c. PLA d. SLD

16. PLA is used to implement


a. Simple sequential circuit b. complex combinational circuit
c. Simple combinational circuit d. Complex sequential circuit
17. The full form of VLSI is
a. Very Large scale integration b. Very Long scale integration
c. Very Least scale integration d. Very Large scale IC
18. In FPGA, vertical and horizontal directions are separated by
a. Flip flop b. Line c. Channel d. Strobe

19. PLA contain


a. AND and OR array b. NAND and OR array c. NOR and OR array d. NOT and OR array

20. How many 'D' flip flops will be required for designing the synchronous counter for the state diagram
shown below?

a. 2 b. 3 c. 5 d. 7
21. If the output of two-bit asynchronous binary up counter using T flip flops is '00' at reset condition,
then what output will be generated after the fourth negative clock edge?
a. 00 b. 01 c. 10 d. 11

22. Which flip flops serve to be the fundamental building blocks of counters?
a. S-R Flip flop b. J-K Flip Flop c. T Flip flop d. D Flip flop

23. In the below drawn schematic, what does an arrow between the circles indicate?
a. Present state b. Next state c. State transition d. Line diagram

24. What does the diode D3 represents in the equivalent circuit of Multiple Emitter Transistor shown
below?

a. Base to emitter junction b. Collector to base junction


c. Collector to emitter junction d. Emitter to emitter junction

25. How are the design specifications represented in the behavioral modeling style of VHDL?
a. Boolean equation b. Truth table c. Logical diagram d. State diagram

26. Dataflow style of architectural modeling is represented as a set of ___________ assignment


statements.
a. Sequential b. Concurrent c. Random d. Combinational

27. Which type of architectural modeling style describes the internal design details in the form of a set
representing the interconnected components?
a. Dataflow b. Behavioral c. Structural d. Mixed

28. Which among the following is the correct way of entity representation for the two input NAND gate
shown below?
a. NAND 5 entity is
port (A, B : input;
C: output);
NAND 5 end;
b. entity NAND5 is
port (A, B : in bit;
C: out bit);
end NAND 5;
c. Entity: NAND5
port(Inputs: A, B;
Output : C);
end;
d. entity : NAND5
port( inbit : A,B),
( outbit: C);
end.
29. Which mechanism allocates the binary value to the states in order to reduce the cost of the
combinational circuits?
a. State Reduction b. State Minimization c. State Assignment d. State Evaluation
30. Why the extent of propagation delay in is synchronous counter much lesser than that of asynchronous
counter?
a. Due to clocking of all flip flops at the same instant
b. Due to increase in number of states
c. Due to absence of connection between outputs of preceding flip flop and clock of next one
d. Due to absence of mode control operation

31. What does an entity specify in the VHDL program format?


a. List of all libraries associated with the design b. Code properties of VHDL
c. Input/output pins of the circuit d. The behaviour of circuit

32. The ability of HDL to describe the performance specification of a circuit is regarded as ____
a. Test case b. System case c. Mark bench d. Test bench

33. Which among the following memories utilizes the electrical voltage for erasing purposes?
a. PROM b. EAROM c. RAM d. CAM

34. Which type of unipolar logic family exhibits its usability for the applications requiring low power
consumption?
a. PMOS b. NMOS c. CMOS d. All of the above

35. Which among the bipolar logic families is specifically adopted for high speed applications?
a. Diode Transistor Logic (DTL) b. Transistor Transistor Logic (TTL)
c. Emitter Coupled Logic (ECL) d. Integrated Injection Logic (I2L)
36. The ripple counter is one kind of
a. sequential counter b. asynchronous counter c. synchronous counter d. up-down counter.

37. Three decade counters would have


a. 2 BCD counters b. 3 BCD counters c. 4 BCD counters d. 1 BCD counter

38. Registers giving response to pulse duration is called


a. Latch b. Gated latch c. Counter d. Flipflop

39. Circular shift register is called


a. SSI counter b. LSI counter c, Ring Counter d. Ripple counter

40. Binary ripple counter is made up of


a. T flip flop b. JK flip flop c. RS flip flop d. D flip flop

41. Recommended fan out of TTL gate is


a. 10 b. 4 c. 20 d. 50

42. Which of the following logic family has complementary outputs?


a. DTL b. TTL c. RTL d. ECL

43. RAM is also known as


a. RWM b.ROM c. EPROM d. EEPROM

44. Which of the following is the most widely employed logic family?
a. Emitter-coupled logic b. Transistor-transistor logic c. CMOS logic family d. NMOS logic

45. Schottky TTL logic family does not have which of the following features?
a. Good fan-in b. Good fan-out c. High speed capability d. High propagation delay

46. Among the VHDL features, which language statements are executed at the same time in parallel flow
a. Concurrent b. Sequential c. Net-list d. Test-bench
47. Complete description of the circuit to be designed is given in
a. Architecture b. Entity c. Library d. Configurations

48. For describing circuits like flip flops _____________ statement is used
a. Always b. Entity c. Component d. Initial

49. The minimum Which of the following is the basic building block of design
a. Architecture b. Entity c. Library d. Configurations

50. number of flipflop required to construct mod 64 ripple counter is


a. 4 b. 6 c. 16 d. 64

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