DESIGN AND ANALYSIS OF 8-BIT CARRY

LOOK AHEAD ADDER USING GATE

DIFFUSION INPUT LOGIC

A project report submitted in partial fulfilment of the requirement

for the award of degree of

BACHELOR OF TECHNOLOGY
In

ELECTRONICS AND COMMUNICATION ENGINEERING

Submitted by
M.V.CHAITANYA (18341A0487)
P.SUDHEER (18341A04B7)

M.VIJAY KRISHNA (18341A04A2)

P. BHAGYA RAJ (18341A04B2)

Under the esteemed guidance of

Dr. V.KANNAN

Professor, Dept. of ECE

GMR Institute of Technology

An Autonomous Institute Affiliated to JNTUK, Kakinada
(Accredited by NBA, NAAC with ‘A’ Grade & ISO 9001:2008 Certified Institution)

GMR Nagar, Rajam – 532 127,

Andhra Pradesh, India
MAY 2022
 Department of Electronics and Communication Engineering
CERTIFICATE
This is to certify that the thesis entitled DESIGN AND ANALYSIS OF 8-BIT CARRY LOOK

AHEAD ADDER USING GDI LOGIC submitted by M.V.CHAITANYA

(18341A0487),P.SUDHEER (18341A04B7), P.BHAGYA RAJ(18345A04B2), M. VIJAY

KRISHNA (18341A04A2) has been carried out in partial fulfilment ofthe requirement for the

award of degree of Bachelor of Technology in Electronics and Communication Engineering

of GMRIT, Rajam affiliated to JNTUK, KAKINADA is a record of bonafide work carried out

by them under my guidance & supervision. The results embodied in this report have not been

submitted to any other University or Institute for the awardof any degree.

Signature of Supervisor Signature of HOD

Dr. V.Kannan Dr. V. Jagan Naveen
Professor Professor & Head
Department of ECE Department of ECE
GMRIT, Rajam. GMRIT, Rajam.

The report is submitted for the viva-voice examination held on ………………..

Signature of Internal Examiner Signature of External Examiner

 ACKNOWLEDGEMENT
It gives us an immense pleasure to express deep sense of gratitude to my guide
Dr. V. Kannan , Professor, Department of Electronics and Communication Engineering of whole
hearted and invaluable guidance throughout the project work. Without his sustained and sincere
effort, this project work would not have taken this shape. He encouraged and helped us to
overcome various difficulties that we have faced at various stages of our project work.

We would like to sincerely thank our Head of the department Dr. V. Jagan Naveen, for providing
all the necessary facilities that led to the successful completion of our project work.

We would like to take this opportunity to thank our beloved Principal Dr. C. L. V. R. S. V Prasad,
for providing a great support to us in completing our project and for giving us the opportunity of
doing the project work.

We would like to take this opportunity to thank our beloved Director Education Dr. J. Girish, for
providing all the necessary facilities and a great support to us in completing the project work.

We would like to thank all the faculty members and the non-teaching staff of the Department of
Electronics and Communication Engineering for their direct or indirect support for helping us in
completion of this project work.

Finally, we would like to thank all of our friends and family members for their continuous help
and encouragement.

M.V.Chaitanya (18341A0487)
P,Sudheer (18341A04B7)
M. Vijay Krishna (18341A04A2)
P.Bhagya Raj (18341A04B2)
 ABSTRACT

In VLSI, Hundreds of thousands of transistors are integrated to produce a chip (or microchip).The
technology for designing CMOS VLSI have been evolving in the current world. By optimising the
leakage power, the propagation delay consumption in the circuits are increased. The transistor
level design is implemented. The GDI is established to address these major issues. Full adders are
used in arithmetic circuits, microprocessors, and other electronic devices. Whether it's digital
signal processing, image or video processing, microcontrollers and other data processing units are
used for the processing. In this project work, an 8-bit Carry Look-ahead Adder is implemented
and compared. Two sorts of architectures considered are Transmission Gate logic and Gate
Diffusion Input logic. In 180nm technology, Tanner Tools v15.23 is used to design and simulate
adders. The two adders' performance parameters, such as power consumption and propagation
delay, are compared at different input supplies and operating frequencies. In terms of power
consumption, transistor count, latency, and power delay product, an 8-bit CLA circuit using GDI
outperforms a TG logic-based solution (PDP).

KEYWORDS: TRANSMISSION GATE (TG), CARRY LOOK AHEAD ADDER (CLA),

RIPPLE CARRY ADDER (RCA), GATE DIFFUSION INPUT (GDI).

i
 TABLE OF CONTENTS

CONTENT NAME PAGE NO

ACKNOWLEDGEMENT

ABSTRACT i

LIST OF TABLES x

LIST OF FIGURES vi

LIST OF SYMBOLS & ABBREVIATIONS xi

1.INTRODUCTION 1
1
1.1 INTRODUCTION TO VLSI

1.1.1 Factors affected in the VLSI process 2

1.1.2 Advantages of VLSI 2

1.1.3 VLSI and its Applications

2

1.2 BASIC MOS TRANSISTORS USING TO DESIGN A LOGIC

1.2.1 Nmos
2
1.2.2 Pmos 3
1.2.3 Cmos 4

1.3 DIFFERENT TYPES OF LOGICS

4
1.3.1 Adiabatic logic 4

1.3.2 Transmission gate logic 5

6
1.3.3 Feedback switch logic

ii
 1.3.4 Gate diffusion input logic 7

1.4 ARTHIMETIC LOGIC UNIT 8

1.4.1 Adder 8
1.4.2 Half adder 9
1.4.3 Full adder 10
1.5 ADDER ARCHITECTURE 11
1.5.1 Ripple carry adder 11

1.6 CARRY LOOK AHEAD ADDER 13

2.0 LITERATURE SURVEY

14
3.0 METHODOLGY 15

3.1 FULL ADDER USING CONVENTIONAL CMOS LOGIC

15
SCHEMATIC

3.2 FULL ADDER USING ADIABATIC LOGIC SCHEMATIC 19

3.3 FULL ADDER USING TRANSMISSION GATE 20
SCHEMATIC
21
3.4 FULL ADDER USING GATE DIFFUSION INPUT LOGIC
SCHEMATIC

3.5 CARRY LOOK AHEAD ADDER(CLA) 22

3.5.1 SCHEMATIC FOR CARRY PROPAGATION IN

22
CLA USING GDI

3.5.2 SCHEMATIC FOR CARRY GENERATION IN 23

CLA USING GDI

3.5.3 SCHEMATIC FOR 8-BIT CLA ADDER USING 24

GDI LOGIC

iii
 3.6 RIPPLE CARRY ADDER
25
3.6.1 SCHEMATIC FOR 8-BIT RIPPLE CARRY 26
ADDER USING GDI LOGIC
28
4.0 SOFTWARE DISCRIPTION

4.1 INTRODUCTION TO TANNER TOOL 28

4.2 RULES AND GUIDELINES TO USE TANNER 28

4.2.1 Setup your directory structure & download libraries

28
4.2.2 Start a new design & setup libraries 28
31
4.2.3 Enter the schematic to simulate the iv behaviour of
an NMOS transistor

4.2.4 Setup the parameters that will be used for DC sweep 36

analysis
36
4.2.5 Setup the spice DC sweep analysis

4.2.6 Design and simulation

37
4.3 CREATE A NEW DESIGN, CONFIGURE LIBRARIES
AND CONFIGURE SIMULATION 38
39
4.3.1 Create the inverter

4.3.2 Create the top schematic for the inverter to be tested 42

4.3.3 Simulate the design

43
4.4 STEPS TO USE MICROWIND 44
4.5 STEPS TO USE DIGITAL SCHEMATIC 45

iv
5.0 RESULTS AND DISCUSSIONS
46
6.0 CONCLUSION AND FUTURE SCOPE 59

REFERENCES 60

v
FIGURE NO TITLE PAGE NO

1.1 Nmos
3
1.2 Pmos 3
4
1.3 Cmos
1.4 Operation of adiabatic logic 5
5
1.5 Transmission Gate
1.6 Feedback Switch Logic 6
7
1.7 Basic GDI Cell
1.8 Logic Gates 8
8
1.9 Adder
1.10 Half adder using logic gates 9
10
1.12 Full adder using logic gate
1.14 8-Bit Ripple Carry Adder 11
1.15 Carry Propagation and Generation, Sum, Carry
13
1.16 8-Bit Carry Look Ahead Adder 13
18
3.1 Schematic of full adder using conventional CMOS
logic
3.2 Schematic of full adder using adiabatic logic 19
3.3 Schematic of full adder using transmission gate 20
logic
3.4 Schematic of full adder using gate diffusion input 21
logic

vi
3.5 Schematic for carry propagation in 23
CLA
3.6 Schematic for carry generation in CLA 23
3.7
Schematic for 8-bit CLA using GDI logic 24
3.8
Schematic of 8-bit Ripple Carry Adder
27
using GDI logic
4.1 Libraries 29
30
4.2 Setup SPICE Simulation of Cell Top 31
4.3 Simulate the IV behaviour of an NMOS Transistor
32
Schematic to Simulate the IV behaviour of an
4.4
NMOS Transistor

4.5 Create a DC source for VDS 33

4.6 VDS Source is the name of the file. "VDS param" - 34
V

4.7 Net Label icon

34
4.8 SPICE Commands
35

4.9 The parameters that will be used for the DC sweep 37

analysis

4.10 Create the Inverter

39
TOP level schematic with a Netlist 40
4.11
Create the Inverter Symbol 41
4.12
4.13 Create the TOP schematic for the inverter to be
42
tested

vii
 Simulate the Design 43
4.14
5.1 46
Layout design of conventional CMOS full adder

5.2 47
Simulation results of conventional CMOS
full adder using Microwind
5.3 48
Simulation of results of conventional
CMOS full adder using tanner 48
5.4
Layout design of adiabatic full adder

5.5 49
Simulation results of adiabatic full adder
using microwind 50
5.6
Simulation results of adiabatic full
Adder using tanner
5.7 50
Layout design of Transmission Gate full
adder
5.8
Simulation results of transmission gate 51
adder using Microwind
52
5.9 Simulation results of transmission gate
full adder using tanner
Layout design of GDI full adder 52
5.10

5.11 Simulation results of GDI full adder using 53

Microwind
5.12 Simulation results of GDI full adder using 54
Tanner
5.13 Layout design of 8-bit CLA adder using 54
GDI logic
5.14 Simulation results of 8-bit CLA adder 55
using GDI logic
5.15 Propagation delay results of 8-bit CLA 56
adder using GDI
5.16 Layout design of 8-bit Ripple Carry adder 56

viii
5.17 Simulation results of 8-bit RCA adder 57
using GDI logic
5.18 Propagation delay results of 8-bit RCA 58
adder using GDI

ix
 LIST OF TABLES

Table .No. TITLE Page.No

1.1 Truth table for Half Adder 9
1.2 Truth table for Full Adder 10
5.1 Comparison of Area and Power and Time delay 46
Of Full adders
5.2 Comparison of Area and Power and Propagation delay 58
Of RCA and CLA

X
 LIST OF SYMBOLS & ABBREVIATIONS

VLSI Very Large Scale Integration

IC Integrated Circuit
CPU Control Processing Unit
RAM Random Access Memory

ROM Read Only Memory

CMOS Complementary Metallic Oxide Semiconductor
FPGA Fine-grained
CGRA Coarse-grained

SDM Sparse Distributed Memory

CM Compute Memory
HBD Hierarchical Binary Decision
PMOS P-channel Metal-Oxide Semiconductor
NMOS N-channel Metal-Oxide Semiconductor
FET Field Effect Transistors
DFW Design Frame Work
ECAD Electrical Computer Aided Design

xi
 CHAPTER-1
INTRODUCTION

1.1 Introduction to VLSI

The term "Very Large Scale Integration" refers to a large-scale integration
project. Hundreds of thousands of transistors or devices are merged into a single
integrated circuit in VLSI (IC). It all started in the 1970s with the development of
complicated semiconductor and communication technologies. A VLSI device is used
as the microprocessor. Prior to the emergence of VLSI technology, most ICs could
only perform a restricted range of functions. Electronic circuits include the CPU,
RAM, and ROM. IC designers can use VLSI to merge all of these functions into a
single chip. The majority of digital VLSI circuits are CMOS.
1.1.1Factors affected in the VLSI process

I. Circuit Delays: Delays in signal propagation via gates and wire, even for
areas a few micro metres wide, are a major issue in large intricate circuits
running at very high frequencies. Because the operation speed is so fast, the
delays build up quickly.
II. Power: Higher operation frequencies lead to higher power consumption.
This accelerates the burning of batteries and increases heat dissipation. Heat
poses a serious threat to the circuit's stability, especially because surface
areas have shrunk.
III. Layout: Circuit component layout is a task that is similar to all fields of
electronics. What makes our scenario unique is that there are numerous
options for doing so: multiple layers of different materials on the same
silicon, varied configurations of smaller pieces for the same component, and
so on. There is a trade-off in a circuit between power dissipation and speed.
When we try to improve one, the other suffers. The choice between the two
is determined by the way we choose the layout of the circuit components.
Layout can also affect the fabrication of VLSI chips, making it either easy or
difficult to implement the components on the silicon

1
 1.1.2 Advantages of VLSI
▪ Increases the Operating speed of circuits.
▪ Higher Reliability

▪ Reduces the Size of Circuits.

▪ Reduces the effective cost of the devices.
▪ Requires less power than discrete components.

1.1.3 VLSI and its Applications

▪ Very large-scale integration is the process of integrating or

embedding hundreds of thousands of transistors on a single silicon
semiconductor microchip (VLSI).

▪ VLSI is a widely utilized technique for the development of microchip

processors, integrated circuits (ICs), and components.

▪ This gave birth to the invention of technology which can fabricate

more number of components onto a single chip.

▪ VLSI chips are used in voice and data communication, networks, DSP
computers, commercial electronics, automobiles, medicine, and many
more disciplines of engineering.

1.2 BASICS MOS TRANSISTORS USED TO DESIGN A LOGIC

1.2.1 NMOS:

A type of MOSFET is the NMOS (NMOSFET). An NMOS transistor features a p-type

substrate and an n-type source and drain. When a voltage is applied to the gate, it drives holes
in the body (p-type substrate) away from it. An n-type channel arises between the source and
the drain, allowing current to flow from the source to the drain through this induced n-type
channel.

2
 Figure 1.1 NMOS

NMOS logic is used to describe logic gates and other digital devices that use NMOSs. A NMOS
has three operational modes: cut off, triode, and saturation. NMOS logic is simple to design
and produce. When the circuit is idle, however, NMOS logic gates waste static power because
DC current passes through the logic gate when the output is low.

1.2.2 PMOS:

PMOS (PMOSFET) is a kind of MOSFET. A PMOS transistor is made up of a p-type source

and drain, as well as an n-type substrate. When a positive voltage is applied between source
and gate, a p-type channel with opposite dissociation is formed between source and drain
(negative voltage between gate and source). Current flows from the source to the drain through
holes in a p-type induced channel.

Figure 1.2 PMOS

A PMOS will not conduct if the gate voltage is too high, but it will conduct if the gate voltage
is too low. PMOS logic should be used in logic gates and other digital devices that use PMOS.
PMOS technology is low-cost and offers strong interference resistance.

3
1.2.3 CMOS:

A CMOS integrated circuit (Complementary Metal-Oxide-Semiconductor) is a type of

electrical device. Microprocessors, microcontrollers, static RAM, and other digital logic
circuits all utilise CMOS technology.

Figure 1.3 CMOS

CMOS technology is also employed in image sensors (CMOS sensor), data converters, and
highly integrated transceivers for a variety of communication applications.

1.3 DIFFERENT TYPES OF LOGIC:

1.3.1 Adiabatic logic:

A typical low-power circuit design approach is adiabatic logic (AL). AL minimize energy by
charging the output slowly and recover the charge stored in the load capacitors on the output .
Figure A depicts the basic operation of adiabatic logic.

In adiabatic logic, a full cycle's energy consumption can be expressed using an equation.

2RtC
𝐸𝑜𝑣𝑒𝑟𝑎𝑙𝑙 = T∗C∗𝑉 2 (1.1)
𝑑𝑑

Where Vdd is the entire swing of the power clock, T is the capacitor charging period, while Rt
is the channel resistance. We discovered that if T >2RtC, AL consumes less energy than
standard CMOS by observing equation 1

4
 Figure 1.4
Operation of adiabatic logic

1.3.2 Transmission gate logic:

A CMOS transmission gate can be made using a parallel combination of NMOS and PMOS
transistors with complementary gate signals to generate a TRANSMISSION GATE LOGIC.
Transistors are known as transmission gates because they can convey information from one
circuit to another. It's a relay with the ability to send and receive data in both directions. It's a
CMOS switch with a strong 1 but a weak 0 signal from the PMOS transistor and a strong 0 but
a weak 1 signal from the NMOS transistor. In this circuit, both PMOS and NMOS transistors
are active at the same time. The source is connected to the input of a Transmission Gate, while
the drain is connected to the output.

Figure 1.5 Transmission Gate

5
The graphic depicts the control signals A and Abar, as well as in as an input signal and out as
an output signal. A major advantage of the CMOS transmission gate over the NMOS
transmission gate is that the input signal can be transferred to the output without being
dampened by the threshold voltage.

1.3.3 Feedback Switch Logic:

The FSL differential circuit family is a clockless differential circuit family that uses a single
gate to generate both the output and its inverse. Figure 1 depicts two different FSL topologies.
Figure 1 shows the better of the two FSL structures (a). Because complimentary networks can
share transistors, the structure in Fig. 1(b) can be useful for FSL tree implementations. Like
dynamic logic families, FSL uses NMOS networks to implement the logic function and its
complement. The output node is also pulled up by two cross-linked PMOS transistors. One of
these pull-ups, however, is a poor keeper, while the other is powerful enough to drive the
production. It generates a lot of drive current during a low to high OUT-BAR transition but has
no influence on a high to low transition since the output feedback switches it off when it's not
needed. Based on the current output state, the feed back operates as a switch to determine which
of the two pull down networks should be employed to provide gate functionality.

Figure 1.6 Feedback Switch Logic

The effective FSL gate delay is always based on two stages when the signal travels through
three serial stages in the worst case, which are Y, Y-BAR, and the output inverter stage. FSL
combines the speed of dynamic logic with the activity-dependent switching behavior of static
logic without requiring a clock connection. However, because the gate's load is driven from a
single side, FSL is slower than dynamic logic.

6
1.3.4 Gate Diffusion Input Logic:

The most modern technology for building VLSI Circuits is Gate Diffusion Input. GDI is
regarded to be more efficient than other design approaches such as CMOs and PTL. The speed
with which a digital circuit produces output when given an input determines its performance.
The most extensively utilized technology for manufacturing digital circuits is CMOS.
Following the advent of CMOs logic, the necessity to optimize circuits in terms of speed grew.
Pass Transistor Logic (PTL), which uses a less number of gates to perform an operation, was
one method considered.

One of them is the Transmission Gate (TG), which is made up of NMOs and PMOs transistors
wired in parallel. The GDI cell is a form of PTL that looks like CMOS but has a different
supply for the input terminals.

The following are the key benefits of PTL over traditional CMOS designs:

1) A lower transistor count means less power loss and a quicker response time.

2) Because there are fewer transistors, there is a smaller area and less interconnect effects.

Reduced circuit speed for low-power operations and increased static power dissipation are two
main downsides of PTL technologies. GDI is a technique for quickly building low-power
circuits using only a few transistors. In terms of design, the GDI cell is similar to a CMOS
inverter. The NMOS source of a CMOS inverter is grounded, while the PMOS source is linked
to Vdd . However , in a GDI cell , this is not necessarily in the case.

Figure 1.7 Basic GDI Cell

7
1.3.4.1 IMPLEMENTATION OF LOGIC GATES USING GDI :

Figure 1.8 Logic Gates

1.4 Arithmetic Logic Unit:

It is the digital computer's functional predecessor that performs arithmetic and logic operations
on machine words that represent operands. It's very prevalent in the central processing unit. It
is the functional forerunner of the digital computer, performing arithmetic and logic operations
on machine words that represent operands. The central processing unit is a popular place to
find it.

1.4.1 Adder: A calculator that adds two binary values together is known as an adder. Many
computers and other types of processors use adders in their arithmetic logic units (ALUs).

Figure 1.9 Adder

8
1.4.2 Half adder:

A digital electronic circuit that performs binary number addition is referred to as a "half adder."
The number system employed is the only difference in the addition operation. In the binary
numbering system, only 0 and 1 exist. The number's weight is entirely determined by the binary
digits' placements. 1 is viewed as the greatest digit, whereas 0 is treated as the smallest.

SUM=A XOR B (1.2)

CARRY=A AND B (1.3)

Figure 1.10 Half Adder using logic gates

Table 1.1 Truth Table for half adder

INPUT OUTPUT

A B SUM CARRY

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

9
1.4.3 Full Adder:

When two binary digits are added together, the total is generated. The MSB bit is referred to
as carry if the output consists of two digits. This is handled as the third bit in the addition
method. The Full Adder is a 'combinational circuit' that can add three input bits or two inputs
plus carry-in from the previous operation.

SUM = A XOR B XOR C (1.4)

CARRY = AB+BC+CA (1.5)

Figure 1.12 Full Adder using logic gate

Table 1.2 Truth Table of FULL ADDER

INPUT OUTPUT

A B Cin SUM CARRRY

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

10
 1.5 ADDER ARCHITECTURE:

Different adder architectures are used to balance criteria like as power, area, speed, and
complexity. Carry look-ahead (CLA) adders, carry-skip adders, carry-select adders,
conditional sum adders, and combinations of these structures are examples of high-speed adder
topologies. Because the carry delay can be reduced by computing each stage in parallel, high-
speed adders based on the CLA principle are still commonly employed.

1.5.1 RIPPLE CARRY ADDER:

A ripple carry adder is a digital combination circuit that adds two binary values at the same
time. It's made up of a series of full adders, with each full adder's output carry coupled to the
following full adder's input carry. A chain of n full adders or a chain of one half adder and (n-
1) full adders is required for adding n-bit values.

The input carry to the least significant place is fixed at '0' in the former scenario. An n-bit RCA
is created by connecting n full adder (FA) circuits. Let's call the two 8-bit inputs A(Augend)
and B(Addend).

Figure1.14 8-BIT RIPPLE CARRY ADDER

11
The least significant input carry C0 must be 0 in this situation. Ci+1 at a significant position
equals the total output carry of the adder. This value is fed into the full adder's input carry,
which moves the bits one significant place to the left. The total bits are generated in this
manner, starting from the rightmost location, and are available as soon as the previous carry
bit is formed.

When two binary numbers are added in parallel, all of the input variables' bits are available for
computation at the same time. Any combinational circuit's output must pass through the gates
before it can be accessed at the output terminals. The total propagation time is the same as the
average gate propagation delay. The time it takes the carry to propagate is the longest
propagation delay period in adder. Because adding bits in RCA takes a long time, the CLA
(carry look ahead adder) was invented to help.

1.6 CARRY LOOK AHEAD ADDER:

The time it takes to propagate the carry is the limiting element for the ripple-carry adder. This
difficulty is solved by the carry look-ahead adder, which calculates the carry signals in advance
based on the input signals. As a result, the time it takes to propagate a carry is lowered. The
ideas of generating and distributing carries are used in carry-lookahead reasoning. Although
it's natural to conceive of producing and propagating in terms of binary addition when thinking
of a carry-lookahead adder, the principles can be used more broadly.

We must alter the Boolean statement dealing with the complete adder to understand how the
carry look-ahead adder works. In a full-adder, propagate P and create G is written as:

Spread the word Ai + Bi = Pi (1.6)

Carry the Generation Gi= Ai.Bi (1.7)
Both propagate and produce signals are valid after a single gate delay since they are only
dependent on the input bits. The following are the modified output sum and carryout
expressions:

Si = Pi Ci Ci+1= Gi + PiCi (1.8)

These equations show that a carry signal will be created in two scenarios:

1) The result is 1 if both bits Ai and Bi are 1.

2) If both Ai and Bi are 1, and the carry-in Ci is 1.

12
Figure 1.15 Carry Propagation and Generation , Sum , Carry

Figure 1.16 8 Bit Carry Look Ahead Adder

13
 CHAPTER-2

LITERATURE REVIEW

This chapter narrates the various literatures referred for performing this project. The
literatures reviewed are as follows.
Prerna, G.S. Taki (2017)They demonstrated a ripple carry adder with CMOS output
wired logic based on majority gates. Digital computation frequently employs a high
degree of arithmetic operations such as addition and subtraction. The binary addition
is the most commonly performed operation, and it is a vital component of the
microprocessor. Then we used CMOS output connected logic to replace these
threshold blocks. CMOS output wired logic joins the outputs of each CMOS inverter
to create a wired logic, which helps reduce transistor count. The ripple carry adder is
a logic circuit in which the preceding bit's carry output is sent into the following
complete adder block. Using CMOS output wired logic based threshold logic, we
created a four bit ripple carry adder. Each inverter's PMOS and NMOS transistor
widths are determined by the weight (W) of each input, and the threshold is achieved
by altering the threshold of the last inverter. To acquire weight values other than one,
alter the diameter of the PMOS transistor. As a result, just two inverters, the
fundamental input inverters and the output inverter, are sized during the design phase.
To add an N-bit number, multiple complete adder circuits can be cascaded in parallel.
In an N-bit parallel adder, there must be N full adder circuits. The carry-out of each
full adder is equal to the carry-in of the next most significant full adder in a ripple
carry adder. It's called a ripple carry adder because each carry bit ripples into the next
stage. In a ripple carry adder, the sum and carry out bits of any half adder stage are
not valid until that stage's carry in occurs. In a normal CMOS ripple carry adder, the
total transistor count is 112, however in the recommended ripple carry adder, the total
transistor count is 88.

Shoba Mohan (2018)presented their work on an 8-bit Gate Diffusion Input (GDI)
logic Ripple Carry Adder (RCA). GDI is a low-power design technique that allows
basic GDI cells to be used to create digital logic functions. XOR implementation
using GDI logic is simple when compared to typical logical designs such as CMOS,

14
PTL, and TFA because it only requires four transistors. GDI logic allows the entire
adder design to be accomplished with only 10T. Because the supply rails
(VDD/GND) are not used directly throughout the entire adder architecture, the short
circuit power consumption can be reduced. In a GDI-based architecture, a single bit
adder requires 10 transistors, whereas in a CMOS-based design, the same operation
requires 28 transistors. PTL performs poorly in terms of delay and power
consumption while having the same amount of transistors as GDI. In terms of
transistor count and latency, the TFA-based design is a good compromise between
CMOS and PTL, however it fails in power consumption. When connected in cascaded
stages, TFA design produces series resistance, which can increase latency. The GDI-
based adder has the lowest PDP value among the simulated designs. As a result, it'd
be a fantastic battery-powered application.

Malipatil Somashekhar (2020)their work on Area Optimization of CMOS Full Adder

Design Using xor GDI Approach allowed With only two transistors, they were able
to perform a wide range of complex logic functions. This method is ideal for creating
low-power, quick circuits with fewer transistors. With The demand for long-lasting
digital devices is increasing, as is the demand for low-power digital gadgets.
Designing such digital devices to fulfil the requirements of the current technological
breakthroughs has become a major priority for designers, as these devices usually
include phones, laptops, and sensor nodes. When designing an integrated circuit, area
and power dissipation are critical considerations. The Vth of transistors drops as
technology develops from m to nm, causing sub-threshold leakage current to climb
exponentially. The XOR gate is made up of three transistors, while the CMOS
complete adder is made up of two 3T XOR and one 2T Mux. The entire adder is
designed in this work using 8 transistors, and voltage scaling is achieved by lowering
the supply voltage. This suggested full adder has a total area of 144m2 and a power
consumption of 4.604W.

Sengupta Rimi (2018) presented their work on a whole adder block based on
threshold logic. Then we used CMOS output connected logic to replace these
threshold blocks. CMOS output wired logic joins the outputs of each CMOS inverter
to create a wired logic, which helps reduce transistor count. Each inverter's PMOS
and NMOS transistor widths are determined by the weight (W) of each input, and the

15
threshold is achieved by altering the threshold of the last inverter. The width of the
PMOS transistor can be changed to obtain weight values other than 1 1. As a result,
just two inverters, the fundamental input inverters and the output inverter, are sized
during the design phase. TL gate1 and TL gate2 are the two threshold gates employed
here. The carry output is provided by TL gate1, which is a majority gate. Four
inverters make up this Majority gate. Three of them are ganged, and the carry output
is obtained by connecting the fourth inverter to the ganged output. As seen in figure
6, the complete adder's inputs (A, B, and Cin) are applied to three inverters (INV1,
INV2, and INV3). All PMOS and NMOS transistors have their W/L ratios modified
so that their resistances are the same (R). As a result, the ganged part's equivalent
circuit can be thought of as a voltage divider network. The last output inverter's
threshold voltage is set between Vdd/3 and 2(Vdd/3). The last inverter provides the
carry output. Another inverter captures the inverter's output and inverts it (INV5).
Finally, this serves as a fourth input for the TL gate 2, which produces a sum output.
This four-bit ripple carry adder circuit uses mostly gate and output wired CMOS
logic. The delay created by the combination of these logics is less than previous
designs at 130nm technology, and the transistor count is likewise less than the
standard design.

Ravi Kumar Korra (2017) proposed their work on high power consumption raises IC
temperature, which has a direct impact on battery life in portable devices, according
to their research. In COMS VLSI circuits, there are three types of power consumption:
static power consumption, which is caused by unwanted leakage current when the
transistor is in the Off state, dynamic power consumption, which is caused by
parasitic component switching, and current fluctuating from VDD to VSS, which
causes short-circuited power consumption. The GDI technique uses less silicon area
than other methods because it has fewer transistors, The node capacitance is reduced
because the area is smaller [12]. As a result, the GDI gate's operating speed is high,
demonstrating that the GDI logic style is an efficient design strategy. The bulk
terminals of NMOS and PMOS should be linked to their diffusion to reduce the bulk
effect, whereas the body effect is the variation in threshold produced by changes in
VSB. When the threshold voltage is disconnected from a source, the body effect is
shown. The area analysis reveals that the suggested work's transistor count is
significantly lower than previous efforts.

16
Omnia Al. Badry (2018)presented their work on a 1-bit full adder circuit that uses
full-swing GDI to decrease power consumption, latency, and area while achieving
full-swing output. In fact, this approach has been proposed for manufacturing in SOI
and twin-well CMOS technologies. In comparison to CMOS, PTL, and TG methods,
it also provides an effective solution to develop fast, low-power designs with fewer
transistors. With only two transistors, numerous complicated functions can be
designed. This logic type has several drawbacks, such as lower output voltage swing
due to threshold dips from VDD or GND by threshold voltage drop (Vth), As the
threshold drops, performance suffers and short circuit power rises. In comparison to
standard GDI logic, this logic is compatible for implementation in a regular CMOS
process and provides improvements in output, power, and power delay product. While
the threshold drop problem has not been fully rectified, the production has continued
to deteriorate. Morgenshtin presented a new GDI technology called Complete Swing
(FS), which only utilises a swing restoration transistor (SR) to offer full swing
operation for F1 and F2 functions. Any logical function can be realized with either
F1 or F2 gates, or a mix of both. Although this method uses more transistors than
classic GDI, it is more efficient. It uses fewer transistors and provides full swing
output than CMOS logic, low power, minimal delay, and a short circuit space.

17
 CHAPTER-3
METHODOLOGY
This chapter narrates the schematics of FULL ADDER using different logics like
CONVENTIONAL CMOS LOGIC , TRANSMISSION LOGIC , ADIABATIC
LOGIC, GATE DIFFUSION INPUT(GDI) LOGIC, Carry Generation for CARRY
LOOK AHEAD ADDER using GDI logic, Carry Propagation for CARRY LOOK
AHEAD ADDER using GDI logic, 8-CARRY LOOK AHEAD ADDER using GDI
logic, The paper considers an 8-BIT RIPPLE CARRY ADDER with GDI logic and
ADDERS architecture. They are explained as follows.

3.1 FULL ADDER USING CONVENTIONAL CMOS LOGIC SCHEMATIC

Figure 3.1 Schematic of Full adder using Conventional CMOS logic

Using a complete adder The circuit is created using 28 transistors with standard
CMOS logic. In classic CMOS implementation, the two functional blocks are pull-
up and pull-down. It looks like a Mirror full adder because the pull-up functional
block is constructed with p-channel n-channel MOS transistors are used to implement

18
MOS transistors and the pull-down functional block. This is an alternate
implementation of the full adder's generate/propagate/delete function. Conventional
CMOS full adder has high noise margin. Conventional CMOS logic is stable at low
voltages and it has weak output driving capability. The schematic of Conventional
CMOS full adder consists of inputs A,B,C and output are sum “S” and carry “ Ca”.

S=A XOR B XOR C (3.1)

Ca=A.B+B.C+C.A (3.2)

3.2 FULL ADDER USING ADIABATIC LOGIC SCHEMATIC

Figure 3.2 Schematic of Full adder using Adiabatic logic

To implement the whole adder utilizing adiabatic logic, 28 transistors are used.
Adiabatic switching logic is utilized to reduce energy consumption during charging
and discharging. The adiabatic process is characterized by a steady current is

19
employed to charge or discharge the nodes. The circuit is charged with AC electricity
during an adiabatic phase, then discharged to recover the charge. The two types of
adiabatic logic families are fully adiabatic and moderately adiabatic logic families. In
fully adiabatic circuits, all of the charges stored on the load capacitor are recovered
and transferred back to the power supply. As a result, fully adiabatic circuits are more
complex and slower than partial adiabatic circuits. The inputs of an adiabatic full
adder are A,B,C, and the outputs are sum "S" and carry " Ca."

S=A XOR B XOR C (3.3)

Ca=A.B+B.C+C.A (3.4)

3.3 FULL ADDER USING TRANSMISSION GATE LOGIC SCHEMATIC

Figure 3.3 Schematic of Full adder using Transmission Gate Logic

Twenty transistors are used to make the entire adder using Transmission gate logic.
The transmission gate is made up of two MOSFETs, one n-channel for accurate logic
zero transmission and the other p-channel for correct logic one transmission.
Transmission gate logic is similar to pass transistor logic, only it uses both NMOS
and PMOS transistors in parallel, whereas pass transistor logic only uses one kind.
Transmission gate logic is based on adiabatic logic and is made up of two functional

20
blocks, F and F complement, that are powered by a single clock. Functional blocks
can accept both simple and complex inputs, which are implemented via transmission
logic. Additional buffers are required when using transmission logic. And there is less
of a delay. Transmission gate logic's parasitic capacitance grows as the number of
internal nodes grows. The inputs of a transmission gate full adder are A,B,Cin, and
the outputs are sum "S" and carry " C."

S=A XOR B XOR Cin (3.5)

C=A.B+B.Cin+Cin.A (3.6)

3.4 FULL ADDER USING GATE DIFFUSION INPUT LOGIC SCHEMATIC

Figure 3.4 Schematic of Full adder using Gate Diffusion Input(GDI) Logic

To create the full adder utilizing Transmission gate logic, 20 transistors are used. The
logic in GDI is essentially identical to that in CMOS. In CMOS logic, the source of
PMOS is connected to VDD, while the source of NMOS is grounded. By using GDI
logic, reduce the transistor count of complex circuits which are implemented using
logics other than GDI . While keeping a low level of logic complexity, this GDI logic
decreases the delay, size, and power consumption of digital circuits. The GDI logic

21
 full adder has inputs A0,B0, and input carry is "0," with sum "S0" and carry " C0" as
outputs.

3.5 CARRY LOOK AHEAD ADDER

A carry-lookahead adder, often known as a fast adder, is a form of digital logic adder. By
reducing the time it takes to determine carry bits, a carry-lookahead adder improves
performance. The working of carry look ahead adder is The carry-in of any stage full adder
is independent of the carry bits created during intermediate stages, according to the
principle. In CLA adder, any stage full adder's carry-in is solely determined by the
following two parameters, they are: bits that were introduced in previous stages and in the
beginning, carry-in was provided. The CLA adder creates carry signals in parallel for
multiple stages. Time complexity reduces from O(n) to O(1).Hardware complexity
increases rapidly with n bits. In CLA adder,

Advantage of CLA adder

A carry look ahead adder has the following advantages:
1. It simultaneously builds the carry-in for each full adder.
2.It reduces the propagation delay.

Disadvantage of CLA adder

The disadvantages of utilising a carry look ahead adder are as follows:
1. It necessitates complex hardware, which is more expensive.
2. It becomes more difficult as the number of bits increases.

3.5.1 SCHEMATIC FOR CARRY PROPAGATION IN CLA USING GDI

In a CLA, If all carry bits are present at the same time, carry propagate and carry create
generate information on the carry bits in each bit of CLA adder. The inputs A,B, and PI
are the carry propagation bits in the CARRY LOOK AHEAD adder's design.

Pi = A XOR B (3.7)

22
 Figure 3.5 Schematic for carry propagation in CLA
3.5.2 SCHEMATIC FOR CARRY GENERATION IN CLA USING GDI

Figure 3.6 Schematic for carry generation in CLA

Carry bits are known in a CLA adder from carry propagate and carry generate, where
all of the carry bits are present at the same time and a carry generation bit is formed
in each bit of the CLA adder. The CARRY LOOK AHEAD adder has three inputs:
A, B, and GI, which is the carry propagation bit.

GI = A AND B (3.8)

23
3.5.3 SCHEMATIC FOR 8-BIT CLA ADDER USING GDI LOGIC

In 8-bit CLA adder consists of eight full adder and inputs augend and addend are give
to full adder , coming to carry input of full adder , each full adder is given with
predicted carry . This predicted carry is circuit implemented to each full adder circuit
based on carry input or initial carry given to first full adder circuit and carry
generation and propagation bits of own and previous full adders such that for each
carry is generated simultaneously and produce sum and carry at a time from a each
full adder of CLA adder and in this way CLA adder works and coming to 8-bit CLA
adder , it have 8-full adder circuits and having 7-input carry prediction circuits based
on carry generation and carry propagation and it have output sum from S0 to S7 and
carry from C7 to C0 and input carry Cin is “0”.

Figure 3.7 Schematic for 8-bit CLA using GDI logic

24
WORKING OF 8-BIT CLA ADDER
• Consider the following two input sequences: 00000101 and 00001010. The A7 A6 A5
A4 A3 A2 A1 A0 and B7 B6 B5 B4 B3 B2 B1 B0 are represented by these.
• The input carry in this adder idea is 0.
• When A0 and B0 are applied to the first full adder, the input carry is 0.
• A0 = 1; B0 = 0; Cin=0
• The sum (S0) and carry (C0) of this adder will be generated according to the Sum and
Carry formulae. Sum = A0B0Cin and Carry = A0B0B0CinCinA0 are the output
equations, according to theory.
• The first full adder's sum and carry are S0=P0Cin and C0=G0+P0Cin, respectively.
•According to this equation, S1 = 1 and C1=0 for the first full adder.
• The output S1 = 1 and C1 = 0 are the same as for the next input bits A1 and B1. The
crucial aspect here is that the second stage complete adder receives input carry, i.e.,
consider C0 =G0+P0C0 as a combinational circuit, and S1=P1C0 and C1 =G1+P1.C0 as
sum circuits.
• As a result, the final output sequence (S7S6S5S4 S3 S2 S1S0) = (00001 1 1 1) and
the output carry C7 = 0 will be obtained.
• When applied to this carry look ahead adder, this is the addition process for 8-bit
input sequences.

3.6 RIPPLE CARRY ADDER

The carry-out of each full adder is equal to the carry-in of the next most
significant full adder in a ripple carry adder. It's called a ripple carry adder because
each carry bit ripples into the next stage. To add an N-bit number, multiple complete
adder circuits can be cascaded in parallel. In an N-bit parallel adder, there must be N
full adder circuits. The carry-out of each full adder is equal to the carry-in of the next
most significant full adder in a ripple carry adder. It's called a ripple carry adder
because each carry bit ripples into the next stage. The sum and carry out bits of any
half adder stage in a ripple carry adder are not valid until that stage's carry in happens.
A propagation delay within the logic circuitry causes this. The duration between the
application of an input and the occurrence of the matching output is known as
propagation delay. The output is "1" when the input is "0," and vice versa. The
propagation delay is the time it takes for the NOT gate's output to become "0" after

25
logic "1" is applied to the NOT gate's input. Similarly, the carry propagation delay is
the time between when the carry in signal is applied and when the carry out (Cout)
occurs Signal. A circuit diagram for an 8-bit ripple carry adder is shown below.
Advantages

The following are some of the advantages of a ripple-carry-adder.

1. This carry adder has the advantage of allowing us to execute correct

addition for n-bit sequences.

2. It's not tough to design this adder.

3. When the input bit sequences are big, half adders and full adders do not
accomplish the addition function. Ripple carry adders offer an option.

4.Low power is needed for the operation. Time response is so fast.

Disadvantages

1. The Ripple Carry Adder does not allow you to employ all of your full adders
at the same time.
2. Each full adder must await the availability of the carry bit from the full adder
adjacent to it.
3. The propagation time is lengthened.
4. As a result, the ripple carry adder becomes extremely slow.

3.6.1 SCHEMATIC OF 8-BIT RIPPLE CARRY ADDER USING GDI

LOGIC
In this adder, four full adders are linked in a cascade. The carry input bit, Cin, is
always set to zero. When the input carry 'Cin' is applied to the two input sequences A0 A1
A2 A3 A4 A5 A6 A7 and B0 B1 B2 B3 B4 B5 B6 B7, S0 S1 S2 S3 S4 S5 S6 S7 and
output carry C7 for A0 A1 A2 A3 A4 A5 A6 A7 and B0 B1 B2 output.

26
 Figure 3.8 Schematic of 8-Bit Ripple Carry Adder using GDI logic

WORKING OF 8- BIT RIPPLE CARRY ADDER

• Consider the following two input sequences: 00000101 and 00001010.These are
representing the A7 A6 A5 A4 A3 A2 A1 A0 and B7 B6 B5 B4 B3 B2 B1 B0.
• As per this adder concept, input carry is 0.
• When A0 and B0 are applied to the first full adder, the input carry is 0.
• A0 = 1; B0 = 0; Cin=0
• The sum (S1) and carry (C1) of this adder will be generated using the Sum and Carry
formulae. Sum = A0B0Cin and Carry = A0B0B0CinCinA0 are the output equations,
according to theory.
• For the first full adder, S0 =1 and Carry output, C0=0, according to this equation.
• The output S1 = 1 and C1 = 0 are the same as for the next input bits A1 and B1. The
crucial point here is that the second stage full adder receives input carry in the form of
C0, which is the first stage full adder's output carry, and it serves as the stage's input
carry.
• As a result, the final output sequence (S7 S6 S5 S4 S3 S2 S1 S0) = (0 0 0 1 1 1 1) and
the output carry C7 = 0 will be obtained.
• When applied to 8-bit input sequences, this is the addition process of carry adder.

27
 CHAPTER-4
SOFTWARE TOOL

4.1 INTRODUCTION TO TANNER TOOL:

Tanner EDA is an integrated circuit design suite. Enter schematics, perform SPICE
simulations, do physical design i.e. With these tools, you can perform design rule checks
(DRC) and layout versus schematic (LVS) testing.
This procedure is carried out using three tools:
1. S-edit is a tool for capturing schematics.
2. T-SPICE is a combined SPICE and S-edit simulation engine. The physical design tool
L-edit.
S-edit is a schematic entry programme for specifying circuits that can be used in an integrated
circuit architecture. It also has the option of using the T-SPICE simulation engine to do SPICE
simulations of the circuits. S-edit can be used to configure and operate T-SPICE.
4.2 RULES AND GUIDELINES TO USE TANNER

4.2.1 Setup your Directory Structure & download Libraries

a) Turn on a computer.
b) You wish to organise all of your Tanner EDA projects into a directory. To use the library
and model files in your simulations, you must additionally download and unzip them from the
course website. EELE414 VLSI Fall2011Tanner Projects is the name of the directory structure.
c) Download the "Tanner Libraries.zip" zip file from the course website. Unzip the file into
your Tanner Projects folder. This package contains everything you'll need to use S-edit (circuit
symbols), run SPICE simulations (models), and do physical layout (layer definitions, DRC,
LVS).
4.2.2 Start a New Design & Setup Libraries

a) Start – All Programs – Tanner EDA – Tanner Tools v12.6 – S-Edit v12.6 a) Create a
New Design: Start – All Programs – Tanner EDA – Tanner Tools v12.
b) Using the pull-down choices, create a new design: - New File – New Design A dialogue
box will popup, asking for the name of the design and its location. S-edit will generate
a folder with the same name in the place you specify, including all of the design files.
You should give each simulation you run a descriptive name. - After clicking "OK" and
inputting the name "HW03 NMOS IV Part1," go to your "EELE414 VLSI

28
 Fall2011Tanner Projects" directory.

c) Make a fresh cell. A design element is referred to as a "cell." Several views, like as
schematics and symbols, can be stored in a cell. Inside other cells, cells can be produced. We
commonly refer to the cell as "TOP" when running a simulation. When testing a circuit, such
as an inverter, each cell will include a diagram of the devices as well as a symbol. The inverter
cell is made up of simulation-only elements like voltage sources and probes. This allows us to
distinguish between cells that will be implemented on the die and cells that will only be used
for simulation Create a new cell view using the pull down menus: - Cell – New View: - type
"TOP" in the cell name. Select "HW03 NMOS IV Part1" as the design name and click OK.
The "view0" interface and view name can be left alone. There will be no schematic page. This
is something you should save immediately.
d) Include symbol libraries: First, make a library with symbols for all basic circuit elements,
such as resistors, NMOS, and capacitors. You downloaded and unzipped the Tanner
Libraries.zip package, which contains libraries for all of the basic symbols - On the left side of
the S-edit screen, click the "Add" button in the Libraries box. - Select "OK" from the
"LibrariesAllAll.tanner" menu. The following libraries should be visited:

Figure 4.1 Libraries

e) Configure the SPICE models in the Generic 025 kit. Symbols for NMOS and PMOS
transistors can be found in the libraries you just uploaded. Even non-linear components like

29
MOS transistors require a model to be described. Because each NMOS transistor made in a
different technology behaves differently, SPICE will not know what to do if you simply enter
an NMOS symbol in your schematic.

We'll use the "Generic 025" transistor technology in this example, which is a standard 0.25um
CMOS process. You'll need to use S-edit to develop SPICE models for this. After that, you can
associate the 0.25um model with that symbol when you enter an NMOS or PMOS transistor.

Configure the SPICE models using the pull-down menus: - Setup – SPICE Simulation – On
the left, highlight "General" in the dialogue that displays.
- Click the "Library Files" field on the right. This is where you'll save any SPICE models you'll
use in your simulations. Choose "Generic 025 Kit Generic 025 SPICE Models Level1.lib" from
the drop-down option. Click the "SPICE File Name" area on the right. This is where you enter
the filename "TOP.sp" and the name and location of the spice netlistEELE414 VLSI
Fall2011Tanner ProjectsHW03 NMOS IV Part1".
- On the right, select the "Simulations Results File Name" field. The outcomes of the simulation
will be recorded here. The waveform viewer will seek for this file when you go to plot your
results. Enter the filename "TOP.out" in your design directory "EELE414 VLSI
Fall2011Tanner ProjectsHW03 NMOS IV Part1."
- You must first choose an analysis type before closing this window

Figure 4.2 Setup SPICE Simulation of Cell Top

30
4.2.3 Enter the Schematic to simulate the IV behaviour of an NMOS Transistor
We shall proceed to the next circuit.

Figure 4.3 Simulate the IV behaviour of an NMOS Transistor

a) The NMOS transistor makes its debut.

- On the left, click "Devices" in the upper box. This will display every symbol in this category.
Every component that a CMOS integrated circuit might need should be visible.
- In the bottom left window, click once on "NMOS." The symbol for the NMOS transistor
should appear in the bottom symbol viewer window.
- To place the NMOS, choose "Instance" from the drop-down menu.
When you press this button, two things happen. First, a popup will display, allowing you to
configure the NMOS parameters. After that, the icon will be tied to your mouse. The NMOS will
be placed in the schematic first, and its attributes will be set subsequently. This is a more
convenient method of using the device. To drop an instance of the NMOS, click in the
schematic window. To quit insert mode, press the "Esc" key.

31
 Figure 4.4 Schematic to Simulate the IV behaviour of an NMOS Transistor
The NMOS has been added to the schematic.
Zooming notes:
- - [Home] = fit zoom
- - [-] zooms out; - [=] zooms in.
- -The scroll wheel also zooms in and out. Click the NMOS icon to configure the NMOS.
On the left, you'll find the device's properties. The following is what we want to do:
As the model, type "NMOS." The Generic 025 library first featured this model.
- Title: M1. The name of MOS transistors must begin with a "M" according to SPICE. The
final name in the TOP.sp file will be "MM1" because S-edit automatically appends a M to the
name. However, it is recommended that all MOS transistors be given the letter M.
- W Set the value to 2.5u. This is the standard.
- L Set the value to 0.25u. This is the standard.

b) Create a DC source for VGS - Create a "SPICE Elements: Voltage Source" in the same way
you did for the NMOS symbol.
- Enter the following values in the voltage source:
- DC Master Connection (This is the default, but you can change it using this method.)
- VGS Source is the name of the file (it is a Using descriptive names is a smart idea.)

32
V - DC Master Connection (This is the default, but you can change it using this method.) This
is where the DC voltage will be set. (For example, 4v, 5v). In this scenario, we'll use a
parameter rather than a hardcoded value. We'll give the option a name here and then configure
it later. For the value of V, type "VGS param." You must employ sweep parameters while
doing a DC sweep.

c) Create a DC source for VDS - Create a DC source for VGS using the same techniques as
before:
- DC Master Interface (This is the default, but you can alter it to something else this way.)
VDS Source is the name of the file. "VDS param" - V

Place the sources as shown in the diagram:

Figure 4.5 Create a DC source for VDS

A word on zooming: To move a component, hold down ALT-M. Click and drag the
components while holding these buttons down.

- To rotate the device, first click it and then use the [r] key..

d) Enter Grounds - To enter three grounds from Gnd, follow the instructions above.

33
Figure 4.6 VDS Source is the name of the file. "VDS param" - V

e) Input Wires - To enter wires, go to the top of the page and click the "wire" symbol.

Figure 4.7 Net Label icon

- By moving a symbol node around, you can make wires. Enter corners by clicking once where
you wish to turn - label nets using the "Net Label" icon at the top.

34
 Figure 4.8 SPICE Commands

f) Monitor IDS with a Current Probe- Type the following SPICE Commands:
Current Print Component Nothing is affected by this. Place it wherever you wish, then use the
properties dialogue to tell it what current to monitor.
D (terminal) in the properties dialogue (this is the Drain of the NMOS)
MM1 device (the name of the device). (Note that we called it M1, but S-edit adds another M
to the name automatically.) This appears only after the Netlist has been run. DC inspection
(SELECTING THIS IS ESSENTIAL!!!)

4.2.4 Set up the parameters that will be used for the DC sweep analysis in Part 4.2.3.
We set the values of the VGS and VDS sources to "VGS param" and "VDS param" when we
entered them. These options must now be set. How to use the pull-down menus:
- SPICE Simulations Setup
- Select "Parameters" from the left-hand menu.
- On the right, click the "Add Parameters" button.
Enter: VGS param is the name of the variable.
1v in value - Click the "Add Parameters" button on the right.
VDS param as a name
Value: 2.5v

35
These settings will be overwritten throughout our sweep, but the parameters must first exist.
4.2.5 : Setup the SPICE DC Sweep Analysis
How to use the pull-down menus:

- SPICE Simulations Setup

- Select "DC Sweep Analysis" from the left-hand menu.

- On the right, type the following for Source: (this is what will be swept)

Name of the source or parameter: VDS parameter

Initial Value: 0

2.5 Stop Value

0.1 step

lin type sweep

- Fill in the blanks on the right for Source (this is what will be swept)

Name of the source or parameter: VGS parameter

1 is the starting value.

1.5 Stop Value

0.5 step

lin type sweep

NOTE: The independent axis will be plotted with the first parameter you bring up in this
window.

4.2.6: Design Simulation

a) First, use the pull-down choices to double-check your design:

Instruments for Design Checks (any warnings or errors will be shown at the bottom)
b) Experiment with your design: - To begin the simulator, set the clock to the Green Arrow:

36
Now the T-Spice window should appear. If everything is in order, the waveform viewer will
also show. If everything went correctly, your waveforms should look like this:

Figure 4.9 The parameters that will be used for the DC sweep analysis
c) View the Netlist:

- Right-click the file at the bottom of the T-spice window and choose "Show Netlist." This will
open the TOP. The spice engine created and uses a sp Netlist. This is a good place to look after
you've made a mistake. This is a text-based summary of your S-edit entries.

d) Check out the Waveform: If the windows viewer does not appear immediately, right-click
the file in the T- spice window and select "Show Waveform."

Example: Symbol Creation and Transient Analysis of a CMOS Inverter

4.3 Create a New Design, Configure Libraries, and Configure Simulation

a) We'll build a CMOS inverter and simulate its transient response in this example. To excite
the circuit, we'll develop an inverter design using a symbol and then instantiate it in another
schematic.
b) Adding another view to a design is how symbols are handled. We'll begin by constructing a
"Inverter" design, followed by a schematic view. NMOS and PMOS inverters will be used in
this design. "Ports" will be added to Input, Output, VDD, and VSS, among other things. The

37
design will then be enhanced with a symbol view. The symbol will include the inverter shape
as well as the pins for Input, Output, VDD, and VSS.
c) After that, we'll create a second TOP schematic for testing the inverter. The inverter symbol
will be made with TOP. The inverter design should only involve fabricate objects. TOP will
include ideal voltage sources, power supply, and a fake load to produce the input waveform.
As a result, we only make progress on isolated circuits when we do physical design (i.e.,
layout).

-Start S-Edit
-Create a new design called:
"HW04 INV Transient Part1 EELE414 VLSI Fall2011 Tanner Projects"
Tanner Projects - Libraries It is necessary to include everything. Combine everything. Tanner
library to the left-hand library list - Using the Pull Down Menus, create a new Cell called
"TOP" - - Name of New Cell
View = TOP
Set up the simulation
in the schematic view type, utilising the pull down menus :

- Setup – SPICE Simulation – In the Setup SPICE box, select the General Tab and make the
following changes:

SPICE HW04 INV Transient Part1 is the file. Generic 025 Kit Simulation Results in TOP.sp
Library Files Generic 025 SPICE Models Level1.lib The file's name is HW04 INV Transient
Part1. TOP.in is a website that provides information on various topics. On the left, select
"Transient/Fourier Analysis" and input the following values:
Stop Time Time Step Maximum = 10ps
- Click "OK" 2ns = Stop Time
4.3.1 Create the Inverter
a) Make a new schematic view using the pull-down menus:
- Cell - New
View Type = schematic
b) New View Name = Inverter
Here's how the inverter works:

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Figure 4.10 Create the Inverter

- Filling up the NMOS: Name = M1 L = 0.25u W = 2.5u

=NMOS model

- Getting inside PMOS:

L = 0.25u W = 5.0u Name = M2

=PMOS model

- Getting into the Ports:

To enter ports, utilise the icons at the top of the S-edit window.

Fill in the blanks:

In the Port: Out Port: Call it "IN" It'll be called "OUT."

Input/Output Port: It'll be called "VDD."

Name the in/out port "VSS"

- Connect the Inverter

Make wire connections as shown in the preceding image.
Make a SPICE network list:
It's a good idea to export a SPICE Netlist to make sure you've entered the schematic
accurately. This Netlist will be used to examine "Layout versus Schematic (LVS)" later on.
We'd want to export a Netlist of the inverter's schematic cells to LVS as a standalone

39
 Netlist. We'll use a TOP level schematic with a Netlist that includes ideal voltage sources
to simulate this inverter. Because it contains non-fabricable components, this Netlist
cannot be used for LVS.

Use the pull-down menus to do the following tasks while the schematic is open:
- Go to File – Export – SPICE.
- Create a file called "Inverter.spc" in your design directory.
- Select "OK."
If you open Inverter.spc using a text editor, you'll see the following:

Figure 4.11 TOP level schematic with a Netlist

Create the Inverter Symbol first.

S-edit may manually or automatically construct symbols by producing a new symbol view. The
symbol generation will be automated. This will create a new symbol view, as well as the
symbol's ports and shape, from the schematic. While the final shape of the sign is rarely what
we want, it does a lot of the work for us.

- While the schematic view is active, use the pull-down choices to generate the symbol view:

Update Symbol in Cell

40
A square symbol and four ports with the same names as the ones you typed into the Inverter,
schematic view will appear in a new window (i.e., IN, OUT, VDD, VSS). You should tweak
the shapes till they're perfect.

Figure 4.12 Create the Inverter Symbol

A note on drawing: You'll be moved to a mode where you can build lines that aren't wires if
you click the "Path" icon.
The "Circle" icon can be clicked to enter the inversion bubble.
Holding down "alt-m" will shift the ports.
By selecting and pushing the "r" button, the ports can be rotated.

Remember to save your work.

4.3.2 Create the TOP schematic for the inverter to be tested.

a) In the TOP schematic, draw the inverter. Using the pull-down choices, open the TOP
schematic view: - Open View Cell is the cell's top name. type of view schematic

Select your "HW04 INV Transient Part1" library from the library windows on the left side of
the window. Your two Cells "TOP" and "Inverter" can be found in the lower left pane.

41
 - When you click "Inverter," your symbol will appear in the symbol viewer.
- You can place your symbol in the top schematic by pressing the "Instance" button.

a) To power and stimulate your inverter, complete the following circuit:

4.13 Create the TOP schematic for the inverter to be tested

- Select a source of pulse voltage. In the SPICE Elements collection, all voltage sources are the
same component. The default is DC, but the properties dialogue allows you to alter it to any
other type of source. Name = Vin_Source

Interface Master = 1ns is the pulse period.

V High = 2.5v V Low = 0v Pulse Width = 0.5ns
10ps rise time
10ps = Fall Time
- From the Devices library, select a Load capacitor.
Cload C =50 degrees F
- For VDD Name = VDD Source, provide a DC Source.
DC V = 2.5v Master Interface
- Name the wire connections Vin and Vout using the Miscellaneous library's grounds
- For both Vin and Vout, insert a voltage probe.

42
4.3.3 Simulate the Design

a) First, use the pull-down choices to double-check your design:

- Design Checking Tools (Errors and warnings will appear at the bottom.)

b) Play around with your design:

- To begin the simulator, set the clock to the Green Arrow:

Now the T-Spice window should appear. If everything is in its appropriate place, the waveform
viewer will also display. Your waveforms should look like this if everything went well:

Figure 4.14 Simulate the Design

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4.4 STEPS TO USE MICROWIND

• Download the EXPORT MICROWIND tool from the sources.

• To open the folder, unzip the file and double-click the "MICROWIND.exe" file.
• Now, a window will be opened.
• To import the saved file from the DSCH, click the option “COMPILE” and open the
“COMPILE VERILOG FILE”.
• A dialogue box will be open and select the “.txt” file and click OPEN.
• Now a dialogue box containing Verilog HDL file will be open and click the option COMPILE.
• Click the COMPILE and click the BACK TO EDITOR option, then the software
automatically generates Layout design of the compiled Verilog HDL file.
• In this window, area of the designed circuit will be appeared at the centered bottom.
• The simulation process will begin when you click the SIMULATON button, and a new
window will open with wave formations. From this, we may obtain the power consumption of
the designed circuit.
• By changing the SELECT FOUNDRY option, we may obtain different design rules of CMOS
designing.
• By taking the appropriate metal from the palate of the software, we may design our own
circuit layout design without importing the Verilog HDL file.

4.5 STEPS TO USE DSCH

• Firstly, download the Digital Schematic tool from sources.
• After downloading “DSCH” zipped file is appeared in downloads. Then unzip the file and
“DSCH” folder is created.
• By clicking on DSCH folder, IEEE folder and some files are appeared.
• Open the folder and double-click the "DSCH.exe" file.
• Now, the software of DSCH tool window will be open.
• HOW TO DESIGN:
• File------ New------ a space will be open for the designing the circuit.
• To design a circuit, components will be dragged from the library (a box in the right side of
the tool).
• The dragging will be accomplished by "holding the left mouse button and dragging."

44
• Connections are made by dragging to the edge of the components while holding the right
mouse button down."
• Entire design of the circuit will be done by dragging and dropping.
• Now select the SAVE option from the FILE menu to save the design.
SIMULATION PROCESS:
• After constructing the circuit design, to start the simulation process, go to the SIMULATION
• Option and click the START SIMULATION.
• In simulation process, a small window will be open at the right bottom of tool. It indicates
the processing of the simulation.
• By clicking on the input switch of the design, we may obtain the function operation of the
circuits.
Clicking the inputs is determined as the logic values.
• While the simulation process is going, we may obtain the timing diagrams from the option of
TIMING DIAGRAM in the tool bar.
• In tool, the option SELECT FOUNDRY is use to chance the nano-meter technology for the
simulation process.
• To import the file into the Microwind, go to the file---select the option “Make a Verilog file”.
• It will automatically gives and imports the Verilog file of the design to the Microwind tool.
• Now, the process of design is stepped to the MICROWIND tool.

45
 CHAPTER-5
RESULTS AND DISCUSSIONS

Designed a Full adders to get balanced parameters such as power, area, delay with
different logics. All the Full adder are designed in EDA tools such as Tanner, Microwind,
Digital Schematic and measures the power , area and delay. The absolute work is carried
using Tanner 130 nmm Technology and Microwind 90nmm technology. The simulation
results specifies layout design and area and power and time delay. Figure 1.1 depicts the
simulation of Conventional CMOS Full adder, which shows area optimization for given
circuit. So, this work focuses on Physical Layout using Microwind.

Table 5.1 Comparison of Area and Power and Time delay

S.NO Full adders Transistor Area Power Time
Count 𝟐 (mW) delay(ns)
(𝝁𝟐 m )
1. Conventional CMOS Full 28T 759 0.327 0.43
Adder
2. Adiabatic Full adder 28T 759 0.322 0.29
3. Transmission gate Full 20T 500 0.321 0.29
adder
4. Gate Diffusion Input 12T 300 0.0711 0.15
Full adder

Figure 5.1 depicts the simulation of Conventional CMOS Full adder, which shows area
optimization for given circuit. So, this work focuses on Physical Layout using Microwind.

Figure 5.1 Layout design of Conventional CMOS Full adder

46
Figure 5.2 depicts the simulation of Conventional CMOS Full adder ,which shows
the power constraints of given circuit using Microwind ,given input parameters step
length for time is 10ps and simulation length is 5ns and by applying this parameters
to Microwind waveform window and we get the power consumed by circuit.

Figure 5.2 Simulation results of Conventional CMOS Full adder using

Microwind

Figure 5.3 depicts the simulation of Conventional CMOS Full adder ,which shows
the time delay constraint of given circuit using Tanner tool ,time delay is time
required to change output after applying input that is high to low or low to high
propagation and using cursors at 50 percent of rise or fall edge of input compared
with output and get time delay of given circuit.

47
Figure 5.3 Simulation results of Conventional CMOS Full adder using Tanner

Figure 5.4 depicts the simulation of Adiabatic Full adder, which shows area
optimization for given circuit. So, this work focuses on Physical Layout using
Microwind.

Figure 5.4 Layout design of Adiabatic Full adder

48
Figure 5.5 depicts the simulation of Adiabatic Full adder ,which shows the power
constraints of given circuit using Microwind ,given input parameters step length for
time is 10ps and simulation length is 5ns and by applying this parameters to
Microwind waveform window and we get the power consumed by circuit.

Figure 5.5 Simulation results of Adiabatic Full adder using Microwind

Figure 5.6 depicts the simulation of Adiabatic Full adder ,which shows the time delay
constraint of given circuit using Tanner tool ,time delay is time required to change
output after applying input that is high to low or low to high propagation and using
cursors at 50 percent of rise or fall edge of input compared with output and get time
delay of given circuit.

49
 Figure 5.6 Simulation results of Adiabatic Full adder using Tanner

Figure 5.7 depicts the simulation of Transmission Gate Full adder, which shows area
optimization for given circuit. So, this work focuses on Physical Layout using
Microwind.

Figure 5.7 Layout design of Transmission Gate Full adder

50
Figure 5.8 depicts the simulation of Transmission Gate Full adder ,which shows the
power constraints of given circuit using Microwind ,given input parameters step
length for time is 10ps and simulation length is 5ns and by applying this parameters
to Microwind waveform window and we get the power consumed by circuit.

Figure 5.8 Simulation results of Transmission Gate adder using Microwind

Figure 5.9 depicts the simulation of Transmission Gate Full adder ,which shows the
time delay constraint of given circuit using Tanner tool ,time delay is time required
to change output after applying input that is high to low or low to high propagation
and using cursors at 50 percent of rise or fall edge of input compared with output and
get time delay of given circuit.

51
 Figure 5.9 Simulation results of Transmission Gate Full adder using Tanner

Figure 5.10 depicts the simulation of Gate Diffusion Input Full adder, which shows
area optimization for given circuit. So, this work focuses on Physical Layout using
Microwind.

Figure 5.10 Layout design of Gate Diffusion Input Full adder

52
Figure 5.11 depicts the simulation of Gate Diffusion Input Full adder ,which shows
the power constraints of given circuit using Microwind ,given input parameters step
length for time is 10ps and simulation length is 5ns and by applying this parameters
to Microwind waveform window and we get the power consumed by circuit.

Figure 5.11 Simulation results of Gate Diffusion Input adder using Microwind

Figure 5.12 depicts the simulation of Gate Diffusion Input Full adder ,which shows
the time delay constraint of given circuit using Tanner tool ,time delay is time
required to change output after applying input that is high to low or low to high
propagation and using cursors at 50 percent of rise or fall edge of input compared
with output and get time delay of given circuit.

53
Figure 5.12 Simulation results of Gate Diffusion Input Full adder using Tanner

Figure 5.13 depicts the simulation of 8-Bit CLA adder using Gate Diffusion Input
Logic, which shows area optimization for given circuit. So, this work focuses on
Physical Layout using Microwind.

Figure 5.13 Layout design of 8-Bit CLA adder using Gate Diffusion Input
Logic

54
Figure 5.14 depicts the simulation of 8-Bit CLA adder using Gate Diffusion Input
Logic, which shows the power constraints of given circuit using Microwind ,given
input parameters step length for time is 10ps and simulation length is 5ns and by
applying this parameters to Microwind waveform window and we get the power
consumed by circuit.

Figure 5.14 Simulation results of 8-Bit CLA adder using Gate Diffusion Input
Logic using Microwind

Figure 5.15 depicts the simulation of 8-Bit CLA adder using Gate Diffusion Input
Logic, which shows the propagation delay constraint of given circuit using Tanner
tool, propagation delay is the time taken by input signal to reach its destination and it
is done by T-spice in tanner tool.

55
Figure 5.15 Propagation delay results of 8-Bit CLA adder using Gate Diffusion
Input Logic using T-Spice window

Figure 5.16 depicts the simulation of 8-Bit Ripple Carry Adder using Gate Diffusion
Input Logic, which shows area optimization for given circuit. So, this work focuses
on Physical Layout using Microwind.

Figure 5.16 Layout design of 8-Bit Ripple Carry Adder using GDI Logic

56
 Figure 5.17 depicts the simulation of 8-Bit Ripple Carry Adder using Gate Diffusion
Input Logic, which shows the power constraints of given circuit using Microwind ,
given input parameters step length for time is 10ps and simulation length is 5ns and
by applying this parameters to Microwind waveform window and we get the power
consumed by circuit.

Figure 5.17 Simulation results of 8-Bit Ripple Carry Adder using GDI Logic using

Figure 5.18 depicts the simulation of 8-Bit Ripple Carry Adder using Gate Diffusion
Input Logic, which shows the propagation delay constraint of given circuit using
Tanner tool, propagation delay is the time taken by input signal to reach its destination
and it is done by T-spice in tanner tool.

57
 Figure 5.18 Propagation delay results 8-Bit Ripple Carry Adder using GDI
Logic of using T-Spice window

Table 5.2 Comparison of Area and Power and Propagation delay

S.NO 8-Bit adder architecture Transistor Area Power Propagation

Count 𝟐 (mW) Delay(ns)
(𝝁𝟐 m )
1. 8-Bit Ripple Carry Adder 96T 2940 0.300 40
2. 8-Bit Carry Look Ahead 152T 4555 0.454 20
adder

58
 CHAPTER-6
CONCLUSION & FUTURE SCOPE

This project proposed the design and analysis of 8-bit carry look ahead adder using
gate diffusion input logic . Also, designed the full adders using different logics and also
done the power, area, delay analysis of all full adder circuits with different logics. By
comparing all the parameters such as power, area, delay, Full adder implemented using
Gate Diffusion Input Logic is found as best. Full adder is implemented using the gate
diffusion input logic, the reduction of power, delay variability and noise immunity and
area calculations are verified. Designed an 8 bit carry look ahead adder and 8 bit ripple
carry adder using gate diffusion input logic and compared all parameters such as power,
area, propagation delay. In this work, it is observed that the propagation delay of CLA
adder is less than RCA adder due to parallel generation of sum and carry in each full adder
circuit . But in case of power and area of the CLA adder has failed when compared to RCA
adder. Finally, this Gate Diffusion Input logic circuit is compared by implementing the
Carry Look Ahead Adder with the Ripple Carry Adder circuit for the optimization of the
area, power, noise immunity and propagation delay using Tanner and Microwind and
Digital Schematic tool in 90nm technology for the CMOS VLSI technologies which is
used in the microprocessors.

Design and implement of with their efficient decoder 8bit, 16bit, 32bit, 64bit
and 128bit Carry Look Ahead Adder architecture can be designed by using the Full Adder
and universal gates and logic gates. New architecture can be developed and implemented
using different adders and they can be further investigated for the reduction in area and
power.

59
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