UNIT 3

COMBINATIONAL LOGIC
A combinational circuit consists of input variables, logic gates, and output variables. The logic gates
accept signals from the inputs and generate signals to the outputs. This process transforms binary
information from the given input data to the required output data. Obviously, both input and output
data are represented by binary signals; i.e., they exist in two possible values, one representing logic-1
and the other logic—0. A block diagram of a combinational circuit is shown in Fig. 4-1.
For n input variables, there are 2n possible combinations of binary input values. For each
possible input combination, there is one and only one possible output combination. A combinational
circuit can be described by m Boolean functions, one for each output variable. Each output function is
expressed in terms of the n input variables.

Adders :
Half adders: A combinational circuit that performs the addition of two bits is called a half adder so
this circuit needs 2 binary inputs and 2 binary outputs. The input variable designates the augend and
addend bits. The output variables produce the sum and carry.
x y C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

Assign symbols x and y to the two inputs and symbol s(for sum) and c(for carry), to outputs.
The carry output is 0 unless both the inputs are one. The carry output is 0 unless both the inputs are
one. The s output represents the least significant bit of sum. The simplified sum of products expression
are S=xy’+x’y. The expression for carry is C=xy.
Block diagram
Half adder can be implemented with an Ex-OR and an AND gate as shown in above figure(e)
Full adders:
Full adder is a combinational circuit that performs the arithmetic sum of 3 input bits. It consists of 3
inputs and 3 outputs, 2 of the input variables denoted by x and y represents the 2 significant bits to be
added. The third input z represents the carry from the previous lower significant position.
Truth Table
Block diagram:

x y z C S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

The K map is used for simplifying the 2 output functions

Subtractor:
Half subtractor : A half-subtractor is a combinational circuit that subtracts two bits and produces their
difference. It also has an output to specify if a 1 has been borrowed. Designate the minuend bit by x
and the subtrahend bit by y. To perform x - y we have to check the relative magnitudes of x and y. If
x > y we have three possibilities: 0-0 = 0, 1-0=1,1-1 = 0. The result is called the difference bit. If x <
y, we have - 1, and it is necessary to borrow a 1 from the next higher stage.
Truth Table:
x y Diiference(D) Borrow(B)
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
The Boolean functions for the two outputs of the half-subtractor are derived directly from the truth
table:
D = x'y + xy'
B = x'y
It is interesting to note that the logic for D is exactly the same as the output S in the half-adder.

Block diagram

Logic Diagram:

Full subtractor: is a combinational circuit that performs a subtraction between 2 bits taking into
account that a 1 may have been borrowed by a lower significant bit. The three inputs x, y, z denote the
minuend subtrahend and previous borrow respectively the 2 outputs D and B represents the difference
and output borrow respectively.
The eight rows under the input variables designate all possible combinations of l's and O's that
the binary variables may take. The l's and 0's for the output variables are determined from the
subtraction of x - y - z. The combinations having input borrow z = reduce to the same four conditions
of the half-adder. For x = 0,
y = 0, and z = 1, we have to borrow a 1 from the next stage, which makes B = 1 and adds 2 to x. Since
2 — 0—1 = 1, D = 1. For x = and yz = 11, we need to borrow again, making B = 1 and x = 2. Since 2
— 1 — 1 = 0, D = 0. For x = 1 and yz = 01, we have x - y - z = 0, which makes B = and D = 0. Finally,
for x = 1, y = 1, z = 1, we have to borrow 1, making B = 1 and x = 3, and 3 — 1 — 1=1, making D =
1.
Truth table:
x y z B D
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Block Diagram:
Logic diagram:

Code Convertor: is a circuit that makes the 2 systems compatible even though each uses a different
binary code. A conversion circuit must be inserted between the two systems if each uses different
codes for the same information.
Design procedures of code converters will be illustrated by means of an example of conversion from
the BCD to the excess -3 code.

The maps are drawn to obtain simplified Boolean functions for each output.
BINARY PARALLEL ADDER
The full-adder forms the sum of two bits and a previous carry. Two binary numbers of n bits each can
be added by means of this circuit. To demonstrate with a specific example, consider two binary
numbers, A = 1011 and B = 0011, whose sum is S = 1110. When a pair of bits are added through a full-
adder, the circuit produces a carry to be used with the pair of bits one significant position higher. This
is shown in the following table:

The bits are added with full-adders, starting from the least significant position (subscript 1), to form
the sum bit and carry bit. The input carry C1, in the least significant position must be 0. The value of
Ci+1, in a given significant position is the output carry of the full-adder. This value is transferred into
the input carry of the full-adder that adds the bits one higher significant position to the left. The sum
bits are thus generated starting from the rightmost position and are available as soon as the
corresponding previous carry bit is generated.
The sum of two n-bit binary numbers, A and B, can be generated in two ways: either in a serial
fashion or in parallel. The serial addition method uses only one full-adder circuit and a storage device
to hold the generated output carry. The pair of bits in A and B are transferred serially, one at a time,
through the single full-adder to produce a string of output bits for the sum. The stored output carry
from one pair of bits is used as an input carry for the next pair of bits. The parallel method uses n full-
adder circuits, and all bits of A and B are applied simultaneously. The output carry from one full-adder
is connected to the input carry of the full-adder one position to its left. As soon as the carries are
generated, the correct sum bits emerge from the sum outputs of all full-adders.
A binary parallel adder is a digital function that produces the arithmetic sum of two binary
numbers in parallel. It consists of full-adders connected in cascade, with the output carry from one
full-adder connected to the input carry of the next full-adder.
Figure shows the interconnection of four full-adder (FA) circuits to provide a 4-bit binary parallel
adder. The augend bits of A and the addend bits of B are designated by subscript numbers from right
to left, with subscript 1 denoting the low-order bit. The carries are connected in a chain through the
full-adders.
The input carry to the adder is C1 and the output carry is C5. The S outputs generate the required
sum bits. When the 4-bit full-adder circuit is enclosed within an IC package, it has four terminals for
the augend bits, four terminals for the addend bits, four terminal s for the sum bits, and two terminals
for the input and output carries.
An n-bit parallel adder requires n full-adders. It can be constructed from 4-bit, 2-bit, and 1-bit
full-adders ICs by cascading several packages. The output carry from one package must be connected
to the input carry of the one with the next higher-order bits.
The 4-bit full-adders is a typical example of an MSI function. It can be used in many applications
involving arithmetic operations. Observe that the design of this circuit by the classical method would
require a truth table with 29 = 512 entries, since there are nine inputs to the circuit. By using an iterative
method of cascading an already known function, we were able to obtain a simple and well-organized
implementation.
The application of this MSI function to the design of a combinational circuit is demonstrated
in the following example.

DECIMAL ADDER
A decimal adder requires a minimum of nine inputs and five outputs, since four bits are required to
code each decimal digit and the circuit must have an input carry and output carry. Of course, there is a
wide variety of possible decimal adder circuits, dependent upon the code used to represent the decimal
digits.

The design of a nine-input, five-output combinational circuit by the classical method requires a truth
table with 29 = 512 entries. Many of the input combinations are don't-care conditions, since each binary
code input has six combinations that are invalid. The simplified Boolean functions for the circuit may
be obtained by a computer-generated tabular method. An alternate procedure is to add the numbers
with full-adder circuits, taking into consideration the fact that six combinations in each 4-bit input are
not used. The output must be modified so that only those binary combinations which are valid
combinations of the decimal code are generated.

Binary Coded Decimal Adder (BCD adder)

Consider the arithmetic addition of two decimal digits in BCD, together with a possible carry from a
previous stage. Since each input digit does not exceed 9, the output sum cannot be greater than 9 + 9
+ 1 = 19, the 1 in the sum being an input carry. Suppose we apply two BCD digits to a 4-bit binary
adder. The adder will form the sum in binary and produce a result which may range from 0 to 19.
These binary numbers are listed in Table and are labeled by symbols K, Z8, Z4, Z2 and Z1. K is the
carry, and the subscripts under the letter Z represent the weights 8, 4, 2, and 1 that can be assigned to
the four bits in the BCD code. The first column in the table lists the binary sums as they appear in the
outputs of a 4-bit binary adder. The output sum of two decimal digits must be represented in BCD and
should appear in the form listed in the second column of the table. The problem is to find a simple rule
by which the binary number in the first column can be converted to the correct BCD-digit
representation of the number in the second column.

When the binary sum is greater than 1001, we obtain a nonvalid BCD representation. The
addition of binary 6 (0110) to the binary sum converts it to the correct BCD representation and
also produces an output carry as required.

The logic circuit that detects the necessary correction can be derived from the table entries. It is obvious
that a correction is needed when the binary sum has an output carry K = 1. The other six combinations
from 1010 to 1111that need a correction have a 1 in position Z8. To distinguish them from binary 1000
and 1001 which also have a 1 in position Z8, we specify further that either Z4 or Z2 must have a 1. The
condition for a correction and an output carry can be expressed by the Boolean function:

C=K+Z8Z4+Z8Z2

when C = 1, it is necessary to add 0110 to the binary sum and provide an output carry for the next
stage.

A BCD adder is a circuit that adds two BCD digits in parallel and produces a sum digit also in BCD.
To add 0110 to the binary sum, we use a second 4-bit binary adder as shown in Figure below. The two
decimal digits, together with the input carry, are first added in the top 4-bit binary adder to produce
the binary sum. When the output carry is equal to zero, nothing is added to the binary sum. When it is
equal to one, binary 0110 is added to the binary sum through the bottom 4-bit binary adder. The output
carry generated from the bottom binary adder can be ignored, since it supplies information already
available at the output-carry terminal.