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Eee g594 Advanced Vlsi Devices

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26 views3 pages

Eee g594 Advanced Vlsi Devices

Uploaded by

Sri Nath
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE, Pilani

Pilani Campus
Instruction Division

BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE, PILANI


INSTRUCTION DIVISION
FIRST SEMESTER 2017-2018

Course Handout (Part - II)


Date: 02/08/2017

In addition to Part-I (General Handout) for all courses appended to the time table), this portion
gives further specific details regarding the course.

Course No : EEE G594


Course Title : Advanced VLSI Devices
Instructor-in-charge : Arnab Hazra

1. Scope of the course:

The present course will basically deal with the Physics, Analysis, and Design of Novel and
Advanced VLSI Device (Mostly in Nano-scale dimensions) Structures. The main topics for this
course center around Nano FETs (Field-Effect Devices) the most promising VLSI Device till date.
2. Objective of the course:

At the end of the course, one will be able to:


 Make projections about CMOS device scaling and how it affects circuit/system
performance.
 Recognize the relevant device physics that underlies CMOS device design.
 Go to a conference or read a journal article about CMOS devices and use the knowledge
obtained in this course to understand the material.
 Develop an intuitive feel in addition to solving equations.
 Obtain necessary skills to explore the research space of state-of-the-art VLSI technology.

3. Course Description:

This course examines the device physics of and engineering of advanced transistors and the way
such devices enter into the development of new technologies. Focus is given on the review of metal
oxide semiconductor (MOS) fundamentals along with quasi-ballistic and ballistic transport. Short-
channel effects (SCEs) in sub-micron (towards nanometer regime) metal oxide semiconductor field-
effect transistors (MOSFETs) including device scaling considerations are also included. Device
physics and engineering issues of sub 100 nm MOSFETs (towards nanometer regime) are the
primary objectives. Limits of the state-of-the-art silicon device technology and key issues in the
miniaturization of devices are also integrated here. Alternative device structures (non-conventional
MOSFETs) and transport in novel nano-devices are also part of this course.
4. Pre-requisite:
_

Please Do Not Print Unless Necessary


BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE, Pilani
Pilani Campus
Instruction Division

Students, want to go through the course, only should have a little background of Electron Devices
[EEE/INSTR F214], and Physics & Modeling of Microelectronics Devices [MEL G631] (but may
not be too stringent !!)

5. Related Books:

[R1] S. M. Sze and K. K. Ng, Physics of Semiconductor Devices, Third Edition, Wiley, 2006.
[R2] Jean-Pierre Colinge (Ed), FinFETs and Other Multi-Gate Transistors, Springer, 2008
[R3] S. D. Brotherton, Introduction to Thin Film Transistors:Physics and Technology of TFTs,
Springer,2013

6. Course Plan:

Lect. Topic Learning Objective Refere


No. nces
Part I: Review of long channel MOSFETs
1-2 MOS Capacitor Device Physics Review the basic concepts of MOS R1
Device Physics.
3-4 Fundamental of MOSFETs Review the basic concepts of MOSFET
device structure, operation, I-V
characteristics, device modelling etc.
5-8 MOSFET Scaling: Short Channel Effects To realize the significance of Second
(SCEs), Mobility reduction, Subthreshold Order Effects on the device operation
Current, Channel Length Modulation, and other performance limitations of
Drain Induced Barrier Lowering (DIBL) conventional MOSFET due to the
and Finite Output Resistance. device scaling.
Part II: Nanoscale MOSFETs
9 Challenges of Nanoscale MOSFETs Down Scaling benefits and rules. R1
10-12 Limitations of Nanoscale MOSFETs: To realize the overall limitations of
Subthreshold Leakage, Threshold Voltage Nanoscale MOSFETs considering the
Variation, Mobility Degradation, Hot Channel, Gate, Drain/Source and
Carrier Effects, Source Drain Tunnelling, Substrate related issues individually.
Parasitic Resistance and Capacitance,
Reverse Biased Junction Leakage Current
etc.
Part III: Advanced MOSFETs
(Reduction of Short Channel Effects and Performance Enhancement Techniques)
13-18 Silicon-on-Insulator (SOI) MOSFETs: To gain the idea about Silicon-on- R1, R2
Fully Depleted (FD) SOI, Partially Insulator (SOI) devices and its &
Depleted (PD) SOI, Junction Less SOI. structures, manufacturing materials, Resea
operations, characterizations, rch
modelling and applications to control of Articl
short channel effects. es
19-24 Other Multigate SOI-MOSFETs: Double Study the advanced MOSFETs
_

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BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE, Pilani
Pilani Campus
Instruction Division

Gate, FinFET, π Gate, Ω Gate, Gate-All- structures and device characteristics to


Around (GAA) or surrounding gate, realize the advantages, drawbacks to
Silicon on Nothing (SON), Nanowire FET propose the possible solutions.
25-30 (i)Channel Engineering: Retrograde Study the complete device engineering
Substrate and Halo Doping profiles; towards more advanced MOSFET
(ii)Gate Engineering: High-k gate device structures.
dielectrics, Metal Gate-Stack;
(iii) Sorce/Drain (S/D) Engineering: S/D
Engineering of nanoscale double gate SOI
MOSFETs, Schottky-barrier S/D
Technology;
(iv) Material Engineering: high mobility
materials (e.g. Ge, GaAs/InGaAs etc.) for
channel of FET;
Part IV: Promising Nanodevices Beyond CMOS
31-33 Thin Film Transistors (TFT): Study the a-Si:H material, a-Si:H TFT R3
Hydrogenated amorphous silicon (a-Si:H) architecture, fabrication process, layout, &
TFT performance and characterizations. Resea
38-40 Impact-Ionization MOSFETs Development of fundamental concepts rch
(IMOSFETs); Tunnel FETs (TFETs); on IMOSFETs, TFETs, SBTFETs, Articl
Schottky-Barrier FETs (SBTFETs); CNTFET, OFET etc.. e(s)
Cabron Nanotube-FETs (CNTFETs);
Organic FETs(OFETs)

7. Other Home and Reading Assignments: These will be specified from time to time.

8. Evaluation Scheme:

Component Duration Marks Date and Time Remarks


Mid Sem Test 90 Mints. 70 9/10 4:00 - 5:30 OB
PM
Assignment Test(s) (Continuous) 20 To be announced Demo / test
Comprehensive 3 hrs 110 2/12 AN CB/OB
TOTAL 200

9. Chamber Consultation Hour: To be announced in Class ([email protected])


10. Make-up Policy: Make-up will be given on extremely genuine grounds only. Prior application
should be made for seeking the make-up examination.
11. Notices: Notices, if any, concerning the course will be put up on EEE Notice Board.

Instructor In Charge
EEE G594

Please Do Not Print Unless Necessary

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