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Cpu

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Hamza Waqas
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6 views2 pages

Cpu

Uploaded by

Hamza Waqas
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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module cpu (

output reg [3:0] acc,


input clk,
input reset
);

reg [3:0] PC;


reg [7:0] IR;
reg [3:0] regA;
reg [7:0] memory [0:7];

wire [3:0] opcode;


wire [3:0] address;
wire [3:0] value;
assign opcode = IR[7:4];
assign address = IR[3:0];
assign value = memory[address];

reg [1:0] state;


localparam FETCH = 2'b00,
DECODE = 2'b01,
EXECUTE = 2'b10;

always @(posedge clk or posedge reset) begin


if (reset) begin
PC <= 0;
IR <= 0;
regA <= 0;
state <= FETCH;
end else begin
case (state)
FETCH: begin

IR <= memory[PC];
PC <=PC + 1;

state <= DECODE;


end
DECODE: begin

state <= EXECUTE;


end
EXECUTE: begin

case (opcode)
4'b0000: regA <= 4'b0010 + value;
4'b1111: regA <= regA;
default: regA <= 4'b0000;
endcase

state <= FETCH;


end
endcase
end
end
always @(posedge clk) begin
acc <= regA;
$display("time=%d | PC=%d | opcode=%b | value=%d | regA=%d | acc=%d",
$time, PC, opcode, value, regA, acc);
end

initial begin
memory[0] = 8'b00000001;
memory[1] = 8'b00000010;
memory[2] = 8'b11110000;
end
endmodule

module tb_cpu;
reg clk;
reg reset;
wire [3:0] acc;

// Instantiate the CPU module


cpu uut (
.acc(acc),
.clk(clk),
.reset(reset)
);

// Clock generation
initial begin
clk = 0;
forever #5 clk = ~clk;
end

// Reset logic
initial begin
reset = 1;
#10 reset = 0;
#200;
end
endmodule

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