NITTE MEENAKSHI

INSTITUTE OF TECHNOLOGY
Yelahanka, Bangalore- 560064, Karnataka- India.
An Autonomous Institution with A+ Grade by NAAC UGC, Approved by VTU, UGC, AICTE, Govt. of India.

Department of VLSI Design and Technology

AY: 2023-2024

Linux and Scripting (SCC-10)

A Report on Analog and Digital Circuits Design using EDA

Submitted By

Aditya Dwivedi 1NT23VL004

Under the Guidance of

Dr. Thimmaraja Yadava G
Associate Professor
 Contents
List of Figures……………………………………………………..………..02
List of Tables………………………………………………………………. 03
1. Design of Analog Circuits using Cadence……………………………… 04
1.1 Title of the Experiment…………………………………………….….. .04
1.2 Theory…………………………………………………………………. .04
1.3 Procedural Steps………………………………………………………...06
1.4 Schematic, Symbol and Test Schematic Diagrams…………………..... .08
1.5 Analog Libraries Specification……………………………………..…. .09
1.6 Simulation Results…………………………………………………..…. 10
1.7 Conclusion…………………………………………………………...…..11
2. Design of Digital Circuits using IRUN/NCLAUNCH/TCL
Scripting………………………………………….……………………... .12
2.1 Title of the Experiment………………………………………………. ..12
2.2 Theory………………………………………………………………. …12
2.3 Procedural Steps………………………………………………………..13
2.4 Simulation Results……………………………………………………. .16
2.5 Conclusion……………………………………………………………...19
References………………………………………………………………….20

1|Page
List of Figures
Figure 1.1: Steps involved in the realization of circuits using cadence…………….5

Figure 1.2: virtuoso window.………………………………………………..……...6

Figure 1.3: library window…………………………………………………..……...7

Figure 1.4:attach library to technology……………………………………………..7

Figure 1.5: new file………………………………………………………..………..8

Figure 1.6: symbol of CMOS inverter……………………………….……………..8

Figure 1.7: Schematic of CMOS inverter………………………….……………….9

Figure 1.8: Test schematic of CMOS inverter…………………….……….……….9

Figure 1.9output plot 01…………………………………………………..………..10

Figure 1.10: output plot 02……………………………………….………..……….11

Figure 2.1: Logic gates……….…………………………………….……..………..12

Figure 2.2: AND simulation……….………………………………..………..…….16

Figure 2.3: NAND simulation……..……………………....………………...……..16

Figure 2.4: NOR simulation………………………………..……………..…….….16

Figure 2.5: OR gate ………………………………………………………….…….17

2|Page
List of Tables
For Example,

Table 1.1 Analog library specification ………………………………………………...10

Table 1.2 components …………………………………………………………………10

3|Page
Chapter 1

Design of Analog Circuits using Cadence

1.1 Realization of CMOS inverter in cadence tool
1.2 Theory
Cadence virtuoso is a tool used for creation and verification of digital integrated circuits its
widely used in the semiconductor industry for its powerful capabilities in schematic capture,
simulation, layout and verification. It provides with a user friendly and intuitive graphical
interface with multiple

1.2.1 Overview of Cadence Virtuoso Environment

 Library and Cell Management- Virtuoso uses a hierarchical design methodology where
designs are organized into libraries containing cells. Each cell can represent a
schematic, symbol, layout, or simulation view of a circuit.

 Schematic Capture-The Schematic Editor is used to draw the circuit schematics,

allowing designers to place components like transistors, resistors, capacitors, and other
elements. It supports hierarchical design, enabling the creation of complex circuits by
nesting simpler blocks.

 Simulation and Analysis - Virtuoso integrates with various simulation tools to perform
different types of analyses, including DC, AC, transient, noise, and parametric sweeps.
Simulation results can be visualized using the Waveform Viewer, which allows for
detailed inspection and measurement of signals.

 Layout Design - The Layout Editor enables the physical design of ICs, where designers
create the geometric representation of the circuit that will be fabricated. It includes tools
for placing and routing components, as well as performing design rule checks (DRC)
to ensure the layout adheres to fabrication constraints.

 Verification- Virtuoso provides robust verification tools, including Layout Versus

Schematic (LVS) to ensure the layout matches the schematic, and parasitic extraction
to account for real-world effects. The Design Rule Check (DRC) tool ensures the layout
meets all manufacturing guidelines.

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1.2.2 Steps involved in the realization of analog circuits using
cadence

Circuit
Simulation Verification
Design

Fig 1.1

1.2.3 Importance of cadence in the field of VLSI

Cadence Virtuoso plays a crucial role in the field of VLSI due to its comprehensive set of
tools designed to handle the complexities of modern IC design. Here are some key points
highlighting its importance:

 Integrated Design Environment

Cadence Virtuoso offers an integrated environment that combines schematic capture,
simulation, layout, and verification tools. This integration streamlines the design
process, reduces the risk of errors, and enhances productivity.

 Support for Advanced Technologies

Cadence Virtuoso offers an integrated environment that combines schematic capture,
simulation, layout, and verification tools. This integration streamlines the design
process, reduces the risk of errors, and enhances productivity.

 Analog and Mixed-Signal Design Capabilities

Virtuoso is renowned for its robust analog and mixed-signal design capabilities. It
provides specialized tools for designing high-precision analog circuits, including
operational amplifiers, filters, and data converters, which are critical in various
applications such as telecommunications, automotive, and consumer electronics.

 Customization and Automation

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 The platform supports extensive customization and automation through scripting and
programmable interfaces. Designers can create custom scripts to automate repetitive
tasks, optimize design flows, and enhance productivity.

 Verification and Validation

Cadence Virtuoso includes powerful verification tools like Layout Versus Schematic
(LVS) and Design Rule Check (DRC), which ensure that designs meet all specified
requirements and are manufacturable. The inclusion of parasitic extraction tools
allows for accurate post-layout simulation, which is crucial for predicting real-world
performance.

 Collaboration and Reusability

The hierarchical design methodology in Virtuoso promotes design reuse and
collaboration. Teams can work on different parts of the design simultaneously and
integrate them seamlessly, enhancing efficiency and reducing time to market.

 Support for Large and Complex Designs

As VLSI designs become increasingly complex, involving billions of transistors,
Cadence Virtuoso provides the scalability and performance needed to handle large
designs efficiently. It offers advanced features for managing complexity, such as
hierarchical design, parameterized cells, and advanced routing algorithms.

 Industry Standard
Cadence Virtuoso is widely adopted in academia and industry, making it a de facto
standard for VLSI design. Its widespread use ensures that students and professionals
are well-equipped with the skills needed for careers in semiconductor design.

1.3 Procedural Steps

1. launch virtuoso
 Open terminal and type “virtuoso”

Fig 1.2

2. Create a new library

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  In the Library Manager, execute File - New – Library. The new library
form appears

Fig 1.3

 In the ―New Library dialog box, Name ― inverter in the Name section.
And select the option in Technology file – “Attach to an existing
technology library “then click OK.

Fig 1.4

 Attach library to Technology Library’ form appears, select

gpdk90/180/45 from the Technology Library and click OK

3. Creating a schematic cell view

 In the CIW or Library manager, execute File – New – Cell view. “New
file” form appears.
Library inverter
Cell Inv_1x
View Schematic
Open with Schematics L

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 Fig 1.5

1.4 Schematic, Symbol and Test Schematic Diagrams

1.4.1 Symbol

fig 1.6
1.4.2 Schematic

8|Page
 fig 1.7

Test schematic

Fig 1.8

1.5 Analog Libraries Specification

 While adding the pins, make sure to specify them correctly
9|Page
 Vdd input
Vss input
Vin input
Vout output

Table 1.1

 Add the following components to the schematic

Library Cell view Properties/commands
name name
analoglib Vpulse DCvoltage:1.8v;
V1:0;V2:1;Period:20n,Delay
time:1n,Rise time:10n,Fall
time10n,Pulse width:10n
analoglib Vdc Vdc=1
analoglib gnd

Table 1.2

1.6 Simulation Results

Fig 1.9

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 Fig 1.10

1.7 Conclusion

The realization of a CMOS inverter using the Cadence tool suite provides a comprehensive
understanding of both the theoretical and practical aspects of digital circuit design. This step-
by-step process involving in design, simulation, and validation of a fundamental digital logic
component, the CMOS inverter. Through this project, we gained an in-depth understanding of
CMOS technology, including the operation and characteristics of PMOS and NMOS
transistors, which is crucial for further exploration and design of more complex digital circuits.
The project illustrated the complete design flow, starting from creating the inverter schematic
to generating the symbol and setting up the test schematic for simulation, emphasizing the
importance of each step and how they contribute to the successful realization of the circuit.

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Chapter 2

Design of Digital Circuits using

IRUN/NCLAUNCH/TCL Scripting

2.1 Realization of various gates using IRUN/NCLAUNCH

2.1.1 Theory

Realizing various logic gates using NCLaunch and iRUN involves understanding the principles
of digital logic design, HDL (Hardware Description Language) coding, and simulation.
NCLaunch is a graphical user interface for managing simulation tasks in the Cadence tool suite,
while iRUN is a command-line tool that automates the compilation, elaboration, and simulation
processes. Here’s a theoretical overview:

 Introduction to logic gates

Logic gates are the fundamental building blocks of digital circuits. Each gate performs
a basic logical function and is implemented using transistors in VLSI design. Common logic
gates include AND, OR, NOT, NAND and NOR gates. These gates are combined to create
more complex digital circuits.

Fig 2.1

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  Hardware description language

Hardware Description Languages (HDLs) like Verilog and VHDL are essential tools in digital
circuit design, allowing engineers to describe the structure, behavior, and timing of electronic
circuits. HDLs enable precise modeling, simulation, and verification of complex designs,
facilitating efficient development and implementation in VLSI systems.

2.1.2 Procedural steps

Create HDL Files:

 Write Verilog or VHDL code to describe the logic gates (e.g., AND, OR, NOT,
NAND, NOR, XOR, XNOR) and their interconnections.

Design Testbenches:

 Develop testbenches to apply input stimuli and verify the outputs of each gate under
different conditions.

Project Setup in NCLaunch:

 Launch NCLaunch and create a new project.

 Add the HDL files (design and testbench) to the project directory.

Compile and Elaborate:

 Use iRUN to compile and elaborate the HDL files, ensuring syntax and semantic
correctness.

Simulation Setup:

 Configure simulation options such as time step, initial conditions, and output file
format in NCLaunch.

Run Simulation:

 Execute the simulation using NCLaunch to generate waveform outputs based on the
testbench inputs.

Waveform Analysis:

 Use SimVision (Cadence's waveform viewer) to analyse simulation results.

 Verify the expected behaviour of each gate by comparing simulated waveforms with
predicted outputs.

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Debug and Iterate:

 Identify and resolve any discrepancies between simulated and expected results
through debugging.
 Make necessary adjustments to the HDL code and repeat simulation until desired
functionality is achieved.

2.1.3 Verilog codes

 AND Gate

and.v and_test.v

module and(a,b,y); module and_test;

input a,b; reg a,b;
output y; wire y;
supply1 vdd; and a1(a,b,y);
supply0 vss; initial begin;
wire s1,y1; a=0;b=0;
pmos p0(y1,vdd,a); #2 b=1; #2 a=1;b=0; #2 b=1; #2;
pmos p1(y1,vdd,b); #2 a=1;b=0;
pmos p2(y,vdd,y1); #2 b=1;
nmos n0(y1,s1,a); #2;
nmos n1(s1,vss,b); end
nmos n2(y,vss,y1); end module
endmodule

 NAND Gate

nand.v nand_test.v

module nandgate(a,b,y); module nandgatet;

input a,b; reg a,b;
output y; wire y;
supply1 vdd; nandgate n1(a,b,y);
supply0 vss; initial begin
wire s1; a=0;b=0;
pmos p0(y,vdd,a); #2 b=1;
pmos p1(y,vdd,b); #2 a=1;b=0;
nmos n0(y,s1,a); #2 b=1;
nmos n1(s1,vss,b); #2;
endmodule end
endmodule

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 NOR Gate

nor.v nor_test.v

module norgate(a,b,y); module norgatet;

input a,b; reg a,b;
output y; wire y;
supply1 vdd; norgate n1(a,b,y);
supply0 vss; initial begin
wire s1; a=0;b=0;
pmos p0(s1,vdd,a); #2 b=1;
pmos p1(y,s1,b); #2 a=1;b=0;
nmos n0(y,vss,a); #2 b=1;
nmos n1(y,vss,b); #2;
endmodule end
endmodule

 OR Gate

or.v or_test.v

module orgate(a,b,y); module orgatet;

input a,b; reg a,b;
output y; wire y;
supply1 vdd; orgate o1(a,b,y);
supply0 vss; initial begin
wire s1,y1; a=0;b=0;
pmos p0(s1,vdd,a); #2 b=1;
pmos p1(y1,s1,b); #2 a=1;b=0;
pmos p2(y,vdd,y1); #2 b=1;
nmos n0(y1,vss,a); #2;
nmos n1(y1,vss,b); end
nmos n2(y,vss,y1); endmodule
endmodule

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2.1.4 simulation results

 AND Gate

Fig 2.2
 NAND Gate

Fig 2.3
 NOR Gate

Fig 2.4

 OR Gate

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 Fig 2.5

2.2 Realization of Boolean expression

2.2.1 Theory

A Boolean expression is a mathematical notation used to represent logical operations and

their outcomes. These expressions use Boolean algebra, a branch of algebra that deals with
variables and operators that have two possible values: true (1) and false (0). Boolean
expressions are fundamental in the design and analysis of digital circuits and computer
systems, as they provide a concise way to describe how logic gates and circuits operate.

2.2.2 Standard Design Constraints

Filename: constraints_top.sdc

create_clock -name clk -period 2 -waveform {0 1} [get_ports "clk"]

set_clock_transition -rise 0.1 [get_clocks "clk"]

set_clock_transition -fall 0.1 [get_clocks "clk"]

2.2.3 TCL Script for Realizing the Circuits and Boolean Expressions
Filename: run.tcl

set_attribute init_lib_search_path /home/install/FOUNDRY/digital/90nm/dig/lib/

set_attribute lef_library /home/install/FOUNDRY/digital/90nm/dig/lef/gsclib090_translated.lef

set_attribute library slow.lib

read_hdl {./boolean1.v}

elaborate

read_sdc ./constraints_top.sdc

set_attribute syn_generic_effort medium

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set_attribute syn_map_effort medium

set_attribute syn_opt_effort medium

syn_generic

syn_map

syn_opt

2.2.4 Examples of different Boolean expressions

y=ab̅+c
Verilog Code – Filename: boolean.v
module boolean(a,b,c,y);
input a,b,c;
output y;
wire s1,s2;
not(s1,b);
and(s2,a,s1);
assign y = s2|c;
endmodule

y=A̅B̅+C̅D̅
Verilog Code - Filename: boolean1.v
module boolean1(A,B,C,D,Y);
input A,B,C,D;
output Y;
wire s1,s2;
nand(s1,A,B);
nand(s2,C,D);
assign y = s1|s2;
endmodule

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 2:1 Mux(Y = DOS̅ + D1S̅)
Verilog Code - Filename: mux21
module mux21(D0,D1,S,Y);
input D0,D1,S;
output Y;
wire sb,a,b;
not(sb,S);
and(a,sb,D0);
and(b,S,D1);
or(Y,a,b);
endmodule

2.2.5 Conclusion
This report has explored the use of NCLaunch and iRUN tools for the design, simulation, and
verification of logic gates and Boolean expressions. By utilizing Hardware Description
Languages (HDLs) such as Verilog, we developed accurate representations of fundamental
logic gates including AND, OR, NOT, NAND and NOR. The use of NCLaunch provided an
intuitive interface for managing and visualizing our simulation tasks, while iRUN facilitated
an efficient command-line workflow for compiling, elaborating, and running our simulations.

The hands-on experience with NCLaunch and iRUN underscored their effectiveness in
managing the complexity of digital circuit design and verification. We were able to debug and
optimize our designs, gaining deeper insights into the behavior of digital circuits and the
application of Boolean algebra in real-world scenarios. The process also enhanced our
problem-solving skills, reinforcing the importance of meticulous design and thorough testing

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References
[1] EECS Department, University of Michigan, "Cadence Virtuoso Tutorial," 2009.
[Online]. Available:
https://www.eecs.umich.edu/courses/eecs522/w09/public/CadenceTutorial1W09.pdf.
[2] TutorialsPoint, "Logic Gates," 2024. [Online]. Available:
https://www.tutorialspoint.com/computer_logical_organization/logic_gates.htm.
[3] W. Millan, A. Clark, and E. Dawson, "Boolean Function Design Using Hill Climbing
Methods," in Information Security and Privacy. ACISP 1999, J. Pieprzyk, R. Safavi-
Naini, and J. Seberry, Eds., Lecture Notes in Computer Science, vol. 1587, Springer,
Berlin, Heidelberg, 1999, pp. 1-15. DOI: 10.1007/3-540-48970-3_1.
[4] Mastering TCL/TK:
rd
A Comprehensive Guide to the TCL programming language –[Brent
B. Welch]- 3 Edition
[5] TCL Programming for Beginners: A Hands-On Guide-[Kevin T. Smith]-6 th Edition

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